/******************************************************************************
* @fn HalUARTPollDMA
*
* @brief Poll a USART module implemented by DMA, including the hybrid solution in which the Rx
* is driven by DMA but the Tx is driven by ISR.
*
* @param none
*
* @return none
*****************************************************************************/
static void HalUARTPollDMA(void)
{
uint8 evt = 0;
uint16 cnt;
#if DMA_PM
PxIEN &= ~DMA_RDYIn_BIT; // Clear to not race with DMA_RDY_IN ISR.
{
if (dmaRdyIsr || HAL_UART_DMA_RDY_IN() || HalUARTBusyDMA())
{
// Master may have timed-out the SRDY asserted state & may need a new edge.
#if HAL_UART_TX_BY_ISR
if (!HAL_UART_DMA_RDY_IN() && (dmaCfg.txHead != dmaCfg.txTail))
#else
if (!HAL_UART_DMA_RDY_IN() && ((dmaCfg.txIdx[0] != 0) || (dmaCfg.txIdx[1] != 0)))
#endif
{
HAL_UART_DMA_CLR_RDY_OUT();
}
dmaRdyIsr = 0;
if (dmaRdyDly == 0)
{
(void)osal_set_event(Hal_TaskID, HAL_PWRMGR_HOLD_EVENT);
}
if ((dmaRdyDly = ST0) == 0) // Reserve zero to signify that the delay expired.
{
dmaRdyDly = 0xFF;
}
HAL_UART_DMA_SET_RDY_OUT();
}
else if ((dmaRdyDly != 0) && (!DMA_PM_DLY || ((uint8)(ST0 - dmaRdyDly) > DMA_PM_DLY)))
{
dmaRdyDly = 0;
(void)osal_set_event(Hal_TaskID, HAL_PWRMGR_CONSERVE_EVENT);
}
}
PxIEN |= DMA_RDYIn_BIT;
#endif
#if !HAL_UART_TX_BY_ISR
HalUARTPollTxTrigDMA();
#endif
cnt = HalUARTRxAvailDMA(); // Wait to call until after the above DMA Rx bug work-around.
#if HAL_UART_DMA_IDLE
if (dmaCfg.rxTick)
{
// Use the LSB of the sleep timer (ST0 must be read first anyway) to measure the Rx timeout.
if ((ST0 - dmaCfg.rxTick) > HAL_UART_DMA_IDLE)
{
dmaCfg.rxTick = 0;
evt = HAL_UART_RX_TIMEOUT;
}
}
else if (cnt != 0)
{
if ((dmaCfg.rxTick = ST0) == 0) // Zero signifies that the Rx timeout is not running.
{
dmaCfg.rxTick = 0xFF;
}
}
#else
if (cnt != 0)
{
evt = HAL_UART_RX_TIMEOUT;
}
#endif
if (cnt >= HAL_UART_DMA_FULL)
{
evt |= HAL_UART_RX_FULL;
}
else if (cnt >= HAL_UART_DMA_HIGH)
{
evt |= HAL_UART_RX_ABOUT_FULL;
if (!DMA_PM && (UxUCR & UCR_FLOW))
{
HAL_UART_DMA_CLR_RDY_OUT(); // Disable Rx flow.
}
}
if (dmaCfg.txMT)
{
dmaCfg.txMT = FALSE;
evt |= HAL_UART_TX_EMPTY;
}
if ((evt != 0) && (dmaCfg.uartCB != NULL))
{
dmaCfg.uartCB(HAL_UART_DMA-1, evt);
}
if (DMA_PM && (dmaRdyDly == 0) && !HalUARTBusyDMA())
{
HAL_UART_DMA_CLR_RDY_OUT();
}
}
/******************************************************************************
* @fn HalUARTPollDMA
*
* @brief Poll a USART module implemented by DMA.
*
* @param none
*
* @return none
*****************************************************************************/
static void HalUARTPollDMA(void)
{
uint16 cnt = 0;
uint8 evt = 0;
if (HAL_UART_DMA_NEW_RX_BYTE(dmaCfg.rxHead))
{
rxIdx_t tail = findTail();
// If the DMA has transferred in more Rx bytes, reset the Rx idle timer.
if (dmaCfg.rxTail != tail)
{
dmaCfg.rxTail = tail;
// Re-sync the shadow on any 1st byte(s) received.
if (dmaCfg.rxTick == 0)
{
dmaCfg.rxShdw = ST0;
}
dmaCfg.rxTick = HAL_UART_DMA_IDLE;
}
else if (dmaCfg.rxTick)
{
// Use the LSB of the sleep timer (ST0 must be read first anyway).
uint8 decr = ST0 - dmaCfg.rxShdw;
if (dmaCfg.rxTick > decr)
{
dmaCfg.rxTick -= decr;
dmaCfg.rxShdw = ST0;
}
else
{
dmaCfg.rxTick = 0;
}
}
cnt = HalUARTRxAvailDMA();
}
else
{
dmaCfg.rxTick = 0;
}
if (cnt >= HAL_UART_DMA_FULL)
{
evt = HAL_UART_RX_FULL;
}
else if (cnt >= HAL_UART_DMA_HIGH)
{
evt = HAL_UART_RX_ABOUT_FULL;
PxOUT |= HAL_UART_Px_RTS; // Disable Rx flow.
}
else if (cnt && !dmaCfg.rxTick)
{
evt = HAL_UART_RX_TIMEOUT;
}
if (dmaCfg.txMT)
{
dmaCfg.txMT = FALSE;
evt |= HAL_UART_TX_EMPTY;
}
if (dmaCfg.txShdwValid)
{
uint8 decr = ST0;
decr -= dmaCfg.txShdw;
if (decr > dmaCfg.txTick)
{
// No protection for txShdwValid is required
// because while the shadow was valid, DMA ISR cannot be triggered
// to cause concurrent access to this variable.
dmaCfg.txShdwValid = FALSE;
}
}
if (dmaCfg.txDMAPending && !dmaCfg.txShdwValid)
{
// UART TX DMA is expected to be fired and enough time has lapsed since last DMA ISR
// to know that DBUF can be overwritten
halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_DMA_CH_TX);
halIntState_t intState;
// Clear the DMA pending flag
dmaCfg.txDMAPending = FALSE;
HAL_DMA_SET_SOURCE(ch, dmaCfg.txBuf[dmaCfg.txSel]);
HAL_DMA_SET_LEN(ch, dmaCfg.txIdx[dmaCfg.txSel]);
dmaCfg.txSel ^= 1;
HAL_ENTER_CRITICAL_SECTION(intState);
HAL_DMA_ARM_CH(HAL_DMA_CH_TX);
do
{
asm("NOP");
} while (!HAL_DMA_CH_ARMED(HAL_DMA_CH_TX));
HAL_DMA_CLEAR_IRQ(HAL_DMA_CH_TX);
HAL_DMA_MAN_TRIGGER(HAL_DMA_CH_TX);
HAL_EXIT_CRITICAL_SECTION(intState);
}
else
{
halIntState_t his;
HAL_ENTER_CRITICAL_SECTION(his);
if ((dmaCfg.txIdx[dmaCfg.txSel] != 0) && !HAL_DMA_CH_ARMED(HAL_DMA_CH_TX)
&& !HAL_DMA_CHECK_IRQ(HAL_DMA_CH_TX))
{
HAL_EXIT_CRITICAL_SECTION(his);
HalUARTIsrDMA();
}
else
{
HAL_EXIT_CRITICAL_SECTION(his);
}
}
if (evt && (dmaCfg.uartCB != NULL))
{
dmaCfg.uartCB(HAL_UART_DMA-1, evt);
}
}