Ejemplo n.º 1
0
_mqx_int _bsp_adc_channel_io_init
(
     /* [IN] number of channel on which to perform hardware initialization */
    uint_16   source
)
{
    uint_8 ch = ADC_GET_CHANNEL(source);
    uint_8 mux = ADC_GET_MUXSEL(source);
    uint_8 gpio_port;
    PORT_MemMapPtr pctl = NULL;

    #define ADC_SIG_PORTA   (0x01 << 5)
    #define ADC_SIG_PORTB   (0x02 << 5)
    #define ADC_SIG_PORTC   (0x03 << 5)
    #define ADC_SIG_PORTD   (0x04 << 5)
    #define ADC_SIG_PORTE   (0x05 << 5)
    #define ADC_SIG_NA      (0x00) /* signal not available */
    #define ADC_SIG_NC      (0x01) /* signal not configurable */

    /* Conversion table for ADC0x inputs, where x is 0 to 23, mux is defaultly "B" */
    const static uint_8 adc0_conv_table[] = {
        ADC_SIG_NC, //0 leave as default
        ADC_SIG_NC, //1 leave as default
        ADC_SIG_NC, //2 leave as default
        ADC_SIG_NC, //3 leave as default
        ADC_SIG_PORTC | 2, //4b
        ADC_SIG_PORTD | 1, //5b
        ADC_SIG_PORTD | 5, //6b
        ADC_SIG_PORTD | 6, //7b
        ADC_SIG_PORTB | 0, //8
        ADC_SIG_PORTB | 1, //9
        ADC_SIG_PORTA | 7, //10
        ADC_SIG_PORTA | 8, //11
        ADC_SIG_PORTB | 2, //12
        ADC_SIG_PORTB | 3, //13
        ADC_SIG_PORTC | 0, //14
        ADC_SIG_PORTC | 1, //15
        ADC_SIG_NC, //16 conflict in K60 Sub-Family Reference Manual, Rev. 5, table 3.7.1.3.1 and 10.3.1
        ADC_SIG_PORTE | 24, //17
        ADC_SIG_PORTE | 25, //18
        ADC_SIG_NC, //19 ADC0_DM0, leave as default
        ADC_SIG_NC, //20 ADC0_DM1, leave as default
        ADC_SIG_NC, //21 conflict in K60 Sub-Family Reference Manual, Rev. 5, table 3.7.1.3.1 and 10.3.1
        ADC_SIG_NC, //22 conflict in K60 Sub-Family Reference Manual, Rev. 5, table 3.7.1.3.1 and 10.3.1
        ADC_SIG_NC, //23 DAC0, leave as default
        ADC_SIG_NA, //24 not implemented
        ADC_SIG_NA, //25 not implemented
        //below: use ADC_SIG_NC (leave as default)
    };

    /* Conversion table for ADC1x, where x is 0 to 23, mux is defaultly "B" (or nothing) */
    const static uint_8 adc1_conv_tableB[] = {
        ADC_SIG_NC, //0 leave as default
        ADC_SIG_NC, //1 leave as default
        ADC_SIG_NC, //2 leave as default
        ADC_SIG_NC, //3 leave as default
        ADC_SIG_PORTC | 8, //4b
        ADC_SIG_PORTC | 9, //5b
        ADC_SIG_PORTC | 10, //6b
        ADC_SIG_PORTC | 11, //7b
        ADC_SIG_PORTB | 0, //8
        ADC_SIG_PORTB | 1, //9
        ADC_SIG_PORTB | 4, //10
        ADC_SIG_PORTB | 5, //11
        ADC_SIG_PORTB | 6, //12
        ADC_SIG_PORTB | 7, //13
        ADC_SIG_PORTB | 10, //14
        ADC_SIG_PORTB | 11, //15
        ADC_SIG_NC, //16
        ADC_SIG_PORTA | 17, //17
        ADC_SIG_NC, //18 VREF, leave as default
        ADC_SIG_NC, //19 ADC1_DM0, leave as default
        ADC_SIG_NC, //20 ADC1_DM1, leave as default
        ADC_SIG_NA, //21 not implemented
        ADC_SIG_NA, //22 not implemented
        ADC_SIG_NC, //23 DAC1, leave as default
        ADC_SIG_NA, //24 not implemented
        ADC_SIG_NA, //25 not implemented
        //below: use ADC_SIG_NC (leave as default)
    };

    /* Conversion table for ADC1x, where x is 4 to 7, mux is "A" */
    const static uint_8 adc1_conv_tableA[] = {
        ADC_SIG_PORTE | 0, //4a
        ADC_SIG_PORTE | 1, //5a
        ADC_SIG_PORTE | 2, //6a
        ADC_SIG_PORTE | 3, //7a
    };

    if (ADC_GET_DIFF(source) && ch > 3)
        return IO_ERROR; /* signal not available */

    if (ADC_GET_DIFF(source) == 0 && ch == 2)
        return IO_ERROR; /* channel 2 (PGA) can be used only as a diff pair */

    if (ch < 26) {
        if (ADC_GET_MODULE(source) == ADC_SOURCE_MODULE(1)) {
            /* Get result for module 0 */
           gpio_port = adc0_conv_table[ch];
        }
        else {
            if ((ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_B) || (ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_X))
            /* Get result for module 1, if user wants "B" channel or any channel */
                gpio_port = adc1_conv_tableB[ch];
            else {
                /* Get result for module 1, if user wants "A" channel or any other */
                if (ch < 4 || ch > 7)
                    gpio_port = ADC_SIG_NA;
                else
                    gpio_port = adc1_conv_tableA[ch - 4];
            }
        }
    }
    else
        gpio_port = ADC_SIG_NC;

    if (gpio_port == ADC_SIG_NA)
        return IO_ERROR; /* signal not available */
    if (gpio_port == ADC_SIG_NC)
        return IO_OK; /* no need to configure signal */
    switch (gpio_port >> 5) {
        case 1: /* PORTA */
            pctl = (PORT_MemMapPtr) PORTA_BASE_PTR;
            break;
        case 2: /* PORTB */
            pctl = (PORT_MemMapPtr) PORTB_BASE_PTR;
            break;
        case 3: /* PORTC */
            pctl = (PORT_MemMapPtr) PORTC_BASE_PTR;
            break;
        case 4: /* PORTD */
            pctl = (PORT_MemMapPtr) PORTD_BASE_PTR;
            break;
        case 5: /* PORTE */
            pctl = (PORT_MemMapPtr) PORTE_BASE_PTR;
            break;
        /* There is no possibility to get other port from table */
    }
    pctl->PCR[gpio_port & 0x1F] &= ~PORT_PCR_MUX_MASK; /* set pin's multiplexer to analog */

    return IO_OK;
}
Ejemplo n.º 2
0
_mqx_int _bsp_adc_channel_io_init
(
     /* [IN] number of channel on which to perform hardware initialization */
    uint_16   source
)
{
    uint_8 ch = ADC_GET_CHANNEL(source);
    uint_8 mux = ADC_GET_MUXSEL(source);
    uint_8 gpio_port;
    PORT_MemMapPtr pctl;

    #define ADC_SIG_PORT_SHIFT (5)
    #define ADC_SIG_PORTA   (0x01 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_PORTB   (0x02 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_PORTC   (0x03 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_PORTD   (0x04 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_PORTE   (0x05 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_PORTF   (0x06 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_NA      (0x00) /* signal not available */
    #define ADC_SIG_NC      (0x01) /* signal not configurable */



/* Conversion table for ADC0x inputs, where x is 0 to 23, mux is defaultly "B" OR "X" */
    const static uint_8 adc0_conv_table_bx[] = {
        ADC_SIG_NC,         //0 leave as default
        ADC_SIG_NC,         //1 leave as default
        ADC_SIG_NC,         //2 leave as default
        ADC_SIG_NC,         //3 leave as default
        ADC_SIG_PORTC | 2,  //ADC0_SE4b/CMP1_IN0/TSI0_CH15
        ADC_SIG_PORTD | 1,  //ADC0_SE5b
        ADC_SIG_PORTD | 5,  //ADC0_SE6b
        ADC_SIG_PORTD | 6,  //ADC0_SE7b
        ADC_SIG_PORTB | 0,  //ADC0_SE8/ADC1_SE8/ADC2_SE8/ADC3_SE8/TSI0_CH0
        ADC_SIG_PORTB | 1,  //ADC0_SE9/ADC1_SE9/ADC2_SE9/ADC3_SE9/TSI0_CH6
        ADC_SIG_PORTA | 7,  //ADC0_SE10
        ADC_SIG_PORTA | 8,  //ADC0_SE11
        ADC_SIG_PORTB | 2,  //ADC0_SE12/TSI0_CH7
        ADC_SIG_PORTB | 3,  //ADC0_SE13/TSI0_CH8
        ADC_SIG_PORTC | 0,  //ADC0_SE14/TSI0_CH13
        ADC_SIG_PORTC | 1,  //ADC0_SE15/TSI0_CH14
        ADC_SIG_NC,         //ADC0_SE16/CMP1_IN2/ADC0_SE21
        ADC_SIG_PORTE | 24, //ADC0_SE17/EXTAL1
        ADC_SIG_PORTE | 25, //ADC0_SE18/XTAL1
        ADC_SIG_NA,         //19 not implemented
        ADC_SIG_NA,         //20 not implemented
        ADC_SIG_NC,         //ADC0_SE16/CMP1_IN2/ADC0_SE21
        ADC_SIG_NC,         //ADC1_SE16/CMP2_IN2/ADC0_SE22
        ADC_SIG_NC            //DAC0_OUT/CMP1_IN3/ADC0_SE23
    };

    /* Conversion table for ADC0x inputs, where x is 4 to 7, mux is defaultly "A" */
    const static uint_8 adc0_conv_table_a[] = {
        ADC_SIG_PORTE | 16, //ADC0_SE4a
        ADC_SIG_PORTE | 17, //ADC0_SE5a
        ADC_SIG_PORTE | 18, //ADC0_SE6a
        ADC_SIG_PORTE | 19   //ADC0_SE7a
    };

    /* Conversion table for ADC1x inputs, where x is 0 to 23, mux is defaultly "B" OR "X"*/
    const static uint_8 adc1_conv_table_bx[] = {
        ADC_SIG_NC,         //0 leave as default
        ADC_SIG_NC,         //1 leave as default
        ADC_SIG_NC,         //2 leave as default
        ADC_SIG_NC,         //3 leave as default
        ADC_SIG_PORTC | 8,  //ADC1_SE4b/CMP0_IN2
        ADC_SIG_PORTC | 9,  //ADC1_SE5b/CMP0_IN3
        ADC_SIG_PORTC | 10, //ADC1_SE6b
        ADC_SIG_PORTC | 11, //ADC1_SE7b
        ADC_SIG_PORTB | 0,  //ADC0_SE8/ADC1_SE8/ADC2_SE8/ADC3_SE8/TSI0_CH0
        ADC_SIG_PORTB | 1,  //ADC0_SE9/ADC1_SE9/ADC2_SE9/ADC3_SE9/TSI0_CH6
        ADC_SIG_PORTB | 4,  //ADC1_SE10
        ADC_SIG_PORTB | 5,  //ADC1_SE11
        ADC_SIG_PORTB | 6,  //ADC1_SE12
        ADC_SIG_PORTB | 7,  //ADC1_SE13
        ADC_SIG_PORTB | 10, //ADC1_SE14
        ADC_SIG_PORTB | 11, //ADC1_SE15
        ADC_SIG_NC,         //ADC1_SE16/CMP2_IN2/ADC0_SE22
        ADC_SIG_PORTA | 17, //ADC1_SE17
        ADC_SIG_NC,         //VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
        ADC_SIG_NA,         //19 not implemented
        ADC_SIG_NA,         //20 not implemented
        ADC_SIG_NA,         //21 not implemented
        ADC_SIG_NA,         //22 not implemented
        ADC_SIG_NC          //DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23
    };
    /* Conversion table for ADC1x inputs, where x is 4 to 7, mux is defaultly "A" */
    const static uint_8 adc1_conv_table_a[] = {
        ADC_SIG_PORTE | 0, //ADC1_SE4a
        ADC_SIG_PORTE | 1, //ADC1_SE5a
        ADC_SIG_PORTE | 2, //ADC1_SE6a
        ADC_SIG_PORTE | 3  //ADC1_SE7a
    };
    /* Conversion table for ADC2x inputs, where x is 0 to 23, mux is defaultly "B" OR "X"*/
    const static uint_8 adc2_conv_table_bx[] = {
        ADC_SIG_NC,         //0 leave as default
        ADC_SIG_NC,         //1 leave as default
        ADC_SIG_NC,         //2 leave as default
        ADC_SIG_NC,         //3 leave as default
        ADC_SIG_PORTF | 4,  //ADC2_SE4b
        ADC_SIG_PORTF | 5,  //ADC2_SE5b
        ADC_SIG_PORTF | 6,  //ADC2_SE6b
        ADC_SIG_PORTF | 7,  //ADC2_SE7b
        ADC_SIG_PORTB | 0,  //ADC0_SE8/ADC1_SE8/ADC2_SE8/ADC3_SE8/TSI0_CH0
        ADC_SIG_PORTB | 1,  //ADC0_SE9/ADC1_SE9/ADC2_SE9/ADC3_SE9/TSI0_CH6
        ADC_SIG_PORTF | 1,  //ADC2_SE10
        ADC_SIG_PORTF | 0,  //ADC2_SE11
        ADC_SIG_PORTA | 29, //ADC2_SE12
        ADC_SIG_PORTA | 28, //ADC2_SE13
        ADC_SIG_PORTA | 27, //ADC2_SE14
        ADC_SIG_PORTA | 26, //ADC2_SE15
        ADC_SIG_PORTE | 8,  //ADC2_SE16
        ADC_SIG_PORTE | 9,  //ADC2_SE17
        ADC_SIG_NA,         //18 not implemented
        ADC_SIG_NA,         //19 not implemented
        ADC_SIG_NA,         //20 not implemented
        ADC_SIG_NA,         //21 not implemented
        ADC_SIG_NA,         //22 not implemented
        ADC_SIG_NA          //23 not implemented
    };
    /* Conversion table for ADC2x inputs, where x is 4 to 7, mux is defaultly "A" */
    const static uint_8 adc2_conv_table_a[] = {
        ADC_SIG_NA,         //4 not implemented
        ADC_SIG_PORTB | 21, //ADC2_SE5a
        ADC_SIG_PORTF | 2,  //ADC2_SE6a
        ADC_SIG_PORTF | 3   //ADC2_SE7a
    };
    /* Conversion table for ADC3x inputs, where x is 0 to 23, mux is defaultly "B" OR "X"*/
    const static uint_8 adc3_conv_table_bx[] = {
        ADC_SIG_NC,         //0 leave as default
        ADC_SIG_NC,         //0 leave as default
        ADC_SIG_NC,         //0 leave as default
        ADC_SIG_NC,         //0 leave as default
        ADC_SIG_PORTE | 27, //ADC3_SE4b
        ADC_SIG_PORTE | 26, //ADC3_SE5b
        ADC_SIG_PORTF | 21, //ADC3_SE6b
        ADC_SIG_PORTF | 22, //ADC3_SE7b
        ADC_SIG_PORTB | 0,  //ADC0_SE8/ADC1_SE8/ADC2_SE8/ADC3_SE8/TSI0_CH0
        ADC_SIG_PORTB | 1,  //ADC0_SE9/ADC1_SE9/ADC2_SE9/ADC3_SE9/TSI0_CH6
        ADC_SIG_PORTF | 23, //ADC3_SE10
        ADC_SIG_PORTF | 24, //ADC3_SE11
        ADC_SIG_PORTF | 25, //ADC3_SE12
        ADC_SIG_PORTF | 26, //ADC3_SE13
        ADC_SIG_PORTF | 27, //ADC3_SE14
        ADC_SIG_PORTA | 11, //ADC3_SE15
        ADC_SIG_PORTE | 11, //ADC3_SE16
        ADC_SIG_PORTE | 12, //ADC3_SE17
        ADC_SIG_NA,         //18 not implemented
        ADC_SIG_NA,         //19 not implemented
        ADC_SIG_NA,         //20 not implemented
        ADC_SIG_NA,         //21 not implemented
        ADC_SIG_NA,         //22 not implemented
        ADC_SIG_NA          //23 not implemented
    };
        /* Conversion table for ADC0x inputs, where x is 4 to 7, mux is defaultly "A" */
    const static uint_8 adc3_conv_table_a[] = {
        ADC_SIG_PORTA | 10, //ADC3_SE4a
        ADC_SIG_PORTA | 9,  //ADC3_SE5a
        ADC_SIG_PORTA | 6,  //ADC3_SE6a
        ADC_SIG_PORTE | 28  //ADC3_SE7a
    };

    if (ADC_GET_DIFF(source) && (ch > 3))
    {
        return IO_ERROR; /* signal not available */
    }

    switch(ADC_GET_MODULE(source))
    {
        case ADC_SOURCE_MODULE(1): /* ADC0 */
            if (ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_A)
            {
                if(ch < 4)
                {
                    gpio_port = adc0_conv_table_a[ch - 4];
                }
                else
                {
                    return IO_ERROR; /* channel does not exist */
                }
            }
            else /*ADC_SOURCE_MUXSEL_B OR ADC_SOURCE_MUXSEL_X*/
            {
                if(ch < 23)
                {
                    gpio_port = adc0_conv_table_bx[ch];
                }
                else
                {
                    return IO_ERROR; /* channel does not exist */
                }
            }
            break;
        case ADC_SOURCE_MODULE(2): /* ADC1 */
            if (ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_A)
            {
                if(ch < 4)
                {
                    gpio_port = adc1_conv_table_a[ch - 4];
                }
                else
                {
                    return IO_ERROR; /* channel does not exist */
                }
            }
            else /*ADC_SOURCE_MUXSEL_B OR ADC_SOURCE_MUXSEL_X*/
            {
                if(ch < 23)
                {
                    gpio_port = adc1_conv_table_bx[ch];
                }
                else
                {
                    return IO_ERROR; /* channel does not exist */
                }
            }
            break;
        case ADC_SOURCE_MODULE(3): /* ADC2 */
            if (ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_A)
            {
                if(ch < 4)
                {
                    gpio_port = adc2_conv_table_a[ch - 4];
                }
                else
                {
                    return IO_ERROR; /* channel does not exist */
                }
            }
            else /*ADC_SOURCE_MUXSEL_B OR ADC_SOURCE_MUXSEL_X*/
            {
                if(ch < 23)
                {
                    gpio_port = adc2_conv_table_bx[ch];
                }
                else
                {
                    return IO_ERROR; /* channel does not exist */
                }
            }
            break;
        case ADC_SOURCE_MODULE(4): /* ADC3 */
            if (ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_A)
            {
                if(ch < 4)
                {
                    gpio_port = adc3_conv_table_a[ch - 4];
                }
                else
                {
                    return IO_ERROR; /* channel does not exist */
                }
            }
            else /*ADC_SOURCE_MUXSEL_B OR ADC_SOURCE_MUXSEL_X*/
            {
                if(ch < 23)
                {
                    gpio_port = adc3_conv_table_bx[ch];
                }
                else
                {
                    return IO_ERROR; /* channel does not exist */
                }
            }
            break;
        default :
            return IO_ERROR; /*ADC0 - ADC3 only*/
    }

    if (gpio_port == ADC_SIG_NA)
    {
        return IO_ERROR; /* signal not available */
    }

    if (gpio_port == ADC_SIG_NC)
    {
        return IO_OK; /* no need to configure signal */
    }

    switch (gpio_port >> ADC_SIG_PORT_SHIFT)
    {
        case 1: /* PORTA */
            pctl = (PORT_MemMapPtr) PORTA_BASE_PTR;
            break;
        case 2: /* PORTB */
            pctl = (PORT_MemMapPtr) PORTB_BASE_PTR;
            break;
        case 3: /* PORTC */
            pctl = (PORT_MemMapPtr) PORTC_BASE_PTR;
            break;
        case 4: /* PORTD */
            pctl = (PORT_MemMapPtr) PORTD_BASE_PTR;
            break;
        case 5: /* PORTE */
            pctl = (PORT_MemMapPtr) PORTE_BASE_PTR;
            break;
        case 6: /* PORTF */
            pctl = (PORT_MemMapPtr) PORTF_BASE_PTR;
            break;
        /* There is no possibility to get other port from table */
    }
    pctl->PCR[gpio_port & 0x1F] &= ~PORT_PCR_MUX_MASK; /* set pin's multiplexer to analog */

    return IO_OK;
}
Ejemplo n.º 3
0
_mqx_int _bsp_adc_channel_io_init
(
     /* [IN] number of channel on which to perform hardware initialization */
    uint16_t   source
)
{
    uint8_t ch = ADC_GET_CHANNEL(source);
    uint8_t gpio_port;
    PORT_MemMapPtr pctl = NULL;
    
    #define ADC_SIG_PORT_SHIFT (5)
    #define ADC_SIG_PORTA   (0x01 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_PORTB   (0x02 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_PORTC   (0x03 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_PORTD   (0x04 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_PORTE   (0x05 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_PORTF   (0x06 << ADC_SIG_PORT_SHIFT)
    #define ADC_SIG_NA      (0x00) /* signal not available */
    #define ADC_SIG_NC      (0x01) /* signal not configurable */



/* Conversion table for ADC0x inputs, where x is 0 to 23, mux is defaultly "B" OR "X" */
    const static uint8_t adc0_conv_table_bx[] = {
        ADC_SIG_NC,         /* 0 leave as default */ 
        ADC_SIG_NC,         /* 1 leave as default */
        ADC_SIG_NC,         /* 2 leave as default */
        ADC_SIG_NC,         /* 3 leave as default */
        ADC_SIG_PORTC | 2,  /* ADC0_SE4b */
        ADC_SIG_PORTD | 1,  /* ADC0_SE5b */
        ADC_SIG_PORTD | 5,  /* ADC0_SE6b */
        ADC_SIG_PORTD | 6,  /* ADC0_SE7b */
        ADC_SIG_PORTB | 0,  /* ADC0_SE8 */
        ADC_SIG_PORTB | 1,  /* ADC0_SE9 */
        ADC_SIG_PORTA | 7,  /* ADC0_SE10 */
        ADC_SIG_PORTA | 8,  /* ADC0_SE11 */
        ADC_SIG_PORTB | 2,  /* ADC0_SE12 */
        ADC_SIG_PORTB | 3,  /* ADC0_SE13 */
        ADC_SIG_PORTC | 0,  /* ADC0_SE14 */
        ADC_SIG_PORTC | 1,  /* ADC0_SE15 */
        ADC_SIG_NC,         /* ADC0_SE16 */
        ADC_SIG_PORTE | 24, /* ADC0_SE17 */
        ADC_SIG_PORTE | 25, /* ADC0_SE18 */
        ADC_SIG_NC,         /* 19 leave as default */
        ADC_SIG_NC,         /* 20 leave as default */
        ADC_SIG_NC,         /* ADC0_SE21 */
        ADC_SIG_NC,         /* ADC0_SE22 */
        ADC_SIG_NC,         /* DAC0_OUT/CMP1_IN3/ADC0_SE23 */
        ADC_SIG_NA,         /* 24 not implemented */
        ADC_SIG_NA,         /* 25 not implemented */       
    };
    
    /* Conversion table for ADC1x inputs, where x is 0 to 23, mux is defaultly "B" OR "X"*/
    const static uint8_t adc1_conv_table_bx[] = {
        ADC_SIG_NC,         /* 0 leave as default */
        ADC_SIG_NC,         /* 1 leave as default */
        ADC_SIG_NC,         /* 2 leave as default */
        ADC_SIG_NC,         /* 3 leave as default */
        ADC_SIG_PORTC | 8,  /* ADC1_SE4b */
        ADC_SIG_PORTC | 9,  /* ADC1_SE5b */
        ADC_SIG_PORTC | 10, /* ADC1_SE6b */
        ADC_SIG_PORTC | 11, /* ADC1_SE7b */
        ADC_SIG_PORTB | 0,  /* ADC1_SE8 */
        ADC_SIG_PORTB | 1,  /* ADC1_SE9 */
        ADC_SIG_PORTB | 4,  /* ADC1_SE10 */
        ADC_SIG_PORTB | 5,  /* ADC1_SE11 */
        ADC_SIG_PORTB | 6,  /* ADC1_SE12 */
        ADC_SIG_PORTB | 7,  /* ADC1_SE13 */
        ADC_SIG_PORTB | 10, /* ADC1_SE14 */
        ADC_SIG_PORTB | 11, /* ADC1_SE15 */
        ADC_SIG_NC,         /* ADC1_SE16 */
        ADC_SIG_PORTA | 17, /* ADC1_SE17 */
        ADC_SIG_NC,         /* VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18 */
        ADC_SIG_NC,         /* 19 leave as default */
        ADC_SIG_NC,         /* 20 leave as default */
        ADC_SIG_NA,         /* 21 not implemented */
        ADC_SIG_NA,         /* 22 not implemented */
        ADC_SIG_NC,         /* DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23 */
        ADC_SIG_NA,         /* 24 not implemented */
        ADC_SIG_NA,         /* 25 not implemented */  
    };
    /* Conversion table for ADC1x inputs, where x is 4 to 7, mux is defaultly "A" */
    const static uint8_t adc1_conv_table_a[] = {
        ADC_SIG_PORTE | 0, /* ADC1_SE4a */
        ADC_SIG_PORTE | 1, /* ADC1_SE5a */
        ADC_SIG_PORTE | 2, /* ADC1_SE6a */
        ADC_SIG_PORTE | 3  /* ADC1_SE7a */
    };


    if (ADC_GET_DIFF(source) && (ch > 3))
    {
        return IO_ERROR; /* signal not available */
    }

    switch(ADC_GET_MODULE(source))
    {
        case ADC_SOURCE_MODULE(1): /* ADC0 */
            if(ch < 26)
            {
                gpio_port = adc0_conv_table_bx[ch];
            }
            else
            {
                gpio_port = ADC_SIG_NC;
            }
            break;
        case ADC_SOURCE_MODULE(2): /* ADC1 */
            if (ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_A)
            {
                if(ch < 4 || ch > 7)
                {
                    gpio_port = ADC_SIG_NA; /* channel does not exist */
                }
                else
                {
                    gpio_port = adc1_conv_table_a[ch - 4];
                }
            }
            else /*ADC_SOURCE_MUXSEL_B OR ADC_SOURCE_MUXSEL_X*/
            {
                if(ch < 26)
                {
                    gpio_port = adc1_conv_table_bx[ch];
                }
                else
                {
                    gpio_port = ADC_SIG_NC;
                }
            }
            break;
        default :
            return IO_ERROR; /*ADC0 - ADC1 only*/
    }

    if (gpio_port == ADC_SIG_NA)
    {
        return IO_ERROR; /* signal not available */
    }
    
    if (gpio_port == ADC_SIG_NC)
    {
        return IO_OK; /* no need to configure signal */
    }
    
    switch (gpio_port >> ADC_SIG_PORT_SHIFT)
    {
        case 1: /* PORTA */
            pctl = (PORT_MemMapPtr) PORTA_BASE_PTR;
            break;
        case 2: /* PORTB */
            pctl = (PORT_MemMapPtr) PORTB_BASE_PTR;
            break;
        case 3: /* PORTC */
            pctl = (PORT_MemMapPtr) PORTC_BASE_PTR;
            break;
        case 4: /* PORTD */
            pctl = (PORT_MemMapPtr) PORTD_BASE_PTR;
            break;
        case 5: /* PORTE */
            pctl = (PORT_MemMapPtr) PORTE_BASE_PTR;
            break;   
        /* There is no possibility to get other port from table */
    }
    pctl->PCR[gpio_port & 0x1F] &= ~PORT_PCR_MUX_MASK; /* set pin's multiplexer to analog */

    return IO_OK;
}
Ejemplo n.º 4
0
_mqx_int _bsp_adc_channel_io_init
(
    /* [IN] number of channel on which to perform hardware initialization */
    uint16_t   source
)
{
    uint8_t gpio_port;
    PORT_MemMapPtr pctl = NULL;
    uint8_t ch = ADC_GET_CHANNEL(source);

#define ADC_SIG_PORTA   (0x01 << 5)
#define ADC_SIG_PORTB   (0x02 << 5)
#define ADC_SIG_PORTC   (0x03 << 5)
#define ADC_SIG_PORTD   (0x04 << 5)
#define ADC_SIG_PORTE   (0x05 << 5)
#define ADC_SIG_NA      (0x00) /* signal not available */
#define ADC_SIG_NC      (0x01) /* signal not configurable */

    /* Conversion table for ADC0x inputs, where x is 0 to 23, mux is defaultly "B" */
    const static uint8_t adc0_conv_table[] = {
        ADC_SIG_NC, //0 leave as default
        ADC_SIG_NC, //1 leave as default
        ADC_SIG_PORTE | 2, //ADC0_DP2
        ADC_SIG_NC, //3 leave as default
        ADC_SIG_PORTC | 2, //4b
        ADC_SIG_PORTD | 1, //5b
        ADC_SIG_PORTD | 5, //6b
        ADC_SIG_PORTD | 6, //7b
        ADC_SIG_PORTB | 0, //8
        ADC_SIG_PORTB | 1, //9
        ADC_SIG_NA,        //10 not implemented
        ADC_SIG_NA,        //11 not implemented
        ADC_SIG_PORTB | 2, //12
        ADC_SIG_PORTB | 3, //13
        ADC_SIG_PORTC | 0, //14
        ADC_SIG_PORTC | 1, //15
        ADC_SIG_NC,        //16
        ADC_SIG_PORTE | 24, //17
        ADC_SIG_PORTE | 25, //18
        ADC_SIG_NC, //19 ADC0_DM0, leave as default
        ADC_SIG_NC, //20 ADC0_DM1, leave as default
        ADC_SIG_NC, //21 leave as default
        ADC_SIG_NC, //22 leave as default
        ADC_SIG_NC, //23 DAC0, leave as default
        ADC_SIG_NA, //24 not implemented
        ADC_SIG_NA, //25 not implemented
    };
    /* Conversion table for ADC0x, where x is 4 to 7, mux is "A" */
    const static uint8_t adc0_conv_tableA[] = {
        ADC_SIG_NA, //4a
        ADC_SIG_NA, //5a
        ADC_SIG_NA, //6a
        ADC_SIG_NA, //7a
    };

    /* Conversion table for ADC1x inputs, where x is 0 to 23, mux is defaultly "B" */
    const static uint8_t adc1_conv_table[] = {
        ADC_SIG_NC, //0 leave as default
        ADC_SIG_NC, //1 leave as default
        ADC_SIG_NA, //2 not implemented
        ADC_SIG_NC, //3 leave as default
        ADC_SIG_PORTC | 8,  //4b
        ADC_SIG_PORTC | 9,  //5b
        ADC_SIG_PORTC | 10, //6b
        ADC_SIG_PORTC | 11, //7b
        ADC_SIG_PORTB | 0,  //8
        ADC_SIG_PORTB | 1,  //9
        ADC_SIG_NA,         //10 Not implemented
        ADC_SIG_NA,         //11 Not implemented
        ADC_SIG_PORTB | 6,  //12
        ADC_SIG_PORTB | 7,  //13
        ADC_SIG_PORTB | 10, //14
        ADC_SIG_PORTB | 11, //15
        ADC_SIG_NA,         //16 Not implemented
        ADC_SIG_NA,         //17 Not implemented
        ADC_SIG_NA,         //18 VREF Output
        ADC_SIG_NC,         //19 ADC1_DM0, leave as default
        ADC_SIG_NC,         //20 ADC1_DM1, leave as default
        ADC_SIG_NA,         //21 Not implemented
        ADC_SIG_NA,         //22 Not implemented
        ADC_SIG_NC, //23 DAC1_SE23, leave as default
        ADC_SIG_NA, //24 not implemented
        ADC_SIG_NA, //25 not implemented
    };
    /* Conversion table for ADC1x, where x is 4 to 7, mux is "A" */
    const static uint8_t adc1_conv_tableA[] = {
        ADC_SIG_PORTE | 0, //4a
        ADC_SIG_PORTE | 1, //5a
        ADC_SIG_PORTE | 2, //6a
        ADC_SIG_PORTE | 3, //7a
    };

    if (ADC_GET_DIFF(source) && ch > 3)
        return IO_ERROR; /* signal not available */

    if (ch < 26) {
        switch(ADC_GET_MODULE(source))
        {
        case ADC_SOURCE_MODULE(1):   // ADC0
            /* Get result for module 0 */
            if ((ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_B) || (ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_X))
                /* Get result for module 1, if user wants "B" channel or any channel */
                gpio_port = adc0_conv_table[ch];
            else {
                /* Get result for module 1, if user wants "A" channel or any other */
                if (ch < 4 || ch > 7)
                    gpio_port = ADC_SIG_NA;
                else
                    gpio_port = adc0_conv_tableA[ch - 4];
            }
            break;
        case ADC_SOURCE_MODULE(2):   //ADC1
            /* Get result for module 0 */
            if ((ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_B) || (ADC_GET_MUXSEL(source) == ADC_SOURCE_MUXSEL_X))
                /* Get result for module 1, if user wants "B" channel or any channel */
                gpio_port = adc1_conv_table[ch];
            else {
                /* Get result for module 1, if user wants "A" channel or any other */
                if (ch < 4 || ch > 7)
                    gpio_port = ADC_SIG_NA;
                else
                    gpio_port = adc1_conv_tableA[ch - 4];
            }
            break;
        default:
            return IO_ERROR;
        }
    }
    else
        gpio_port = ADC_SIG_NC;

    if (gpio_port == ADC_SIG_NA)
        return IO_ERROR; /* signal not available */
    if (gpio_port == ADC_SIG_NC)
        return IO_OK; /* no need to configure signal */
    switch (gpio_port >> 5) {
    case 1: /* PORTA */
        pctl = (PORT_MemMapPtr) PORTA_BASE_PTR;
        break;
    case 2: /* PORTB */
        pctl = (PORT_MemMapPtr) PORTB_BASE_PTR;
        break;
    case 3: /* PORTC */
        pctl = (PORT_MemMapPtr) PORTC_BASE_PTR;
        break;
    case 4: /* PORTD */
        pctl = (PORT_MemMapPtr) PORTD_BASE_PTR;
        break;
    case 5: /* PORTE */
        pctl = (PORT_MemMapPtr) PORTE_BASE_PTR;
        break;
        /* There is no possibility to get other port from table */
    }
    pctl->PCR[gpio_port & 0x1F] &= ~PORT_PCR_MUX_MASK; /* set pin's multiplexer to analog */

    return IO_OK;
}