Ejemplos de ADC_REG_CHAN_CNTRL en C++ (Cpp)

Ejemplo n.º 1

Archivo: adc_core.c Proyecto: basbergstage/no-OS

/***************************************************************************//**
* @brief adc_setup
*******************************************************************************/
int32_t adc_setup(uint32_t adc_addr, uint32_t dma_addr,  uint8_t ch_no)
{
	uint8_t index;
	uint32_t status;

	adc_baseaddr = adc_addr;
	adc_dmac_baseaddr = dma_addr;

	adc_write(ADC_REG_RSTN, 0x00);
	adc_write(ADC_REG_RSTN, 0x03);

	mdelay(100);

	for(index = 0; index < ch_no; index++)
	{
		adc_write(ADC_REG_CHAN_CNTRL(index), 0x51);
	}

	adc_read(ADC_REG_STATUS, &status);
	if(status == 0x0)
	{
		xil_printf("ADC Core Status errors.\n\r");

		return -1;
	}
	else
	{
		xil_printf("ADC Core successfully initialized.\n");

		return 0;
	}
}

Ejemplo n.º 2

Archivo: adc_core.c Proyecto: Deepak1108/no-OS

/***************************************************************************//**
 * @brief adc_pn_mon
*******************************************************************************/
int32_t adc_pn_mon(adc_core core,
				   enum adc_pn_sel sel)
{
	uint8_t	index;
	uint32_t reg_data;
	int32_t pn_errors = 0;

	for (index = 0; index < core.no_of_channels; index++) {
		adc_write(core, ADC_REG_CHAN_CNTRL(index), ADC_ENABLE);
		adc_set_pnsel(core, index, sel);
	}
	mdelay(1);

	for (index = 0; index < core.no_of_channels; index++) {
		adc_write(core, ADC_REG_CHAN_STATUS(index), 0xff);
	}
	mdelay(100);

	for (index = 0; index < core.no_of_channels; index++) {
		adc_read(core, ADC_REG_CHAN_STATUS(index), &reg_data);
		if (reg_data != 0) {
			pn_errors = -1;
			xil_printf("ADC PN Status: %d, %d, 0x%02x!\n", index, sel, reg_data);
		}
	}

	return pn_errors;
}

Ejemplo n.º 3

Archivo: adc_core.c Proyecto: Deepak1108/no-OS

/***************************************************************************//**
* @brief adc_setup
*******************************************************************************/
int32_t adc_setup(adc_core core)
{
	uint8_t	 index;
	uint32_t reg_data;
	uint32_t adc_clock;

	adc_read(core, ADC_REG_ID, &reg_data);
	if (reg_data)
		core.master = 1;
	else
		core.master = 0;

	adc_write(core, ADC_REG_RSTN, 0);
	adc_write(core, ADC_REG_RSTN, ADC_MMCM_RSTN | ADC_RSTN);

	for(index = 0; index < core.no_of_channels; index++) {
		adc_write(core, ADC_REG_CHAN_CNTRL(index), 0x51);
	}

	mdelay(100);

	adc_read(core, ADC_REG_STATUS, &reg_data);
	if(reg_data == 0x0) {
		xil_printf("ADC Core Status errors.\n");
		return -1;
	}

	adc_read(core, ADC_REG_CLK_FREQ, &adc_clock);
	adc_read(core, ADC_REG_CLK_RATIO, &reg_data);
	adc_clock = (adc_clock * reg_data * 100) + 0x7fff;
	adc_clock = adc_clock >> 16;

	xil_printf("ADC Core Initialized (%d MHz).\n", adc_clock);

	return 0;
}

Ejemplo n.º 4

Archivo: adc_core.c Proyecto: basbergstage/no-OS

/***************************************************************************//**
 * @brief adc_init
*******************************************************************************/
void adc_init(struct ad9361_rf_phy *phy)
{
	adc_write(phy, ADC_REG_RSTN, 0);
	adc_write(phy, ADC_REG_RSTN, ADC_RSTN);

	adc_write(phy, ADC_REG_CHAN_CNTRL(0),
		ADC_IQCOR_ENB | ADC_FORMAT_SIGNEXT | ADC_FORMAT_ENABLE | ADC_ENABLE);
	adc_write(phy, ADC_REG_CHAN_CNTRL(1),
		ADC_IQCOR_ENB | ADC_FORMAT_SIGNEXT | ADC_FORMAT_ENABLE | ADC_ENABLE);
	adc_st.rx2tx2 = phy->pdata->rx2tx2;
	if(adc_st.rx2tx2)
	{
		adc_write(phy, ADC_REG_CHAN_CNTRL(2),
			ADC_IQCOR_ENB | ADC_FORMAT_SIGNEXT | ADC_FORMAT_ENABLE | ADC_ENABLE);
		adc_write(phy, ADC_REG_CHAN_CNTRL(3),
			ADC_IQCOR_ENB | ADC_FORMAT_SIGNEXT | ADC_FORMAT_ENABLE | ADC_ENABLE);
	}
	else
	{
		adc_write(phy, ADC_REG_CHAN_CNTRL(2), 0);
		adc_write(phy, ADC_REG_CHAN_CNTRL(3), 0);
	}
}