int AnalogEncoder::EncoderValue()
{
int analogPin = AnalogPinNumbers[pin];
ADCNumber adcNum = ADCNumbers[pin];
Encoder_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(analogPin);
Encoder_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(analogPin);
int result;
if (adcNum == ADC0)
{
ADC_Config_Alt(ADC0_BASE_PTR, &Encoder_Adc_Config); // config ADC0
// Check the status control register to see is the COnversion is COmplete
while (( ADC0_SC1A & ADC_SC1_COCO_MASK ) != ADC_SC1_COCO_MASK){}
result = ADC0_RA;
}
else
{
ADC_Config_Alt(ADC1_BASE_PTR, &Encoder_Adc_Config); // config ADC0
// Check the status control register to see is the COnversion is COmplete
while (( ADC1_SC1A & ADC_SC1_COCO_MASK ) != ADC_SC1_COCO_MASK){}
result = ADC1_RA;
}
return result;
}
/*
** ===================================================================
** Method : ADC0_Init (component Init_ADC)
** Description :
** This method initializes registers of the ADC module
** according to the Peripheral Initialization settings.
** Call this method in user code to initialize the module. By
** default, the method is called by PE automatically; see "Call
** Init method" property of the component for more details.
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
void ADC0_Init(void)
{
/* SIM_SCGC6: ADC0=1 */
SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
/* ADC0_CFG1: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,ADLPC=0,ADIV=0,ADLSMP=0,MODE=0,ADICLK=0 */
ADC0_CFG1 = ADC_CFG1_ADIV(0x00) |
ADC_CFG1_MODE(0x00) |
ADC_CFG1_ADICLK(0x00);
/* ADC0_CFG2: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,ADACKEN=0,ADHSC=0,ADLSTS=0 */
ADC0_CFG2 &= (uint32_t)~(uint32_t)(
ADC_CFG2_ADACKEN_MASK |
ADC_CFG2_ADHSC_MASK |
ADC_CFG2_ADLSTS(0x03) |
0xFFFFFFE0U
);
/* ADC0_CV1: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CV=0 */
ADC0_CV1 = ADC_CV1_CV(0x00);
/* ADC0_CV2: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CV=0 */
ADC0_CV2 = ADC_CV2_CV(0x00);
/* ADC0_OFS: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OFS=4 */
ADC0_OFS = ADC_OFS_OFS(0x04);
/* ADC0_SC2: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,ADACT=0,ADTRG=0,ACFE=0,ACFGT=0,ACREN=0,DMAEN=0,REFSEL=0 */
ADC0_SC2 = ADC_SC2_REFSEL(0x00);
/* ADC0_SC3: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CAL=0,CALF=0,??=0,??=0,ADCO=0,AVGE=0,AVGS=0 */
ADC0_SC3 = ADC_SC3_AVGS(0x00);
/* ADC0_SC1A: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COCO=0,AIEN=0,DIFF=0,ADCH=0x1F */
ADC0_SC1A = ADC_SC1_ADCH(0x1F);
/* ADC0_SC1B: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COCO=0,AIEN=0,DIFF=0,ADCH=0x1F */
ADC0_SC1B = ADC_SC1_ADCH(0x1F);
}
/** adc_init
* \brief initialize and calibrate ADC0 module
* \brief 48MHz IPBus clock; ADC clock = 48M/2/8 = 3MHz
* \brief Total conversion time: 56N+4ADCK
* \brief given sampling rate Fs = 6.4K, 156us/sample, 156*3= 468 ADCK
* \author FSL
* \param none
* \return none
* \warning assumes 48MHz IPBus clock
*/
void adc_init(void)
{
uint8_t cal_ok;
SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
#ifdef CMSIS
NVIC_EnableIRQ(ADC0_IRQn);
#else
enable_irq(INT_ADC0 - 16);
#endif
/* 48MHz IPBus clock
* ADC clock = 48M/2/8 = 3MHz
* Total conversion time: 56N+4ADCK
* Given sampling rate Fs = 6.4K, 156us/sample, 156*3= 468 ADCK
* the maximum h/w average number = 8
* use h/w average number = 4
* Total conversion time: 56*4+4 = 228 ADC clocks,76us
* There are 468-228 = 240 ADC clocks (ie. 80us) free for post processing
*/
// Initialize ADC0
// Do calibration first with 32 h/w averages
Master_Adc_Config.CONFIG1 = ADLPC_NORMAL | ADC_CFG1_ADIV(ADIV_8) | ADLSMP_LONG | ADC_CFG1_MODE(MODE_16)
| ADC_CFG1_ADICLK(ADICLK_BUS_2);
Master_Adc_Config.CONFIG2 = MUXSEL_ADCA | ADACKEN_ENABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_20) ;
Master_Adc_Config.COMPARE1 = 0x1234u ;
Master_Adc_Config.COMPARE2 = 0x5678u ;
Master_Adc_Config.STATUS2 = ADTRG_SW | ACFE_DISABLED | ACFGT_GREATER | ACREN_ENABLED | DMAEN_DISABLED | ADC_SC2_REFSEL(REFSEL_EXT);
Master_Adc_Config.STATUS3 = CAL_OFF | ADCO_SINGLE | AVGE_ENABLED | ADC_SC3_AVGS(AVGS_32);
// Master_Adc_Config.PGA = PGAEN_DISABLED | PGACHP_NOCHOP | PGALP_NORMAL | ADC_PGA_PGAG(PGAG_64);
Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC
cal_ok = ADC_Cal(ADC0_BASE_PTR); // do the calibration
if (cal_ok != 0) printf("ADC calibration error");
ADC_Read_Cal(ADC0_BASE_PTR,&CalibrationStore[1]); // store the cal
// Now do normal ADC configuration with 4 h/w averages and h/w trigger from PDB
Master_Adc_Config.CONFIG1 = ADLPC_NORMAL | ADC_CFG1_ADIV(ADIV_8) | ADLSMP_LONG | ADC_CFG1_MODE(MODE_12)
| ADC_CFG1_ADICLK(ADICLK_BUS_2);
Master_Adc_Config.CONFIG2 = MUXSEL_ADCB | ADACKEN_ENABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_20) ;
Master_Adc_Config.COMPARE1 = 0x1234u ;
Master_Adc_Config.COMPARE2 = 0x5678u ;
Master_Adc_Config.STATUS2 = !ADTRG_HW | ACFE_DISABLED | ACFGT_GREATER | ACREN_DISABLED | DMAEN_DISABLED | ADC_SC2_REFSEL(REFSEL_EXT);
Master_Adc_Config.STATUS3 = CAL_OFF | ADCO_SINGLE | AVGE_ENABLED | ADC_SC3_AVGS(AVGS_4);
// Master_Adc_Config.PGA = PGAEN_DISABLED | PGACHP_NOCHOP | PGALP_NORMAL | ADC_PGA_PGAG(PGAG_64);
Master_Adc_Config.STATUS1A = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(31);
Master_Adc_Config.STATUS1B = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(31);
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config the ADC again to default conditions
}
uint16 adc_read(uint8 channel)
{
ADC0_SC1A = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(channel) ; // start conversion
while((ADC0_SC1A & ADC_SC1_COCO_MASK)!= 0){};
return ADC0_RA;
}
uint16_t adc::convert ()
{
//Select 4 channal and start conversation
ADC0->SC1[0] = ADC_SC1_ADCH(n_channel);
while (!(ADC0->SC1[0]&ADC_SC1_COCO_MASK));
return ADC0->R[0];
}
uint16_t conv_adc(uint8_t pin)
{
//Select 4 channal and start conversation
ADC0->SC1[0] = ADC_SC1_ADCH(pin);
while (!(ADC0->SC1[0]&ADC_SC1_COCO_MASK));
return ADC0->R[0];
}
/*****************************************************************************//*!
*
* @brief set ADC channel.
*
* @param[in] pADC point to ADC module type.
* @param[in] u8Channel adc channel to conversion.
*
* @return none
*
* @ Pass/ Fail criteria: none
*****************************************************************************/
void ADC_SetChannel( ADC_Type *pADC, uint8_t u8Channel )
{
uint32_t u32temp;
u32temp = pADC->SC1;
u32temp &= ~ADC_SC1_ADCH_MASK;
pADC->SC1 = u32temp|ADC_SC1_ADCH(u8Channel);
}
/* adc_init()
* Calibrates and initializes adc to perform single conversions and generate
* DMA requests at the end of the conversion
*
* */
void adc_init(void)
{
// Enable clocks
SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK; // ADC0 clock
// Calibrate ADC
adc_cal();
// Configure ADC
ADC0_CFG1 = 0; // Reset register
ADC0_CFG1 = (ADC_CFG1_MODE(3) | // 12 bits mode see table
ADC_CFG1_ADICLK(0)| // Input Bus Clock (20-25 MHz out of reset (FEI mode))
ADC_CFG1_ADIV(1)|ADC_CFG1_ADLSMP_MASK) ; // Clock divide by 2 (10-12.5 MHz)
ADC0_SC1A |= ADC_SC1_AIEN_MASK; // Interrupt enable
ADC0_CFG2=ADC_CFG2_ADHSC_MASK |ADC_CFG2_MUXSEL_MASK; //high speed conversion
ADC0_SC3=ADC_SC3_AVGE_MASK|ADC_SC3_AVGS(3);//hardware avg- 32 sampels
//ADC0_CV1=250;
enable_irq(INT_ADC0-16);
set_irq_priority(INT_ADC0-16,2);
//ADC0_SC2 |= ADC_SC2_DMAEN_MASK; // DMA Enable
//ADC0_SC2=ADC_SC2_ADTRG_MASK; //hardware triger
//ADC0_SC3 = 0; // Reset SC3
//ADC0_SC1A = ADC_SC1_ADCH(x); //adx chnner see table
ADC0_SC1A = ADC_SC1_ADCH(7)|ADC_SC1_AIEN_MASK;
}
void Init_ADC(void) {
adc_sim();
// set PTE20 as ADC0_SE0 -- DEFAULT
PORTE->PCR[20] &= ~PORT_PCR_MUX_MASK;
PORTE->PCR[20] |= PORT_PCR_MUX(0);
// set PTE21 as ADC0_SE4a -- DEFAULT
PORTE->PCR[21] &= ~PORT_PCR_MUX_MASK;
PORTE->PCR[21] |= PORT_PCR_MUX(0);
// set PTE22 as ADC0_SE3 -- DEFAULT
PORTE->PCR[22] &= ~PORT_PCR_MUX_MASK;
PORTE->PCR[22] |= PORT_PCR_MUX(0);
ADC0->SC1[0] = 0;
ADC0->CFG1 = 0;
ADC0->SC2 = 0;
//Enable Interrupt and select ADC0SE0
ADC0->SC1[0] |= ADC_SC1_AIEN_MASK|ADC_SC1_ADCH(0);
// Low Power configuration and 16 bit unsigned single-ended conversion
ADC0->CFG1 |= ADC_CFG1_ADLPC_MASK|ADC_CFG1_MODE(3);
//// ADC0->CFG2 |= ADC_CFG2_ADHSC_MASK;
ADC0->SC2 |= ADC_SC2_ADTRG_MASK;
NVIC_EnableIRQ (ADC0_IRQn);
}
void InitADC_12Bit()
{
SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
// setup the initial ADC default configuration to get setup for calibration
Master_Adc_Config.CONFIG1 = ADLPC_NORMAL
| ADC_CFG1_ADIV(ADIV_4)
| ADLSMP_LONG
| ADC_CFG1_MODE(MODE_12)
| ADC_CFG1_ADICLK(ADICLK_BUS);
Master_Adc_Config.CONFIG2 = MUXSEL_ADCA
| ADACKEN_DISABLED
| ADHSC_HISPEED
| ADC_CFG2_ADLSTS(ADLSTS_20) ;
Master_Adc_Config.COMPARE1 = 0x1234u ; // can be anything
Master_Adc_Config.COMPARE2 = 0x5678u ; // can be anything
// since not using
// compare feature
Master_Adc_Config.STATUS2 =
ACFE_DISABLED
| ACFGT_GREATER
| ACREN_ENABLED
| DMAEN_DISABLED
| ADC_SC2_REFSEL(REFSEL_EXT);
Master_Adc_Config.STATUS3 = CAL_OFF
| ADCO_SINGLE
| AVGE_ENABLED
| ADC_SC3_AVGS(AVGS_16);
Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
// Configure ADC as it will be used, but becuase ADC_SC1_ADCH is 31,
// the ADC will be inactive. Channel 31 is just disable function.
// There really is no channel 31.
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC
// Calibrate the ADC in the configuration in which it will be used:
ADC_Cal(ADC0_BASE_PTR); // do the calibration
// The structure still has the desired configuration. So restore it.
// Why restore it? The calibration makes some adjustments to the
// configuration of the ADC. The are now undone:
// config the ADC again to desired conditions
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);
// *****************************************************************************
// ADC0 using the PDB trigger in ping pong
// *****************************************************************************
// use interrupts, single ended mode, and real channel numbers now:
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC0
}
void adcEnable() {
//if ((SIM_SCGC6 & SIM_SCGC6_ADC0) == 0x00) {
if ((BITBAND_U32(SIM_SCGC6, SIM_SCGC6_ADC0_BIT)) == 0x00) {
BITBAND_U32(SIM_SCGC6, SIM_SCGC6_ADC0_BIT) = 0x01;
//SIM_SCGC6 |= SIM_SCGC6_ADC0;// enable ADC clock
ADC0_SC1A |= ADC_SC1_ADCH(0x05);// enable ADC
}
}
void adcDisable() {
//if (SIM_SCGC6 & SIM_SCGC6_ADC0) {
if ((BITBAND_U32(SIM_SCGC6, SIM_SCGC6_ADC0_BIT)) == 0x01) {
ADC0_SC1A |= ADC_SC1_ADCH(0x1F);// disable ADC
BITBAND_U32(SIM_SCGC6, SIM_SCGC6_ADC0_BIT) = 0x00;
//SIM_SCGC6 &= ~SIM_SCGC6_ADC0;// disable ADC clock
}
}
void adc_deinit (void) {
/*
* this disables the ADC peripheral
*/
/* ADC0_SC1A: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COCO=0,AIEN=0,DIFF=0,ADCH=0x1F */
ADC0_SC1A = ADC_SC1_ADCH(0x1F);
/* SIM_SCGC6: ADC0=0 */
SIM_SCGC6 &= ~SIM_SCGC6_ADC0_MASK;
}
uint16_t Module_ADC_Read(_ADC_Pin pin) {
ADC_SC1 |= ADC_SC1_ADCH(pin.channel); // select channel to read
while (!(ADC_SC1 & ADC_SC1_COCO_MASK))
; // wait until conversion has completed
pin.result = ADC_R;
return ADC_R ;
}
// Measure the voltage of Vref (V3_3)
float Measure_VRail(void) {
float vrail;
unsigned res=0;
ADC0->SC1[0] = ADC_SC1_ADCH(27); // start conversion on channel 27 (Bandgap reference)
while (!(ADC0->SC1[0] & ADC_SC1_COCO_MASK));
res = ADC0->R[0];
vrail = (VBG_VALUE/res)*65536; // calculate hte value of Vref
return vrail;
}
int adc_init(adc_t line)
{
/* make sure the given line is valid */
if (line >= ADC_NUMOF) {
return -1;
}
/* prepare the device: lock and power on */
prep(line);
/* configure the connected pin mux */
if (adc_config[line].pin != GPIO_UNDEF) {
gpio_init_port(adc_config[line].pin, GPIO_AF_ANALOG);
}
/* The ADC requires at least 2 MHz module clock for full accuracy, and less
* than 12 MHz */
/* For the calibration it is important that the ADC clock is <= 4 MHz */
uint32_t adiv;
if (CLOCK_BUSCLOCK > (ADC_MAX_CLK << 3)) {
#if KINETIS_HAVE_ADICLK_BUS_DIV_2
/* Some CPUs, e.g. MK60D10, MKW22D5, provide an additional divide by two
* divider for the bus clock as CFG1[ADICLK] = 0b01
*/
adiv = ADC_CFG1_ADIV(3) | ADC_CFG1_ADICLK(1);
#else
/* Newer CPUs seem to have replaced this with various alternate clock
* sources instead */
adiv = ADC_CFG1_ADIV(3);
#endif
}
else {
unsigned int i = 0;
while ((i < 3) && (CLOCK_BUSCLOCK > (ADC_MAX_CLK << i))) {
++i;
}
adiv = ADC_CFG1_ADIV(i);
}
/* set configuration register 1: clocking and precision */
/* Set long sample time */
dev(line)->CFG1 = ADC_CFG1_ADLSMP_MASK | adiv;
/* select ADxxb channels, longest sample time (20 extra ADC cycles) */
dev(line)->CFG2 = ADC_CFG2_MUXSEL_MASK | ADC_CFG2_ADLSTS(0);
/* select software trigger, external ref pins */
dev(line)->SC2 = ADC_SC2_REFSEL(0);
/* select hardware average over 32 samples */
dev(line)->SC3 = ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(3);
/* set an (arbitrary) input channel, single-ended mode */
dev(line)->SC1[0] = ADC_SC1_ADCH(0);
/* perform calibration routine */
int res = kinetis_adc_calibrate(dev(line));
done(line);
return res;
}
void IrScanEnd(){
int i;
TPM1_C1V = ZeroDegree;//start at degree 0 -look forward
delay(250);
TPM0_C4V = FullDegree;//start at degree 180 -look forward
delay(50);
int counter=0;
while (TPM0_C4V>=FullDegree-3.96*80){//80 degree scan
ADC0_SC1A=ADC_SC1_ADCH(7);
TPM0_C4V-=9;
delay(25);
IrSampels[43-counter]=DistanceMeasuring1(ADC0_RA);
ADC0_SC1A=ADC_SC1_ADCH(6);
TPM1_C1V+=9;
delay(25);
IrSampels[counter+44]=DistanceMeasuring2(ADC0_RA);
counter++;
}
delay(25);
TPM1_C1V = ZeroDegree;//start at degree 0 -look forward
delay(25);
TPM0_C4V = FullDegree;//start at degree 180 -look forward
delay(50);
}
//------------------------------------------------------------
// Sélection du canal à convertir
// aCh: quel canal
//------------------------------------------------------------
void iAd_SelectChannel(ADCChannelEnum aCh)
{
UInt16 aVal;
// Clear ADCH field
ADC1_SC1A&=(~ADC_SC1_ADCH_MASK);
// Configuration du canal
ADC1_SC1A|=(ADC_SC1_ADCH(aCh));
}
//Analog read function causes digital output to behave strangely????????
float AnalogInputPin::Value()
{
int analogPin = AnalogPinNumbers[pin];
ADCNumber adcNum = ADCNumbers[pin];
Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(analogPin);
Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(analogPin);
unsigned int result;
// Disable Encoder Interrupts Temporarily
NVICICER2 = (1 << (4));
if (adcNum == ADC0)
{
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC0
// Check the status control register to see is the COnversion is COmplete
while (( ADC0_SC1A & ADC_SC1_COCO_MASK ) != ADC_SC1_COCO_MASK){}
result = ADC0_RA;
}
else
{
ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // config ADC0
// Check the status control register to see is the COnversion is COmplete
while (( ADC1_SC1A & ADC_SC1_COCO_MASK ) != ADC_SC1_COCO_MASK){}
result = ADC1_RA;
}
// Re-enable Encoder Interrupt
NVICICPR2 |= (1 << (4));
NVICISER2 |= (1 << (4));
// // Re-enable button Interrupt
// NVICICPR2 |= (1 << ( 26 ));
// NVICISER2 |= (1 << ( 26 ));
float v = (result & 0xFFFFu) *3.33 / (0xFFFFu);
return v;
}
void sadc_StartSingleConversion(int channel)
{
if (FIFOMode)
{
error("sadc: attempt to do a single conversion while in FIFO mode.");
}
else
{
ADC->SC1 = (ADC->SC1 & ~ADC_SC1_ADCH_MASK) | ADC_SC1_ADCH(channel); // // Read SC1, clearing the channel selection bits, and select a new channel
}
}
void init_ADC16(void){
// Turn on the ADC0 clock as well as the PDB clocks to test ADC triggered by PDB
SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK );
// SIM_SCGC6 |= SIM_SCGC6_PDB_MASK ; pdb
PMC_REGSC |= PMC_REGSC_BGBE_MASK ;
// setup the initial ADC default configuration
Master_Adc_Config.CONFIG1 = ADLPC_LOW
| ADC_CFG1_ADIV(ADIV_1)
| ADLSMP_LONG
| ADC_CFG1_MODE(MODE_16)
| ADC_CFG1_ADICLK(ADICLK_BUS);
Master_Adc_Config.CONFIG2 = MUXSEL_ADCA
| ADACKEN_DISABLED
| ADHSC_HISPEED
| ADC_CFG2_ADLSTS(ADLSTS_20) ;
Master_Adc_Config.COMPARE1 = 0x1234u ; // can be anything
Master_Adc_Config.COMPARE2 = 0x5678u ; // can be anything
// since not using
// compare feature
Master_Adc_Config.STATUS2 = ADTRG_SW
| ACFE_DISABLED
| ACFGT_GREATER
| ACREN_DISABLED
| DMAEN_DISABLED
| ADC_SC2_REFSEL(REFSEL_EXT);
Master_Adc_Config.STATUS3 = CAL_OFF
| ADCO_SINGLE
| !AVGE_ENABLED
| ADC_SC3_AVGS(AVGS_4);
Master_Adc_Config.STATUS1A = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(31);
// Configure ADC as it will be used, but becuase ADC_SC1_ADCH is 31,
// the ADC will be inactive. Channel 31 is just disable function.
// There really is no channel 31.
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC
// Calibrate the ADC in the configuration in which it will be used:
ADC_Cal(ADC0_BASE_PTR); // do the calibration
// The structure still has the desired configuration. So restore it.
// Why restore it? The calibration makes some adjustments to the
// configuration of the ADC. The are now undone:
// config the ADC again to desired conditions
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);
}
//------------------------------------------------------------
// Configuration du convertisseur AD
//------------------------------------------------------------
void iAd_Config(void)
{
// Lets calibrate the ADC. 1st setup how the channel will be used.
disable_irq(INT_ADC1-16);
// ADC configuration register 1 (ADCx_CFG1)
// K10 Sub-Family Reference Manual, Rev. 6, Nov 2011 page 757
// ADLPC=0, Normal power configuration
// ADIV=0,The divide ratio is 1 and the clock rate is (input clock)/1
// ADLSMP=0,short sample time
// MODE=11,It is single-ended 16-bit conversion
// ADICLK=0,Bus clock divided by 1 --> 50MHz
ADC1_CFG1=0;
ADC1_CFG1|=(ADC_CFG1_ADIV(0)|ADC_CFG1_MODE(3)|ADC_CFG1_ADICLK(0));
// Configuration register 2 (ADCx_CFG2)
// K10 Sub-Family Reference Manual, Rev. 6, Nov 2011 page 759
// MUXSEL=0,ADxxa channels are selected
// ADACKEN=0,Asynchronous clock output disabled
// ADHSC=1,high speed conversion sequence selected
// ADLSTS=3,2 extra ADCK cycles; 6 ADCK cycles total sample time
ADC1_CFG2=0|ADC_CFG2_ADHSC_MASK|ADC_CFG2_ADLSTS(3);
// --> une conversion 5us --> 128 pixels: 640us
// Status and control register 2 (ADCx_SC2)
// K10 Sub-Family Reference Manual, Rev. 6, Nov 2011 page 762
// ADTRG=0,Software trigger selected
// ACFE=0,Compare function disabled
// ACFGT=0,Configures less than threshold, outside range not inclusive and inside range not inclusive functionality
// based on the values placed in the CV1 and CV2 registers
// ACREN=0,Range function disabled. Only the compare value 1 register (CV1) is compared
// DMAEN=0,DMA is disabled
// REFSEL=0,Default voltage reference pin pair (external pins VREFH and VREFL)
ADC1_SC2=0;
// Status and control register 2 (ADCx_SC3)
// K10 Sub-Family Reference Manual, Rev. 6, Nov 2011 page 764
// ADCO=0, One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
// AVGE=0, Hardware average function disabled
// AVGS=0, 4 samples averaged
ADC1_SC3=0|ADC_SC3_AVGE_MASK|ADC_SC3_AVGS(0);
// ADC status and control registers 1 (ADCx_SC1n)
// K10 Sub-Family Reference Manual, Rev. 6, Nov 2011 page 754
// AIEN=0,Conversion complete interrupt disabled
// DIFF=0,Differential mode enable -> Single-ended conversions and input channels are selected
// ADCH=0x03,Input channel select -> POT1
ADC1_SC1A=0;
ADC1_SC1A=0|(ADC_SC1_ADCH(3));
}
void sadc_StartFIFOConversion(int channels[])
{
if (!FIFOMode)
{
error("sadc: attempt to do a FIFO conversion while in single mode.");
}
else
{
for (int i = 0; i < FIFODepth; ++i)
{
ADC->SC1 = (ADC->SC1 & ~ADC_SC1_ADCH_MASK) | ADC_SC1_ADCH(channels[i]); // Clear the channel selection bits and select each channel, in order
}
}
}
void
main(void)
{
adc_init();
dma_init();
enter_thread_mode();
sema_wait(&adc_start_sema);
struct dma_ctx *ctx;
ctx = dma_setup(DMAMUX_ADC0, &ADC_R_REG(ADC0, 0), dstbuf, 2, sizeof(dstbuf)/2, DMA_SRC_STICKY | DMA_DOUBLEBUF | DMA_LOOP, dma_done, NULL);
adc_sample_prepare(ADC_MODE_CONTINUOUS);
bf_set_reg(ADC_SC2_REG(ADC0), ADC_SC2_DMAEN, 1);
ADC_SC1_REG(ADC0, 0) = ADC_SC1_ADCH(0) | ADC_SC1_DIFF_MASK;
wait(main);
}
/*************************************************************************
* 野火嵌入式開發工作室
*
* 函數名稱：adc_start
* 功能說明：啟動adc軟件采樣，B通道不能用於軟件觸發！！！！
* 參數說明：ADCx 模塊號（ ADC0、 ADC1）
* ADC_Channel 通道號
* ADC_nbit 精度（ ADC_8bit,ADC_12bit, ADC_10bit, ADC_16bit ）
* 函數返回：無
* 修改時間：2012-2-10
* 備 注：修改蘇州大學的例程
*************************************************************************/
void adc_start(ADCn adcn,ADC_Ch ch,ADC_nbit bit)
{
Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH( ch );
//初始化ADC默認配置
Master_Adc_Config.CONFIG1 = ADLPC_NORMAL
| ADC_CFG1_ADIV(ADIV_4)
| ADLSMP_LONG
| ADC_CFG1_MODE(bit)
| ADC_CFG1_ADICLK(ADICLK_BUS);
Master_Adc_Config.CONFIG2 = MUXSEL_ADCB //MUXSEL_ADCB
| ADACKEN_DISABLED
| ADHSC_HISPEED
| ADC_CFG2_ADLSTS(ADLSTS_20) ;
Master_Adc_Config.COMPARE1 = 0x1234u ; //任意值
Master_Adc_Config.COMPARE2 = 0x5678u ; //任意值
adc_config_alt(ADCx[adcn], &Master_Adc_Config); // 配置 ADCn
}
inline void adc_start() {
// to start the ADC conversion
ADC_SC1_REG(ADC0_BASE_PTR, A)= AIEN_ON
| DIFF_SINGLE
| ADC_SC1_ADCH(18);
}
int adc_init() {
adc_pixelIndex = 0;
// disable ADC irq - not ready yet
disable_irq(ADC_IRQ_NUM);
// turn on clock to ADC0
SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK);
// to setup SW trigger on FTM2
SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(10);
// to calibrate the ADC module
unsigned short cal_var;
cal_var = 0x0000;
// add the plus-side calibration results
cal_var += ADC_CLP0_REG(ADC0_BASE_PTR);
cal_var += ADC_CLP1_REG(ADC0_BASE_PTR);
cal_var += ADC_CLP2_REG(ADC0_BASE_PTR);
cal_var += ADC_CLP3_REG(ADC0_BASE_PTR);
cal_var += ADC_CLP4_REG(ADC0_BASE_PTR);
cal_var += ADC_CLPS_REG(ADC0_BASE_PTR);
cal_var /= 2;
cal_var |= 0x8000;
// store value in plus-side gain calibration register (PG)
ADC_PG_REG(ADC0_BASE_PTR) = ADC_PG_PG(cal_var);
cal_var = 0x0000;
// add the minus-side calibration results
cal_var += ADC_CLM0_REG(ADC0_BASE_PTR);
cal_var += ADC_CLM1_REG(ADC0_BASE_PTR);
cal_var += ADC_CLM2_REG(ADC0_BASE_PTR);
cal_var += ADC_CLM3_REG(ADC0_BASE_PTR);
cal_var += ADC_CLM4_REG(ADC0_BASE_PTR);
cal_var += ADC_CLMS_REG(ADC0_BASE_PTR);
cal_var /= 2;
cal_var |= 0x8000;
// store value in minus-side gain calibration register (MG)
ADC_MG_REG(ADC0_BASE_PTR) = ADC_MG_MG(cal_var);
ADC_SC3_REG(ADC0_BASE_PTR) &= ~ADC_SC3_CAL_MASK;
// to set the configuration register 1 (CFG1) to select the mode of
// operation, clock source, clock divide, and configuration for low
// power or long sample time
ADC_CFG1_REG(ADC0_BASE_PTR) = ADLPC_NORMAL
| ADC_CFG1_ADIV(ADIV_1)
| ADLSMP_SHORT
| ADC_CFG1_MODE(MODE_8)
| ADC_CFG1_ADICLK(ADICLK_BUS);
// to set the configuration register 2 (CFG2) to select the special
// high-speed configuration for very high speed conversions and
// select the long sample time duration during long sample mode
ADC_CFG2_REG(ADC0_BASE_PTR) = MUXSEL_ADCA
| ADACKEN_DISABLED
| ADHSC_HISPEED
| ADC_CFG2_ADLSTS(ADLSTS_2);
// to configure the status and control register 2 (SC2)
ADC_SC2_REG(ADC0_BASE_PTR) = ADTRG_SW
| ACFE_DISABLED
| ACFGT_GREATER
| ACREN_DISABLED
| DMAEN_DISABLED
| ADC_SC2_REFSEL(REFSEL_EXT);
// to configure the status and control register 3 (SC3)
// enable hw averaging, 16 samples taken
ADC_SC3_REG(ADC0_BASE_PTR) = CAL_OFF
| ADCO_SINGLE
| AVGE_ENABLED
| ADC_SC3_AVGS(AVGS_16);
// to configure the status and control register 1 (SC1)
// enable the interrupt, single-ended conversion, on AD18
ADC_SC1_REG(ADC0_BASE_PTR, A)= AIEN_ON
| DIFF_SINGLE
| ADC_SC1_ADCH(18);
// to configure the PGA register
ADC_PGA_REG(ADC0_BASE_PTR) = PGAEN_DISABLED
| PGACHP_NOCHOP
| PGALP_NORMAL
| ADC_PGA_PGAG(PGAG_64);
// enable ADC irq
enable_irq(ADC_IRQ_NUM);
return ADC_RET_SUCCESS;
}
uint8_t Hw_Trig_Test(void)
{
// Notes:
// PDB settings : continous mode, started by sotware trigger.
// This means that once the software "pulls the trigger" by setting a certain bit, the PDB starts counting
// and handing out four triggers per cycle of its counter.
// PDB settings: CH0_DLY0, CH0_DLY1 , CH1_DLY0, CH1_DLY1
// set to different values to distinguish effect on ADCx_Ry register
// need to provide 4 different voltages to convert at two ADC0 and two ADC1 input channels
// PDB counter clock prescaled to allow time for printf's and slow down things to they are visible, each trigger.
// Using adiclk= BUS , and adidiv/4 to get 12,5MHz on Tower demonstration.
// visibility of PDB start trigger is obtained by generating a toggling edge on
// GPIOxx with PDBisr set to trigger immediatly at zero value of PDB counter.
// Conversion end of each ADC and channel within the ADC ( A,B ) will be done by
// toggling second GPIO pin inside ADCisr ( this pin is also reset by PDB isr )
// GPIO PIN to low voltage .. this macro sets the PIN low.
PIN_LOW
// Initialize PIN1 and PIN2 GPIO outputs
Init_Gpio2();
// Disable ADC and PDB interrupts
disable_irq(ADC0_irq_no) ; // not ready for this interrupt yet. Plug vector first.
disable_irq(ADC1_irq_no) ; // not ready for this interrupt yet. Plug vector first.
disable_irq(PDB_irq_no) ; // not ready for this interrupt yet. Plug vector first.
// Dynamic interrupt vector modification whilst those interruts are disabled
__VECTOR_RAM[73] = (uint32)adc0_isr; // plug isr into vector table in case not there already
__VECTOR_RAM[74] = (uint32)adc1_isr; // plug isr into vector table in case not there already
__VECTOR_RAM[88] = (uint32)pdb_isr; // plug isr into vector table in case not there already
// The System Integration Module largely determines the role of the different ball map locations on Kinetis.
// When an external pin is used, the System Integration Module should be consulted and invoked as needed.
// System integration module registers start with SIM_
// Turn on the ADC0 and ADC1 clocks as well as the PDB clocks to test ADC triggered by PDB
SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK );
SIM_SCGC3 |= (SIM_SCGC3_ADC1_MASK );
SIM_SCGC6 |= SIM_SCGC6_PDB_MASK ;
// Configure System Integration Module for defaults as far as ADC
SIM_SOPT7 &= ~(SIM_SOPT7_ADC1ALTTRGEN_MASK | // selects PDB not ALT trigger
SIM_SOPT7_ADC1PRETRGSEL_MASK |
SIM_SOPT7_ADC0ALTTRGEN_MASK | // selects PDB not ALT trigger
SIM_SOPT7_ADC0ALTTRGEN_MASK) ;
SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0); // applies only in case of ALT trigger, in which case
// PDB external pin input trigger for ADC
SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0); // same for both ADCs
/////////////////////////////////////////////////////////////////////////////////////////
//PDB configured below 以下是PDB配置
// Configure the Peripheral Delay Block (PDB):
// enable PDB, pdb counter clock = busclock / 20 , continous triggers, sw trigger , and use prescaler too
PDB0_SC = PDB_SC_CONT_MASK // Contintuous, rather than one-shot, mode
| PDB_SC_PDBEN_MASK // PDB enabled
| PDB_SC_PDBIE_MASK // PDB Interrupt Enable
| PDB_SC_PRESCALER(0x5) // Slow down the period of the PDB for testing
| PDB_SC_TRGSEL(0xf) // Trigger source is Software Trigger to be invoked in this file
| PDB_SC_MULT(2); // Multiplication factor 20 for the prescale divider for the counter clock
// the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time.
PDB0_IDLY = 0x0000; // need to trigger interrupt every counter reset which happens when modulus reached
PDB0_MOD = 0xffff; // largest period possible with the slections above, so slow you can see each conversion.
// channel 0 pretrigger 0 and 1 enabled and delayed
PDB0_CH0C1 = PDB_C1_EN(0x01)
| PDB_C1_TOS(0x01)
| PDB_C1_EN(0x02)
| PDB_C1_TOS(0x02) ;
PDB0_CH0DLY0 = ADC0_DLYA ;
PDB0_CH0DLY1 = ADC0_DLYB ;
// channel 1 pretrigger 0 and 1 enabled and delayed
PDB0_CH1C1 = PDB_C1_EN(0x01)
| PDB_C1_TOS(0x01)
| PDB_C1_EN(0x02)
| PDB_C1_TOS(0x02) ;
PDB0_CH1DLY0 = ADC1_DLYA ;
PDB0_CH1DLY1 = ADC1_DLYB ;
PDB0_SC = PDB_SC_CONT_MASK // Contintuous, rather than one-shot, mode
| PDB_SC_PDBEN_MASK // PDB enabled
| PDB_SC_PDBIE_MASK // PDB Interrupt Enable
| PDB_SC_PRESCALER(0x5) // Slow down the period of the PDB for testing
| PDB_SC_TRGSEL(0xf) // Trigger source is Software Trigger to be invoked in this file
| PDB_SC_MULT(2) // Multiplication factor 20 for the prescale divider for the counter clock
| PDB_SC_LDOK_MASK; // Need to ok the loading or it will not load certain regsiters!
// the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time.
//PDB configured above 以上是PDB配置
/////////////////////////////////////////////////////////////////////////////////////////
//ADC configured below 以下是ADC配置
// setup the initial ADC default configuration
Master_Adc_Config.CONFIG1 = ADLPC_NORMAL
| ADC_CFG1_ADIV(ADIV_4)
| ADLSMP_LONG
| ADC_CFG1_MODE(MODE_16)
| ADC_CFG1_ADICLK(ADICLK_BUS);
Master_Adc_Config.CONFIG2 = MUXSEL_ADCA
| ADACKEN_DISABLED
| ADHSC_HISPEED
| ADC_CFG2_ADLSTS(ADLSTS_20) ;
Master_Adc_Config.COMPARE1 = 0x1234u ; // can be anything
Master_Adc_Config.COMPARE2 = 0x5678u ; // can be anything
// since not using
// compare feature
Master_Adc_Config.STATUS2 = ADTRG_HW
| ACFE_DISABLED
| ACFGT_GREATER
| ACREN_ENABLED
| DMAEN_DISABLED
| ADC_SC2_REFSEL(REFSEL_EXT);
Master_Adc_Config.STATUS3 = CAL_OFF
| ADCO_SINGLE
| AVGE_ENABLED
| ADC_SC3_AVGS(AVGS_32);
Master_Adc_Config.PGA = PGAEN_DISABLED
| PGACHP_NOCHOP
| PGALP_NORMAL
| ADC_PGA_PGAG(PGAG_64);
Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
// Configure ADC as it will be used, but becuase ADC_SC1_ADCH is 31,
// the ADC will be inactive. Channel 31 is just disable function.
// There really is no channel 31.
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC
// Calibrate the ADC in the configuration in which it will be used:
ADC_Cal(ADC0_BASE_PTR); // do the calibration
// The structure still has the desired configuration. So restore it.
// Why restore it? The calibration makes some adjustments to the
// configuration of the ADC. The are now undone:
// config the ADC again to desired conditions
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);
// REPEAT for BOTH ADC's. However we will only 'use' the results from
// the ADC wired to the Potentiometer on the Kinetis Tower Card.
// Repeating for ADC1:
ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // config ADC
ADC_Cal(ADC1_BASE_PTR); // do the calibration
// ADC_Read_Cal(ADC1_BASE_PTR,&CalibrationStore[0]); // store the cal
// config the ADC again to default conditions
ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config);
// *****************************************************************************
// ADC0 and ADC1 using the PDB trigger in ping pong
// *****************************************************************************
// use interrupts, single ended mode, and real channel numbers now:
Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC0_CHANA);
Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC0_CHANB);
ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC0
Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC1_CHANA);
Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC1_CHANB);
ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // config ADC1
// Note that three different balls are being sampled:
// ADC0_CHANA not used in this demo, but readings are shown
// ADC0_CHANB not used in this demo, but readings are shown
// ADC1_CHANA POT channel set the same as the following for demo: 20
// ADC1_CHANB POT channel set the same as the above for demo: 20
// The potentiometer is only on ADC1. That is the one used
// to calculate the change of the potentiometer below.
while(char_present()) in_char(); // flush terminal buffer
printf ("\n\n\n");
printf("********************************************************\n");
printf("* Running ADC0 & ADC1 HARDWARE TRIGGER by PDB *\n");
printf("* The one PDB is triggering both ADC0 and ADC1 *\n");
printf("* ADC1 A,B is the POT. Vary the POT setting. *\n");
printf("* Hit any key to exit (ADC0 readings not used) *\n");
printf("********************************************************\n");
printf ("\n\n");
// Enable the ADC and PDB interrupts in NVIC
enable_irq(ADC0_irq_no) ; // ready for this interrupt.
enable_irq(ADC1_irq_no) ; // ready for this interrupt.
enable_irq(PDB_irq_no) ; // ready for this interrupt.
// In case previous test did not end with interrupts enabled, enable used ones.
EnableInterrupts ;
cycle_flags=0;
PDB0_SC |= PDB_SC_SWTRIG_MASK ; // kick off the PDB - just once
//The system is now working!!!! The PDB is *continuously* triggering ADC
// conversions. Now, to display the results! The line above
// was the SOFTWARE TRIGGER...
// The demo will continue as long as no character is pressed on the terminal.
while(!char_present()) // as long as no operater intervention, keep running this:
{
while( cycle_flags != ( ADC0A_DONE | ADC0B_DONE | ADC1A_DONE | ADC1B_DONE )); // wait for one complete cycle
printf("R0A=%6d R0B=%6d R1A=%6d R1B=%6d POT=%6d\r",
result0A,result0B,result1A,result1B, exponentially_filtered_result1);
}
// disable the PDB
PDB0_SC = 0 ;
// Disable the ADC and PDB interrupts in NVIC
disable_irq(ADC0_irq_no) ; // through with this interrupt.
disable_irq(ADC1_irq_no) ; // through with this interrupt.
disable_irq(PDB_irq_no) ; // through with this interrupt.
printf ("\n\n\n");
printf("********************************************************\n");
printf("* Demonstration ended at operator request *\n");
printf("* ADC0 & ADC1 PDB TRIGGER DEMO COMPLETE *\n");
printf("********************************************************\n");
printf ("\n\n");
return 0;
}
void IrScan(){
int i;
turnOffUs();
EnqueueString("qwer");
EnqueueChar('i');
EnqueueChar('\n');
EnqueueInt16((uint16_t)x);
EnqueueInt16((uint16_t)y);
if(carDirection==-1)EnqueueInt16((uint16_t)(carDirection+1));
else EnqueueInt16((uint16_t)carDirection);
TPM1_C1V = ZeroDegree;//start at degree 0 -look forward
delay(50);
TPM0_C4V = FullDegree;//start at degree 180 -look forward
delay(150);
int counter=0;
while (TPM0_C4V>=FullDegree-3.96*99){//99 degree scan
ADC0_SC1A=ADC_SC1_ADCH(7);
TPM0_C4V-=9;
delay(25);
IrSampels[43-counter]=ADC0_RA;
ADC0_SC1A=ADC_SC1_ADCH(6);
TPM1_C1V+=9;
delay(25);
IrSampels[counter+44]=ADC0_RA;
counter++;
}
delay(25);
Servo1SetPos(7);
delay(25);
Servo2SetPos(7);
delay(50);
//conversion from adc sample to distance- left servo
for(i=0;i<44;i++){
IrSampels[i]=DistanceMeasuring1(IrSampels[i]);
EnqueueInt16(IrSampels[i]);
}
//conversion from adc sample to distance-right servo
for(i=44;i<88;i++){
IrSampels[i]=DistanceMeasuring2(IrSampels[i]);
EnqueueInt16(IrSampels[i]);
}
//left servo
for(i=0;i<44;i++){
//removing noises
if((IrSampels[i]<140)&&(i==0||(abs(IrSampels[i-1]-IrSampels[i])<15&&abs(IrSampels[i+1]-IrSampels[i])<15))){
//calculate the coordination of the block
int xIndex=(int)round(x-0.5-(sin(0.01745*((43-i)*2.51 + carDirection))*IrSampels[i]/5));
int yIndex=(int)round(y+cos(0.01745*((43-i)*2.51 + carDirection))*IrSampels[i]/5);
//adding blocks to metrix
if((xIndex/6+1>0&&xIndex/6+1<15)&&yIndex/6>=0&&yIndex/6<16){
if(maze[xIndex/6+1][yIndex/6]=='r') maze[xIndex/6][yIndex/6]='H';
else if(xIndex/6==(int)(x/6)&&xIndex+2<(int)x) maze[xIndex/6][yIndex/6]='H';
else maze[xIndex/6+1][yIndex/6]='H';
}
}
}
//right servo
for(i=44;i<88;i++){
//removing noises
if((IrSampels[i]<140)&&(i==87||(abs(IrSampels[i-1]-IrSampels[i])<15&&abs(IrSampels[i+1]-IrSampels[i])<15))){
//calculate the coordination of the block
int xIndex=(int)round(x+0.5+(sin(0.01745*((i-44)*2.27 + carDirection))*IrSampels[i]/5));
int yIndex=(int)round(y+cos(0.01745*((i-44)*2.27 + carDirection))*IrSampels[i]/5);
//adding blocks to metrix
if((xIndex/6+1>0&&xIndex/6+1<15)&&yIndex/6>=0&&yIndex/6<16){
if(maze[xIndex/6+1][yIndex/6]=='r') maze[xIndex/6+2][yIndex/6]='H';
else if(xIndex/6==(int)x/6&&xIndex-2>(int)x) maze[xIndex/6+2][yIndex/6]='H';
else maze[xIndex/6+1][yIndex/6]='H';
}
}
}
EnqueueChar(0x1A);
EnqueueChar('\n');
EnqueueChar(0xff);
UART0_C2 |= UART_C2_TIE_MASK; //enable transmit interrupt for start sendding
turnOnUs();
}
turnOnIr(){
ADC0_SC1A = ADC_SC1_ADCH(7)|ADC_SC1_AIEN_MASK;
adcMux=0;
}
