void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
uint8_t i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16) {
return;
}
for (i = 1; i <= length; i++) {
if (i <= 6) {
reg32_3 |= (channel[i - 1] << ((i - 1) * 5));
}
if ((i > 6) & (i <= 12)) {
reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5));
}
if ((i > 12) & (i <= 16)) {
reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5));
}
}
reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB);
ADC_SQR1(adc) = reg32_1;
ADC_SQR2(adc) = reg32_2;
ADC_SQR3(adc) = reg32_3;
}
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0, reg32_4 = 0;
uint8_t i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16) {
return;
}
for (i = 1; i <= length; i++) {
if (i <= 4) {
reg32_1 |= (channel[i - 1] << (i * 6));
}
if ((i > 4) & (i <= 9)) {
reg32_2 |= (channel[i - 1] << ((i - 4 - 1) * 6));
}
if ((i > 9) & (i <= 14)) {
reg32_3 |= (channel[i - 1] << ((i - 9 - 1) * 6));
}
if ((i > 14) & (i <= 16)) {
reg32_4 |= (channel[i - 1] << ((i - 14 - 1) * 6));
}
}
reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB);
ADC_SQR1(adc) = reg32_1;
ADC_SQR2(adc) = reg32_2;
ADC_SQR3(adc) = reg32_3;
ADC_SQR4(adc) = reg32_4;
}
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
uint32_t fifth6 = 0;
uint32_t fourth6 = 0;
uint32_t third6 = 0;
uint32_t second6 = 0;
uint32_t first6 = 0;
uint8_t i = 0;
if (length > ADC_SQR_MAX_CHANNELS_REGULAR) {
return;
}
for (i = 1; i <= length; i++) {
if (i <= 6) {
first6 |= (channel[i - 1] << ((i - 1) * 5));
}
if ((i > 6) & (i <= 12)) {
second6 |= (channel[i - 1] << ((i - 6 - 1) * 5));
}
if ((i > 12) & (i <= 18)) {
third6 |= (channel[i - 1] << ((i - 12 - 1) * 5));
}
if ((i > 18) & (i <= 24)) {
fourth6 |= (channel[i - 1] << ((i - 18 - 1) * 5));
}
if ((i > 24) & (i <= 28)) {
fifth6 |= (channel[i - 1] << ((i - 24 - 1) * 5));
}
}
#if defined(ADC_SQR5)
ADC_SQR1(adc) = fifth6 | ((length - 1) << ADC_SQR1_L_LSB);
ADC_SQR2(adc) = fourth6;
ADC_SQR3(adc) = third6;
ADC_SQR4(adc) = second6;
ADC_SQR5(adc) = first6;
#else
ADC_SQR1(adc) = third6 | ((length - 1) << ADC_SQR1_L_LSB);
ADC_SQR2(adc) = second6;
ADC_SQR3(adc) = first6;
#endif
}
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
uint32_t reg32[5] = {0,0,0,0,0};
uint8_t i = 0;
/* Maximum sequence length is 28 channels. */
if (length > 28)
return;
for (i = 0; i < length; i++)
reg32[4 - i/6] |= (channel[i] << ((i%6)*5));
reg32[0] |= ((length -1) << ADC_SQR1_L_LSB);
ADC_SQR1(adc) = reg32[0];
ADC_SQR2(adc) = reg32[1];
ADC_SQR3(adc) = reg32[2];
ADC_SQR4(adc) = reg32[3];
ADC_SQR5(adc) = reg32[4];
}
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
{
u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
u8 i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16)
return;
for (i = 1; i <= length; i++) {
if (i <= 6)
reg32_3 |= (channel[i - 1] << ((i - 1) * 5));
if ((i > 6) & (i <= 12))
reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5));
if ((i > 12) & (i <= 16))
reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5));
}
reg32_1 |= ((length -1) << ADC_SQR1_L_LSB);
ADC_SQR1(adc) = reg32_1;
ADC_SQR2(adc) = reg32_2;
ADC_SQR3(adc) = reg32_3;
}
/**
* @brief Initializes the ADCx peripheral according to the specified parameters
* in the ADC_InitStruct without initializing the ADC MSP.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
/* Set ADC parameters */
/* Set the ADC clock prescaler */
ADC->CCR &= ~(ADC_CCR_ADCPRE);
ADC->CCR |= hadc->Init.ClockPrescaler;
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
hadc->Instance->CR1 |= hadc->Init.Resolution;
/* Set ADC data alignment */
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
hadc->Instance->CR2 |= hadc->Init.DataAlign;
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
}
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
if(hadc->Init.DiscontinuousConvMode != DISABLE)
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
/* Enable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
}
else
{
/* Disable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
}
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
}
/**
* @brief Configures for the selected ADC injected channel its corresponding
* rank in the sequencer and its sample time.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param sConfigInjected: ADC configuration structure for injected channel.
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
{
#ifdef USE_FULL_ASSERT
uint32_t tmp = 0;
#endif /* USE_FULL_ASSERT */
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
#ifdef USE_FULL_ASSERT
tmp = ADC_GET_RESOLUTION(hadc);
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
}
/* Process locked */
__HAL_LOCK(hadc);
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
/*---------------------------- ADCx JSQR Configuration -----------------*/
hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
/* Rank configuration */
/* Clear the old SQx bits for the selected rank */
hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
/* Set the SQx bits for the selected rank */
hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
}
if (sConfigInjected->AutoInjectedConv != DISABLE)
{
/* Enable the selected ADC automatic injected group conversion */
hadc->Instance->CR1 |= ADC_CR1_JAUTO;
}
else
{
/* Disable the selected ADC automatic injected group conversion */
hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
}
if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
{
/* Enable the selected ADC injected discontinuous mode */
hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
}
else
{
/* Disable the selected ADC injected discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
}
switch(sConfigInjected->InjectedRank)
{
case 1:
/* Set injected channel 1 offset */
hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
break;
case 2:
/* Set injected channel 2 offset */
hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
break;
case 3:
/* Set injected channel 3 offset */
hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
break;
default:
/* Set injected channel 4 offset */
hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
break;
}
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
}
/* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
