void InitPeripheralClocks(void)
{
EALLOW;
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
SysCtrlRegs.HISPCP.all = 0x0001;
SysCtrlRegs.LOSPCP.all = 0x0002;
// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
// XTIMCLK = SYSCLKOUT/2
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
// Enable XCLKOUT
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// Peripheral clock enables set for the selected peripherals.
// If you are not using a peripheral leave the clock off
// to save on power.
//
// Note: not all peripherals are available on all 2833x derivates.
// Refer to the datasheet for your particular device.
//
// This function is not written to be an example of efficient code.
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
// *IMPORTANT*
// The ADC_cal function, which copies the ADC calibration values from TI reserved
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
ADC_cal();
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4
SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5
SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
EDIS;
}
void initAdc(void) {
// Load the calibration value
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
EDIS;
DELAY_US( ADC_usDELAY );
// Reset the ADC Module
AdcRegs.ADCTRL1.all = 0x4000;
asm(" NOP");
asm(" NOP");
DELAY_US( ADC_usDELAY );
// Power up bandgap / reference circuitry
AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x03;
DELAY_US( ADC_usDELAY );
// Power up rest of ADC
AdcRegs.ADCTRL3.bit.ADCPWDN = 1;
DELAY_US( ADC_usDELAY );
// Setup ADCTRL 3 Core Clock Divider to divide by 8
AdcRegs.ADCTRL3.bit.ADCCLKPS = 8;
// Setup ADCTRL1 Register
// Acquisition window size of 16
// Core clock prescaler set (/2)
// Cascaded mode
AdcRegs.ADCTRL1.all = 0x0F90;
// Setup ADCTRL2 Register
// Reset Sequencer
// Interrupt enabled (INT SEQ1)
AdcRegs.ADCTRL2.all = 0x4800;
// Specify 16 conversions
AdcRegs.ADCMAXCONV.all = 0x000F;
// Configure channel selection;
AdcRegs.ADCCHSELSEQ1.all = 0x3210;
AdcRegs.ADCCHSELSEQ2.all = 0x7654;
AdcRegs.ADCCHSELSEQ3.all = 0xBA98;
AdcRegs.ADCCHSELSEQ4.all = 0xFEDC;
// Run the calibration routines
EALLOW;
ADC_cal();
EDIS;
// Setup the ADC reference select register
AdcRegs.ADCREFSEL.bit.REF_SEL = 0;
// 5ms delay before any conversion is done
DELAY_US( ADC_usDELAY );
// Enable SEQ1_INT in PIE
PieCtrlRegs.PIEIER1.bit.INTx6 = 1;
// Enable INT1 in IER
IER |= 0x0001;
initFilter();
}
/*=============================================================================*
* FUNCTION: InitAdc()
* PURPOSE : ADC hardware module initialization.
* INPUT:
* void
*
* RETURN:
* void
*
* CALLS:
* void
*
* CALLED BY:
* Main.c
*
*============================================================================*/
void InitAdc(void)
{ // start of InitAdc()
//--- Reset the ADC module
AdcRegs.ADCTRL1.bit.RESET = 1; // Reset the ADC
asm(" RPT #22 || NOP"); // Must for ADC reset to take effect
//--- Call the ADC_cal() function located in the Boot ROM.
/* ADC_cal_func_ptr is a macro defined in the file 5KW_MAINHEADER.h This
macro simply defines ADC_cal_func_ptr to be a function pointer to
the correct address in the boot ROM. */
ADC_cal();
//--- Select the ADC reference
AdcRegs.ADCREFSEL.bit.REF_SEL = 0x1;
//bit1-0, 00-internal, 01-external 2.048V, 10-1.500V, 11-1.024V
// Power-up reference and main ADC sampling mode
AdcRegs.ADCTRL3.all = 0x00E7;
//bit15-8, 0, reserved
//bit7-6, 11, ADCBGRFDN, reference power, 00=off, 11=on
//bit5, 1, ADCPWDN, main ADC power, 0=off, 1=on
//bit4-1, 0011, ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
// =75MHz/(2*3)=12.5MHz; can be changed to 12.5MHz, by 0110 to 0011
//bit0, 1, SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling
DelayUs(1000); // Wait 5ms before using the ADC
// ADC has started, necessary config for Channel and Conversion Mode needed.
//--- for SVPWM data acquisition simultaneously in cascaded mode
AdcRegs.ADCMAXCONV.all = 0x0007; //8 double's conversions
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0000; // Convert Channel ADCINA/B0
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x0001; // Convert Channel ADCINA/B1
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x0002; // Convert Channel ADCINA/B2
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x0003; // Convert Channel ADCINA/B3
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x0004; // Convert Channel ADCINA/B4
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x0005; // Convert Channel ADCINA/B5
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x0006; // Convert Channel ADCINA/B6
AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x0007; // Convert Channel ADCINA/B7
AdcRegs.ADCTRL1.all = 0x0310; // 0000 0011 0001 0000
//bit15, 0, reserved
//bit14, 0, RESET, 0=no action, 1=reset ADC
//bit13-12, 00, SUSMOD, 00=ignore emulation suspend
//bit11-8, 0011, ACQ_PS (Acquisition), Sampling Window Width =
// (ACQ_PS+1) x ADCCLK Period = 4*(1/12.5MHz)=0.32us.
//bit7, 0, CPS (Core clock), 0: ADCCLK=FCLK/1, 1: ADCCLK=FCLK/2
//bit6, 0, CONT_RUN, 0=start/stop mode, 1=continuous run
//bit5, 0, SEQ_OVRD, 0=disabled, 1=enabled
//bit4, 1, SEQ_CASC, 0=dual sequencer, 1=cascaded sequencer
//bit3-0,0000, reserved
/* ADCCLK=HSPCLK/(2*ADCCLKPS_Patameter*(CPS_Parameter+1))=75/(2*3)
=12.5MHz, and the total ADC time is, T(SMODE=1)=(2.5+(1+ACQ_PS)+5+(3+ACQ_PS)*7)*ADCCLK
=(29.5+ACQ_PS*8)*80ns=4.28us, this is the time duration from ADC_trigging
to All_ADC_result_ready. Proper adjustment should be done to satisfy
minimum interval of other higher frequency sampling and digital process.
*/
AdcRegs.ADCTRL2.all = 0x8900;
// bit15, 1, ePWM_SOCB_SEQ, 0=no action
// bit14, 0, RST_SEQ1, 0=no action
// bit13, 0, SOC_SEQ1, 0=clear any pending SOCs, 1=software trigger
// bit12, 0, reserved
// bit11, 1, INT_ENA_SEQ1, 1=enable interrupt
// bit10, 0, INT_MOD_SEQ1, 0=int on every SEQ1 conv,
// 1=int on every other SEQ1 conv
// bit9, 0, reserved
// bit8, 1, ePWM_SOCA_SEQ1, 1=SEQ1 start from ePWM_SOCA trigger
// bit7, 0, EXT_SOC_SEQ1, 1=SEQ1 start from ADCSOC pin
// bit6, 0, RST_SEQ2, 0=no action
// bit5, 0, SOC_SEQ2, no effect in cascaded mode
// bit4, 0, reserved
// bit3, 0, INT_ENA_SEQ2, 0=int disabled
// bit2, 0, INT_MOD_SEQ2, 0=int on every other SEQ2 conv
// bit1, 0, reserved
// bit0, 0, ePWM_SOCB_SEQ2, 0=no action
//--- Enable the ADC interrupt
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable ADCINT in PIE group 1
for (AD_Time_Delay=0;AD_Time_Delay<=2;AD_Time_Delay++)
{
AdcRegs.ADCTRL2.bit.SOC_SEQ1=1; //软件启动AD
while(AdcRegs.ADCST.bit.INT_SEQ1!=1)
{
DelayUs(200);
}
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // RESET SEQ1
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // 清除SEQ1中断标志
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // 清除中断1标志
}
} // end of InitAdc()
int calculate_method::DWI_Compute(string input,string output,DWIConstTable *DWIConst)
{
const int MIN = 900;
const Uint16 *pixel1;
const Uint16 *pixel2;
DcmFileFormat fileformat1;
DcmFileFormat fileformat2;
int sum=-1;
string temInaddress = input;
string temOutaddress = output;
cout<<"after DWI sort"<<endl;
for(int i=0;i<DWIConst->DSliceNum;++i)
{
int height,width;
height=256;
width=256;
OFCondition os1 =fileformat2.loadFile((temInaddress+"IM0-"+itos(i)).c_str());//+"_"+itos(SL)
OFCondition os2 =fileformat1.loadFile((temInaddress+"IM1-"+itos(i)).c_str());//+"_"+itos(SL)
//cout<<image->getHeight()<<endl;
if(os1.good() && os2.good()){
}
else{
printf("wrong format\n");
continue;
}
fileformat1.getDataset()->findAndGetUint16Array(DCM_PixelData, pixel1);
fileformat2.getDataset()->findAndGetUint16Array(DCM_PixelData, pixel2);
DcmDataset *ds=fileformat2.getDataset();
sum=-1;
for(int j=0;j<height;++j)
{
for(int k=0;k<width;++k)
{
pixelBmp[j * 256 + k]=0;
if(pixel1[j*height+k] >= MIN)
{
pixel[j * 256 + k]=ADC_cal(1000,(_orig)pixel1[j*height+k],(_orig)pixel2[j*height+k]);
}
else
{
pixel[j * 256 + k]=0.0;
}
if(pixel[j * 256 + k]>= DWIConst->ADCMin)//)pixel[j][k]<=(2100*0.000001) &&pixel[j][k]<=600*0.000001
{
if(pixel[j * 256 + k]<DWIConst->ADCMax)
{
pixelBmp[j * 256 + k]=(Uint16)(pixel[j * 256 + k]*1000000);
}else
{
pixelBmp[j * 256 + k]=(Uint16)(DWIConst->ADCMax*1000000);
}
}else
{
pixelBmp[j * 256 + k]=0;
}
}
}
ds->putAndInsertString(DCM_WindowCenter,"1300");//1300
ds->putAndInsertString(DCM_WindowWidth,"2100");//2100
ds->putAndInsertUint16Array(DCM_PixelData,pixelBmp,256*256);
fileformat2.saveFile((temOutaddress+"ADC_"+itos(i+1)).c_str(),EXS_LittleEndianExplicit);//+"_"+itos(SL)
}
//delete for new
puts("DWI DONE");
return 0;
}
