Ejemplo n.º 1
0
static void amvdec_pg_enable(bool enable)
{
    ulong timeout;

    if (enable) {
        AMVDEC_CLK_GATE_ON(MDEC_CLK_PIC_DC);
        AMVDEC_CLK_GATE_ON(MDEC_CLK_DBLK);
        AMVDEC_CLK_GATE_ON(MC_CLK);
        AMVDEC_CLK_GATE_ON(IQIDCT_CLK);
        //AMVDEC_CLK_GATE_ON(VLD_CLK);
        AMVDEC_CLK_GATE_ON(AMRISC);
    } else {
        AMVDEC_CLK_GATE_OFF(AMRISC);

        timeout = jiffies + HZ / 10;

        while (READ_VREG(MDEC_PIC_DC_STATUS) != 0) {
            if (time_after(jiffies, timeout)) {
                WRITE_VREG_BITS(MDEC_PIC_DC_CTRL, 1, 0, 1);
                WRITE_VREG_BITS(MDEC_PIC_DC_CTRL, 0, 0, 1);
                READ_VREG(MDEC_PIC_DC_STATUS);
                READ_VREG(MDEC_PIC_DC_STATUS);
                READ_VREG(MDEC_PIC_DC_STATUS);
                break;
            }
        }

        AMVDEC_CLK_GATE_OFF(MDEC_CLK_PIC_DC);

        timeout = jiffies + HZ / 10;

        while (READ_VREG(DBLK_STATUS) & 1) {
            if (time_after(jiffies, timeout)) {
                WRITE_VREG(DBLK_CTRL, 3);
                WRITE_VREG(DBLK_CTRL, 0);
                READ_VREG(DBLK_STATUS);
                READ_VREG(DBLK_STATUS);
                READ_VREG(DBLK_STATUS);
                break;
            }
        }
        AMVDEC_CLK_GATE_OFF(MDEC_CLK_DBLK);

        timeout = jiffies + HZ / 10;

        while (READ_VREG(MC_STATUS0) & 1) {
            if (time_after(jiffies, timeout)) {
                SET_VREG_MASK(MC_CTRL1, 0x9);
                CLEAR_VREG_MASK(MC_CTRL1, 0x9);
                READ_VREG(MC_STATUS0);
                READ_VREG(MC_STATUS0);
                READ_VREG(MC_STATUS0);
                break;
            }
        }
        AMVDEC_CLK_GATE_OFF(MC_CLK);

        timeout = jiffies + HZ / 10;
        while (READ_VREG(DCAC_DMA_CTRL) & 0x8000) {
            if (time_after(jiffies, timeout)) {
                break;
            }
        }

        AMVDEC_CLK_GATE_OFF(IQIDCT_CLK);

        //AMVDEC_CLK_GATE_OFF(VLD_CLK);
    }
}
Ejemplo n.º 2
0
static void amvdec_pg_enable(bool enable)
{
	ulong timeout;

	if (enable) {
		AMVDEC_CLK_GATE_ON(MDEC_CLK_PIC_DC);
		AMVDEC_CLK_GATE_ON(MDEC_CLK_DBLK);
		AMVDEC_CLK_GATE_ON(MC_CLK);
		AMVDEC_CLK_GATE_ON(IQIDCT_CLK);
		/* AMVDEC_CLK_GATE_ON(VLD_CLK); */
		AMVDEC_CLK_GATE_ON(AMRISC);
		/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD */
		if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8)
			WRITE_VREG(GCLK_EN, 0x3ff);
		/* #endif */
		CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31);
	} else {

		AMVDEC_CLK_GATE_OFF(AMRISC);
		timeout = jiffies + HZ / 10;

		while (READ_VREG(MDEC_PIC_DC_STATUS) != 0) {
			if (time_after(jiffies, timeout)) {
				WRITE_VREG_BITS(MDEC_PIC_DC_CTRL, 1, 0, 1);
				WRITE_VREG_BITS(MDEC_PIC_DC_CTRL, 0, 0, 1);
				READ_VREG(MDEC_PIC_DC_STATUS);
				READ_VREG(MDEC_PIC_DC_STATUS);
				READ_VREG(MDEC_PIC_DC_STATUS);
				break;
			}
		}

		AMVDEC_CLK_GATE_OFF(MDEC_CLK_PIC_DC);
		timeout = jiffies + HZ / 10;

		while (READ_VREG(DBLK_STATUS) & 1) {
			if (time_after(jiffies, timeout)) {
				WRITE_VREG(DBLK_CTRL, 3);
				WRITE_VREG(DBLK_CTRL, 0);
				READ_VREG(DBLK_STATUS);
				READ_VREG(DBLK_STATUS);
				READ_VREG(DBLK_STATUS);
				break;
			}
		}
		AMVDEC_CLK_GATE_OFF(MDEC_CLK_DBLK);
		timeout = jiffies + HZ / 10;

		while (READ_VREG(MC_STATUS0) & 1) {
			if (time_after(jiffies, timeout)) {
				SET_VREG_MASK(MC_CTRL1, 0x9);
				CLEAR_VREG_MASK(MC_CTRL1, 0x9);
				READ_VREG(MC_STATUS0);
				READ_VREG(MC_STATUS0);
				READ_VREG(MC_STATUS0);
				break;
			}
		}
		AMVDEC_CLK_GATE_OFF(MC_CLK);
		timeout = jiffies + HZ / 10;
		while (READ_VREG(DCAC_DMA_CTRL) & 0x8000) {
			if (time_after(jiffies, timeout))
				break;
		}
		AMVDEC_CLK_GATE_OFF(IQIDCT_CLK);
		/* AMVDEC_CLK_GATE_OFF(VLD_CLK); */
	}
}