/************************************************************************************//**
** \brief Initializes the UART communication interface.
** \return none.
**
****************************************************************************************/
void UartInit(void)
{
blt_int32u baud_reg_value; /* baudrate register value */
/* the current implementation supports UART0. throw an assertion error in case
* a different UART channel is configured.
*/
ASSERT_CT(BOOT_COM_UART_CHANNEL_INDEX == 0);
/* disable UART related interrupt generation. this driver works in polling mode */
U0IER = 0;
/* clear interrupt id register */
U0IIR = 0;
/* clear line status register */
U0LSR = 0;
/* set divisor latch DLAB = 1 so buadrate can be configured */
U0LCR = UART_DLAB;
/* Baudrate calculation:
* y = BOOT_CPU_SYSTEM_SPEED_KHZ * 1000 / 16 / BOOT_COM_UART_BAUDRATE and add
* smartness to automatically round the value up/down using the following trick:
* y = x/n can round with y = (x + (n + 1)/2 ) / n
*/
/* check that baudrate register value is not 0 */
ASSERT_CT((((BOOT_CPU_SYSTEM_SPEED_KHZ*1000/16)+((BOOT_COM_UART_BAUDRATE+1)/2))/ \
BOOT_COM_UART_BAUDRATE) > 0);
/* check that baudrate register value is not greater than max 16-bit unsigned value */
ASSERT_CT((((BOOT_CPU_SYSTEM_SPEED_KHZ*1000/16)+((BOOT_COM_UART_BAUDRATE+1)/2))/ \
BOOT_COM_UART_BAUDRATE) <= 65535);
baud_reg_value = (((BOOT_CPU_SYSTEM_SPEED_KHZ*1000/16)+ \
((BOOT_COM_UART_BAUDRATE+1)/2))/BOOT_COM_UART_BAUDRATE);
/* write the calculated baudrate selector value to the registers */
U0DLL = (blt_int8u)baud_reg_value;
U0DLM = (blt_int8u)(baud_reg_value >> 8);
/* configure 8 data bits, no parity and 1 stop bit and set DLAB = 0 */
U0LCR = UART_MODE_8N1;
/* enable and reset transmit and receive FIFO. necessary for UART operation */
U0FCR = UART_FIFO_RX1;
} /*** end of UartInit ***/
/****************************************************************************************
** NAME: Init
** PARAMETER: none
** RETURN VALUE: none
** DESCRIPTION: Initializes the microcontroller. The interrupts are disabled, the
** clocks are configured and the flash wait states are configured.
**
****************************************************************************************/
static void Init(void)
{
volatile blt_int32u StartUpCounter = 0, HSEStatus = 0;
blt_int32u pll_multiplier;
/* reset the RCC clock configuration to the default reset state (for debug purpose) */
/* set HSION bit */
RCC->CR |= (blt_int32u)0x00000001;
/* reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
RCC->CFGR &= (blt_int32u)0xF8FF0000;
/* reset HSEON, CSSON and PLLON bits */
RCC->CR &= (blt_int32u)0xFEF6FFFF;
/* reset HSEBYP bit */
RCC->CR &= (blt_int32u)0xFFFBFFFF;
/* reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (blt_int32u)0xFF80FFFF;
/* disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* enable HSE */
RCC->CR |= ((blt_int32u)RCC_CR_HSEON);
/* wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != 1500));
/* check if time out was reached */
if ((RCC->CR & RCC_CR_HSERDY) == RESET)
{
/* cannot continue when HSE is not ready */
ASSERT_RT(BLT_FALSE);
}
/* enable flash prefetch buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* reset flash wait state configuration to default 0 wait states */
FLASH->ACR &= (blt_int32u)((blt_int32u)~FLASH_ACR_LATENCY);
#if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000)
/* configure 2 flash wait states */
FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2;
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)
/* configure 1 flash wait states */
FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFGR |= (blt_int32u)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK/2 */
RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK/2 */
RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE1_DIV2;
/* reset PLL configuration */
RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | \
RCC_CFGR_PLLMULL));
/* assert that the pll_multiplier is between 2 and 16 */
ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) >= 2);
ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) <= 16);
/* calculate multiplier value */
pll_multiplier = BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ;
/* convert to register value */
pll_multiplier = (blt_int32u)((pll_multiplier - 2) << 18);
/* set the PLL multiplier and clock source */
RCC->CFGR |= (blt_int32u)(RCC_CFGR_PLLSRC_HSE | pll_multiplier);
/* enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* select PLL as system clock source */
RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_SW));
RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL;
/* wait till PLL is used as system clock source */
while ((RCC->CFGR & (blt_int32u)RCC_CFGR_SWS) != (blt_int32u)0x08)
{
}
/* enable clocks for CAN transmitter and receiver pins (GPIOB and AFIO) */
RCC->APB2ENR |= (blt_int32u)(0x00000008 | 0x00000001);
/* configure CAN Rx (GPIOB8) as alternate function input pull-up */
/* first reset the configuration */
GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 0);
/* CNF8[1:0] = %10 and MODE8[1:0] = %00 */
GPIOB->CRH |= (blt_int32u)((blt_int32u)0x8 << 0);
/* configure CAN Tx (GPIOB9) as alternate function push-pull */
/* first reset the configuration */
GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 4);
/* CNF9[1:0] = %10 and MODE9[1:0] = %11 */
GPIOB->CRH |= (blt_int32u)((blt_int32u)0xb << 4);
/* remap CAN1 pins to PortB */
AFIO->MAPR &= ~(blt_int32u)((blt_int32u)0x3 << 13);
AFIO->MAPR |= (blt_int32u)((blt_int32u)0x2 << 13);
/* enable clocks for CAN controller peripheral */
RCC->APB1ENR |= (blt_int32u)0x02000000;
} /*** end of Init ***/
/************************************************************************************//**
** \brief Initializes the microcontroller.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
volatile blt_int32u StartUpCounter = 0, HSEStatus = 0;
blt_int32u pll_multiplier;
#if (BOOT_FILE_LOGGING_ENABLE > 0) && (BOOT_COM_UART_ENABLE == 0)
GPIO_InitTypeDef GPIO_InitStruct;
USART_InitTypeDef USART_InitStruct;
#endif
/* reset the RCC clock configuration to the default reset state (for debug purpose) */
/* set HSION bit */
RCC->CR |= (blt_int32u)0x00000001;
/* reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
RCC->CFGR &= (blt_int32u)0xF8FF0000;
/* reset HSEON, CSSON and PLLON bits */
RCC->CR &= (blt_int32u)0xFEF6FFFF;
/* reset HSEBYP bit */
RCC->CR &= (blt_int32u)0xFFFBFFFF;
/* reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (blt_int32u)0xFF80FFFF;
/* disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* enable HSE */
RCC->CR |= ((blt_int32u)RCC_CR_HSEON);
/* wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
}
while((HSEStatus == 0) && (StartUpCounter != 1500));
/* check if time out was reached */
if ((RCC->CR & RCC_CR_HSERDY) == RESET)
{
/* cannot continue when HSE is not ready */
ASSERT_RT(BLT_FALSE);
}
/* enable flash prefetch buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* reset flash wait state configuration to default 0 wait states */
FLASH->ACR &= (blt_int32u)((blt_int32u)~FLASH_ACR_LATENCY);
#if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000)
/* configure 2 flash wait states */
FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2;
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)
/* configure 1 flash wait states */
FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1;
#endif
/* HCLK = SYSCLK */
RCC->CFGR |= (blt_int32u)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK/2 */
RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK/2 */
RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE1_DIV2;
/* reset PLL configuration */
RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | \
RCC_CFGR_PLLMULL));
/* assert that the pll_multiplier is between 2 and 16 */
ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) >= 2);
ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) <= 16);
/* calculate multiplier value */
pll_multiplier = BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ;
/* convert to register value */
pll_multiplier = (blt_int32u)((pll_multiplier - 2) << 18);
/* set the PLL multiplier and clock source */
RCC->CFGR |= (blt_int32u)(RCC_CFGR_PLLSRC_HSE | pll_multiplier);
/* enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* select PLL as system clock source */
RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_SW));
RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL;
/* wait till PLL is used as system clock source */
while ((RCC->CFGR & (blt_int32u)RCC_CFGR_SWS) != (blt_int32u)0x08)
{
}
#if (BOOT_COM_CAN_ENABLE > 0)
/* enable clocks for CAN transmitter and receiver pins (GPIOB and AFIO) */
RCC->APB2ENR |= (blt_int32u)(0x00000008 | 0x00000001);
/* configure CAN Rx (GPIOB8) as alternate function input pull-up */
/* first reset the configuration */
GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 0);
/* CNF8[1:0] = %10 and MODE8[1:0] = %00 */
GPIOB->CRH |= (blt_int32u)((blt_int32u)0x8 << 0);
/* configure CAN Tx (GPIOB9) as alternate function push-pull */
/* first reset the configuration */
GPIOB->CRH &= ~(blt_int32u)((blt_int32u)0xf << 4);
/* CNF9[1:0] = %10 and MODE9[1:0] = %11 */
GPIOB->CRH |= (blt_int32u)((blt_int32u)0xb << 4);
/* remap CAN1 pins to PortB */
AFIO->MAPR &= ~(blt_int32u)((blt_int32u)0x3 << 13);
AFIO->MAPR |= (blt_int32u)((blt_int32u)0x2 << 13);
/* enable clocks for CAN controller peripheral */
RCC->APB1ENR |= (blt_int32u)0x02000000;
#endif
#if (BOOT_COM_UART_ENABLE > 0)
/* enable clock for USART2 peripheral */
RCC->APB1ENR |= (blt_int32u)0x00020000;
/* enable clocks for USART2 transmitter and receiver pins (GPIOA and AFIO) */
RCC->APB2ENR |= (blt_int32u)(0x00000004 | 0x00000001);
/* configure USART2 Tx (GPIOA2) as alternate function push-pull */
/* first reset the configuration */
GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 8);
/* CNF2[1:0] = %10 and MODE2[1:0] = %11 */
GPIOA->CRL |= (blt_int32u)((blt_int32u)0xb << 8);
/* configure USART2 Rx (GPIOA3) as alternate function input floating */
/* first reset the configuration */
GPIOA->CRL &= ~(blt_int32u)((blt_int32u)0xf << 12);
/* CNF2[1:0] = %01 and MODE2[1:0] = %00 */
GPIOA->CRL |= (blt_int32u)((blt_int32u)0x4 << 12);
#elif (BOOT_FILE_LOGGING_ENABLE > 0)
/* enable UART peripheral clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
/* enable GPIO peripheral clock for transmitter and receiver pins */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE);
/* configure USART Tx as alternate function push-pull */
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOA, &GPIO_InitStruct);
/* Configure USART Rx as alternate function input floating */
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_3;
GPIO_Init(GPIOA, &GPIO_InitStruct);
/* configure UART communcation parameters */
USART_InitStruct.USART_BaudRate = BOOT_COM_UART_BAUDRATE;
USART_InitStruct.USART_WordLength = USART_WordLength_8b;
USART_InitStruct.USART_StopBits = USART_StopBits_1;
USART_InitStruct.USART_Parity = USART_Parity_No;
USART_InitStruct.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStruct.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(USART2, &USART_InitStruct);
/* enable UART */
USART_Cmd(USART2, ENABLE);
#endif
} /*** end of Init ***/
