void nandflash_hw_init(void)
{
const struct pio_desc nand_pins[] = {
{"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_F},
{"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_F},
{"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_F},
{"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_F},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_DEFAULT, PIO_OUTPUT},
{"D0", AT91C_PIN_PA(0), 0, PIO_PULLUP, PIO_PERIPH_F},
{"D1", AT91C_PIN_PA(1), 0, PIO_PULLUP, PIO_PERIPH_F},
{"D2", AT91C_PIN_PA(2), 0, PIO_PULLUP, PIO_PERIPH_F},
{"D3", AT91C_PIN_PA(3), 0, PIO_PULLUP, PIO_PERIPH_F},
{"D4", AT91C_PIN_PA(4), 0, PIO_PULLUP, PIO_PERIPH_F},
{"D5", AT91C_PIN_PA(5), 0, PIO_PULLUP, PIO_PERIPH_F},
{"D6", AT91C_PIN_PA(6), 0, PIO_PULLUP, PIO_PERIPH_F},
{"D7", AT91C_PIN_PA(7), 0, PIO_PULLUP, PIO_PERIPH_F},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pio_configure(nand_pins);
pmc_sam9x5_enable_periph_clk(AT91C_ID_HSMC);
/* EBI Configuration Register */
writel((AT91C_EBICFG_DRIVE0_HIGH |
AT91C_EBICFG_PULL0_NONE |
AT91C_EBICFG_DRIVE1_HIGH |
AT91C_EBICFG_PULL1_NONE), SFR_EBICFG + AT91C_BASE_SFR);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91C_SMC_SETUP_NWE(1) |
AT91C_SMC_SETUP_NCS_WR(1) |
AT91C_SMC_SETUP_NRD(1) |
AT91C_SMC_SETUP_NCS_RD(1), (ATMEL_BASE_SMC + SMC_SETUP3));
writel(AT91C_SMC_PULSE_NWE(2) |
AT91C_SMC_PULSE_NCS_WR(3) |
AT91C_SMC_PULSE_NRD(2) |
AT91C_SMC_PULSE_NCS_RD(3), (ATMEL_BASE_SMC + SMC_PULSE3));
writel(AT91C_SMC_CYCLE_NWE(5) |
AT91C_SMC_CYCLE_NRD(5), (ATMEL_BASE_SMC + SMC_CYCLE3));
writel(AT91C_SMC_TIMINGS_TCLR(2) |
AT91C_SMC_TIMINGS_TADL(7) |
AT91C_SMC_TIMINGS_TAR(2) |
AT91C_SMC_TIMINGS_TRR(3) |
AT91C_SMC_TIMINGS_TWB(7) |
AT91C_SMC_TIMINGS_RBNSEL(2) |
AT91C_SMC_TIMINGS_NFSEL, (ATMEL_BASE_SMC + SMC_TIMINGS3));
writel(AT91C_SMC_MODE_READMODE_NRD_CTRL |
AT91C_SMC_MODE_WRITEMODE_NWE_CTRL |
AT91C_SMC_MODE_DBW_8 |
AT91C_SMC_MODE_TDF_CYCLES(1), (ATMEL_BASE_SMC + SMC_MODE3));
}
void nandflash_hw_init(void)
{
/* Configure nand pins */
const struct pio_desc nand_pins[] = {
{"NANDALE", AT91C_PIN_PE(21), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PE(22), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Configure the nand controller pins*/
pio_configure(nand_pins);
writel((1 << AT91C_ID_PIOE), (PMC_PCER + AT91C_BASE_PMC));
/* Enable the clock */
writel(1 << AT91C_ID_SMC, (PMC_PCER + AT91C_BASE_PMC));
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91C_SMC_SETUP_NWE(1)
| AT91C_SMC_SETUP_NCS_WR(1)
| AT91C_SMC_SETUP_NRD(2)
| AT91C_SMC_SETUP_NCS_RD(1),
(ATMEL_BASE_SMC + SMC_SETUP3));
writel(AT91C_SMC_PULSE_NWE(5)
| AT91C_SMC_PULSE_NCS_WR(7)
| AT91C_SMC_PULSE_NRD(5)
| AT91C_SMC_PULSE_NCS_RD(7),
(ATMEL_BASE_SMC + SMC_PULSE3));
writel(AT91C_SMC_CYCLE_NWE(8)
| AT91C_SMC_CYCLE_NRD(9),
(ATMEL_BASE_SMC + SMC_CYCLE3));
writel(AT91C_SMC_TIMINGS_TCLR(3)
| AT91C_SMC_TIMINGS_TADL(10)
| AT91C_SMC_TIMINGS_TAR(3)
| AT91C_SMC_TIMINGS_TRR(4)
| AT91C_SMC_TIMINGS_TWB(5)
| AT91C_SMC_TIMINGS_RBNSEL(3)
| AT91C_SMC_TIMINGS_NFSEL,
(ATMEL_BASE_SMC + SMC_TIMINGS3));
writel(AT91C_SMC_MODE_READMODE_NRD_CTRL
| AT91C_SMC_MODE_WRITEMODE_NWE_CTRL
| AT91C_SMC_MODE_EXNWMODE_DISABLED
| AT91C_SMC_MODE_DBW_8
| AT91C_SMC_MODE_TDF_CYCLES(1),
(ATMEL_BASE_SMC + SMC_MODE3));
}
void nandflash_hw_init(void)
{
const struct pio_desc nand_pins[] = {
{"NANDALE", AT91C_PIN_PE(21), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PE(22), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pmc_enable_periph_clock(AT91C_ID_PIOE);
pio_configure(nand_pins);
pmc_enable_periph_clock(AT91C_ID_SMC);
writel(AT91C_SMC_SETUP_NWE(1)
| AT91C_SMC_SETUP_NCS_WR(1)
| AT91C_SMC_SETUP_NRD(2)
| AT91C_SMC_SETUP_NCS_RD(1),
(ATMEL_BASE_SMC + SMC_SETUP3));
writel(AT91C_SMC_PULSE_NWE(5)
| AT91C_SMC_PULSE_NCS_WR(7)
| AT91C_SMC_PULSE_NRD(5)
| AT91C_SMC_PULSE_NCS_RD(7),
(ATMEL_BASE_SMC + SMC_PULSE3));
writel(AT91C_SMC_CYCLE_NWE(8)
| AT91C_SMC_CYCLE_NRD(9),
(ATMEL_BASE_SMC + SMC_CYCLE3));
writel(AT91C_SMC_TIMINGS_TCLR(3)
| AT91C_SMC_TIMINGS_TADL(10)
| AT91C_SMC_TIMINGS_TAR(3)
| AT91C_SMC_TIMINGS_TRR(4)
| AT91C_SMC_TIMINGS_TWB(5)
| AT91C_SMC_TIMINGS_RBNSEL(3)
| AT91C_SMC_TIMINGS_NFSEL,
(ATMEL_BASE_SMC + SMC_TIMINGS3));
writel(AT91C_SMC_MODE_READMODE_NRD_CTRL
| AT91C_SMC_MODE_WRITEMODE_NWE_CTRL
| AT91C_SMC_MODE_EXNWMODE_DISABLED
| AT91C_SMC_MODE_DBW_8
| AT91C_SMC_MODE_TDF_CYCLES(1),
(ATMEL_BASE_SMC + SMC_MODE3));
}
