/**Function*************************************************************
Synopsis [Read the network from a file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Io_Read( char * pFileName, Io_FileType_t FileType, int fCheck )
{
Abc_Ntk_t * pNtk, * pTemp;
// get the netlist
pNtk = Io_ReadNetlist( pFileName, FileType, fCheck );
if ( pNtk == NULL )
return NULL;
if ( !Abc_NtkIsNetlist(pNtk) )
return pNtk;
// flatten logic hierarchy
assert( Abc_NtkIsNetlist(pNtk) );
if ( Abc_NtkWhiteboxNum(pNtk) > 0 )
{
pNtk = Abc_NtkFlattenLogicHierarchy( pTemp = pNtk );
Abc_NtkDelete( pTemp );
if ( pNtk == NULL )
{
fprintf( stdout, "Flattening logic hierarchy has failed.\n" );
return NULL;
}
}
// convert blackboxes
if ( Abc_NtkBlackboxNum(pNtk) > 0 )
{
printf( "Hierarchy reader converted %d instances of blackboxes.\n", Abc_NtkBlackboxNum(pNtk) );
pNtk = Abc_NtkConvertBlackboxes( pTemp = pNtk );
Abc_NtkDelete( pTemp );
if ( pNtk == NULL )
{
fprintf( stdout, "Converting blackboxes has failed.\n" );
return NULL;
}
}
// consider the case of BLIF-MV
if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV )
{
//Abc_NtkPrintStats( stdout, pNtk, 0 );
// Io_WriteBlifMv( pNtk, "_temp_.mv" );
pNtk = Abc_NtkStrashBlifMv( pTemp = pNtk );
Abc_NtkDelete( pTemp );
if ( pNtk == NULL )
{
fprintf( stdout, "Converting BLIF-MV to AIG has failed.\n" );
return NULL;
}
return pNtk;
}
// convert the netlist into the logic network
pNtk = Abc_NtkToLogic( pTemp = pNtk );
Abc_NtkDelete( pTemp );
if ( pNtk == NULL )
{
fprintf( stdout, "Converting netlist to logic network after reading has failed.\n" );
return NULL;
}
return pNtk;
}
/**Function*************************************************************
Synopsis [Transform the netlist into a logic network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkToLogic( Abc_Ntk_t * pNtk )
{
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObj, * pFanin;
int i, k;
// consider the case of the AIG
if ( Abc_NtkIsStrash(pNtk) )
return Abc_NtkAigToLogicSop( pNtk );
assert( Abc_NtkIsNetlist(pNtk) );
// consider simple case when there is hierarchy
// assert( pNtk->pDesign == NULL );
assert( Abc_NtkWhiteboxNum(pNtk) == 0 );
assert( Abc_NtkBlackboxNum(pNtk) == 0 );
// start the network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, pNtk->ntkFunc );
// duplicate the nodes
Abc_NtkForEachNode( pNtk, pObj, i )
Abc_NtkDupObj(pNtkNew, pObj, 0);
// reconnect the internal nodes in the new network
Abc_NtkForEachNode( pNtk, pObj, i )
Abc_ObjForEachFanin( pObj, pFanin, k )
Abc_ObjAddFanin( pObj->pCopy, Abc_ObjFanin0(pFanin)->pCopy );
// collect the CO nodes
Abc_NtkFinalize( pNtk, pNtkNew );
// fix the problem with CO pointing directly to CIs
Abc_NtkLogicMakeSimpleCos( pNtkNew, 0 );
// duplicate EXDC
if ( pNtk->pExdc )
pNtkNew->pExdc = Abc_NtkToLogic( pNtk->pExdc );
if ( !Abc_NtkCheck( pNtkNew ) )
fprintf( stdout, "Abc_NtkToLogic(): Network check has failed.\n" );
return pNtkNew;
}
/**Function*************************************************************
Synopsis [Write the network into a BLIF file with the given name.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteBlifMv( Abc_Ntk_t * pNtk, char * FileName )
{
FILE * pFile;
Abc_Ntk_t * pNtkTemp;
int i;
assert( Abc_NtkIsNetlist(pNtk) );
assert( Abc_NtkHasBlifMv(pNtk) );
// start writing the file
pFile = fopen( FileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteBlifMv(): Cannot open the output file.\n" );
return;
}
fprintf( pFile, "# Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
// write the master network
Io_NtkWriteBlifMv( pFile, pNtk );
// write the remaining networks
if ( pNtk->pDesign )
{
Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pNtkTemp, i )
{
if ( pNtkTemp == pNtk )
continue;
fprintf( pFile, "\n\n" );
Io_NtkWriteBlifMv( pFile, pNtkTemp );
}
}
/**Function*************************************************************
Synopsis [Write the network into a BLIF file with the given name.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches, int fBb2Wb, int fSeq )
{
FILE * pFile;
Abc_Ntk_t * pNtkTemp;
int i;
assert( Abc_NtkIsNetlist(pNtk) );
// start writing the file
pFile = fopen( FileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteBlif(): Cannot open the output file.\n" );
return;
}
fprintf( pFile, "# Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
// write the master network
Io_NtkWrite( pFile, pNtk, fWriteLatches, fBb2Wb, fSeq );
// make sure there is no logic hierarchy
assert( Abc_NtkWhiteboxNum(pNtk) == 0 );
// write the hierarchy if present
if ( Abc_NtkBlackboxNum(pNtk) > 0 )
{
Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pNtkTemp, i )
{
if ( pNtkTemp == pNtk )
continue;
fprintf( pFile, "\n\n" );
Io_NtkWrite( pFile, pNtkTemp, fWriteLatches, fBb2Wb, fSeq );
}
}
/**Function*************************************************************
Synopsis [Prints statistics about latches.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkPrintLatch( FILE * pFile, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pLatch, * pFanin;
int i, Counter0, Counter1, Counter2;
int InitNums[4], Init;
assert( !Abc_NtkIsNetlist(pNtk) );
if ( Abc_NtkLatchNum(pNtk) == 0 )
{
fprintf( pFile, "The network is combinational.\n" );
return;
}
for ( i = 0; i < 4; i++ )
InitNums[i] = 0;
Counter0 = Counter1 = Counter2 = 0;
Abc_NtkForEachLatch( pNtk, pLatch, i )
{
Init = Abc_LatchInit( pLatch );
assert( Init < 4 );
InitNums[Init]++;
pFanin = Abc_ObjFanin0(Abc_ObjFanin0(pLatch));
if ( Abc_NtkIsLogic(pNtk) )
{
if ( !Abc_NodeIsConst(pFanin) )
continue;
}
else if ( Abc_NtkIsStrash(pNtk) )
{
if ( !Abc_AigNodeIsConst(pFanin) )
continue;
}
else
assert( 0 );
// the latch input is a constant node
Counter0++;
if ( Abc_LatchIsInitDc(pLatch) )
{
Counter1++;
continue;
}
// count the number of cases when the constant is equal to the initial value
if ( Abc_NtkIsStrash(pNtk) )
{
if ( Abc_LatchIsInit1(pLatch) == !Abc_ObjFaninC0(pLatch) )
Counter2++;
}
else
{
if ( Abc_LatchIsInit1(pLatch) == Abc_NodeIsConst1(pLatch) )
Counter2++;
}
}
/**Function*************************************************************
Synopsis [Returns the mapping from the fraig nodes point into the nodes of the netlist.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
stmm_table * Abc_NtkDressDeriveMapping( Abc_Ntk_t * pNtk )
{
stmm_table * tResult;
Abc_Obj_t * pNode, * pNodeMap, * pNodeFraig;
int i;
assert( Abc_NtkIsNetlist(pNtk) );
tResult = stmm_init_table(stmm_ptrcmp,stmm_ptrhash);
Abc_NtkForEachNode( pNtk, pNode, i )
{
// get the fraiged node
pNodeFraig = Abc_ObjRegular(pNode->pCopy);
// if this node is already mapped, skip
if ( stmm_is_member( tResult, (char *)pNodeFraig ) )
continue;
// get the mapping of this node
pNodeMap = Abc_ObjNotCond( pNode, Abc_ObjIsComplement(pNode->pCopy) );
// add the mapping
stmm_insert( tResult, (char *)pNodeFraig, (char *)pNodeMap );
}
/**Function*************************************************************
Synopsis [Prepares the IVY package.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Ivy_Man_t * Abc_NtkIvyBefore( Abc_Ntk_t * pNtk, int fSeq, int fUseDc )
{
Ivy_Man_t * pMan;
int fCleanup = 1;
//timeRetime = clock();
assert( !Abc_NtkIsNetlist(pNtk) );
if ( Abc_NtkIsBddLogic(pNtk) )
{
if ( !Abc_NtkBddToSop(pNtk, 0) )
{
printf( "Abc_NtkIvyBefore(): Converting to SOPs has failed.\n" );
return NULL;
}
}
if ( fSeq && Abc_NtkCountSelfFeedLatches(pNtk) )
{
printf( "Warning: The network has %d self-feeding latches.\n", Abc_NtkCountSelfFeedLatches(pNtk) );
// return NULL;
}
// print warning about choice nodes
if ( Abc_NtkGetChoiceNum( pNtk ) )
printf( "Warning: The choice nodes in the initial AIG are removed by strashing.\n" );
// convert to the AIG manager
pMan = Abc_NtkToIvy( pNtk );
if ( !Ivy_ManCheck( pMan ) )
{
printf( "AIG check has failed.\n" );
Ivy_ManStop( pMan );
return NULL;
}
// Ivy_ManPrintStats( pMan );
if ( fSeq )
{
int nLatches = Abc_NtkLatchNum(pNtk);
Vec_Int_t * vInit = Abc_NtkCollectLatchValuesIvy( pNtk, fUseDc );
Ivy_ManMakeSeq( pMan, nLatches, vInit->pArray );
Vec_IntFree( vInit );
// Ivy_ManPrintStats( pMan );
}
//timeRetime = clock() - timeRetime;
return pMan;
}
/**Function*************************************************************
Synopsis [Write verilog.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName )
{
Abc_Ntk_t * pNetlist;
FILE * pFile;
int i;
// can only write nodes represented using local AIGs
if ( !Abc_NtkIsAigNetlist(pNtk) && !Abc_NtkIsMappedNetlist(pNtk) )
{
printf( "Io_WriteVerilog(): Can produce Verilog for mapped or AIG netlists only.\n" );
return;
}
// start the output stream
pFile = fopen( pFileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteVerilog(): Cannot open the output file \"%s\".\n", pFileName );
return;
}
// write the equations for the network
fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
fprintf( pFile, "\n" );
// write modules
if ( pNtk->pDesign )
{
// write the network first
Io_WriteVerilogInt( pFile, pNtk );
// write other things
Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pNetlist, i )
{
assert( Abc_NtkIsNetlist(pNetlist) );
if ( pNetlist == pNtk )
continue;
fprintf( pFile, "\n" );
Io_WriteVerilogInt( pFile, pNetlist );
}
}
/**Function*************************************************************
Synopsis [Strashes the BLIF-MV netlist.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkStrashBlifMv( Abc_Ntk_t * pNtk )
{
int fUsePositional = 0;
Vec_Ptr_t * vNodes;
Abc_Obj_t ** pBits;
Abc_Obj_t ** pValues;
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObj, * pTemp, * pBit, * pNet;
int i, k, v, nValues, nValuesMax, nBits;
int nCount1, nCount2;
assert( Abc_NtkIsNetlist(pNtk) );
assert( Abc_NtkHasBlifMv(pNtk) );
assert( Abc_NtkWhiteboxNum(pNtk) == 0 );
assert( Abc_NtkBlackboxNum(pNtk) == 0 );
// get the largest number of values
nValuesMax = 2;
Abc_NtkForEachNet( pNtk, pObj, i )
{
nValues = Abc_ObjMvVarNum(pObj);
if ( nValuesMax < nValues )
nValuesMax = nValues;
}
/**Function*************************************************************
Synopsis [Performs minimum-register retiming.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t *
Abc_FlowRetime_MinReg( Abc_Ntk_t * pNtk, int fVerbose,
int fComputeInitState, int fGuaranteeInitState, int fBlockConst,
int fForwardOnly, int fBackwardOnly, int nMaxIters,
int maxDelay, int fFastButConservative ) {
int i;
Abc_Obj_t *pObj, *pNext;
InitConstraint_t *pData;
// create manager
pManMR = ALLOC( MinRegMan_t, 1 );
pManMR->pNtk = pNtk;
pManMR->fVerbose = fVerbose;
pManMR->fComputeInitState = fComputeInitState;
pManMR->fGuaranteeInitState = fGuaranteeInitState;
pManMR->fBlockConst = fBlockConst;
pManMR->fForwardOnly = fForwardOnly;
pManMR->fBackwardOnly = fBackwardOnly;
pManMR->nMaxIters = nMaxIters;
pManMR->maxDelay = maxDelay;
pManMR->fComputeInitState = fComputeInitState;
pManMR->fConservTimingOnly = fFastButConservative;
pManMR->vNodes = Vec_PtrAlloc(100);
pManMR->vInitConstraints = Vec_PtrAlloc(2);
pManMR->pInitNtk = NULL;
pManMR->pInitToOrig = NULL;
pManMR->sizeInitToOrig = 0;
vprintf("Flow-based minimum-register retiming...\n");
if (!Abc_NtkHasOnlyLatchBoxes(pNtk)) {
printf("\tERROR: Can not retime with black/white boxes\n");
return pNtk;
}
if (maxDelay) {
vprintf("\tmax delay constraint = %d\n", maxDelay);
if (maxDelay < (i = Abc_NtkLevel(pNtk))) {
printf("ERROR: max delay constraint (%d) must be > current max delay (%d)\n", maxDelay, i);
return pNtk;
}
}
// print info about type of network
vprintf("\tnetlist type = ");
if (Abc_NtkIsNetlist( pNtk )) { vprintf("netlist/"); }
else if (Abc_NtkIsLogic( pNtk )) { vprintf("logic/"); }
else if (Abc_NtkIsStrash( pNtk )) { vprintf("strash/"); }
else { vprintf("***unknown***/"); }
if (Abc_NtkHasSop( pNtk )) { vprintf("sop\n"); }
else if (Abc_NtkHasBdd( pNtk )) { vprintf("bdd\n"); }
else if (Abc_NtkHasAig( pNtk )) { vprintf("aig\n"); }
else if (Abc_NtkHasMapping( pNtk )) { vprintf("mapped\n"); }
else { vprintf("***unknown***\n"); }
vprintf("\tinitial reg count = %d\n", Abc_NtkLatchNum(pNtk));
vprintf("\tinitial levels = %d\n", Abc_NtkLevel(pNtk));
// remove bubbles from latch boxes
if (pManMR->fVerbose) Abc_FlowRetime_PrintInitStateInfo(pNtk);
vprintf("\tpushing bubbles out of latch boxes\n");
Abc_NtkForEachLatch( pNtk, pObj, i )
Abc_FlowRetime_RemoveLatchBubbles(pObj);
if (pManMR->fVerbose) Abc_FlowRetime_PrintInitStateInfo(pNtk);
// check for box inputs/outputs
Abc_NtkForEachLatch( pNtk, pObj, i ) {
assert(Abc_ObjFaninNum(pObj) == 1);
assert(Abc_ObjFanoutNum(pObj) == 1);
assert(!Abc_ObjFaninC0(pObj));
pNext = Abc_ObjFanin0(pObj);
assert(Abc_ObjIsBi(pNext));
assert(Abc_ObjFaninNum(pNext) <= 1);
if(Abc_ObjFaninNum(pNext) == 0) // every Bi should have a fanin
Abc_FlowRetime_AddDummyFanin( pNext );
pNext = Abc_ObjFanout0(pObj);
assert(Abc_ObjIsBo(pNext));
assert(Abc_ObjFaninNum(pNext) == 1);
assert(!Abc_ObjFaninC0(pNext));
}
/**Function*************************************************************
Synopsis [Write the network into file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName )
{
Abc_Ntk_t * pNtkTemp, * pNtkResult, * pNtkBase = NULL;
// check if the current network is available
if ( pNtk == NULL )
{
fprintf( stdout, "Empty network.\n" );
return;
}
// read the base network
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIF )
pNtkBase = Io_ReadBlifMv( pBaseName, 0, 1 );
else if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIFMV )
pNtkBase = Io_ReadBlifMv( pBaseName, 1, 1 );
else if ( Io_ReadFileType(pBaseName) == IO_FILE_VERILOG )
pNtkBase = Io_ReadVerilog( pBaseName, 1 );
else
fprintf( stderr, "Unknown input file format.\n" );
if ( pNtkBase == NULL )
return;
// flatten logic hierarchy if present
if ( Abc_NtkWhiteboxNum(pNtkBase) > 0 )
{
pNtkBase = Abc_NtkFlattenLogicHierarchy( pNtkTemp = pNtkBase );
if ( pNtkBase == NULL )
return;
Abc_NtkDelete( pNtkTemp );
}
// reintroduce the boxes into the netlist
if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIFMV )
{
if ( Abc_NtkBlackboxNum(pNtkBase) > 0 )
{
printf( "Hierarchy writer does not support BLIF-MV with blackboxes.\n" );
Abc_NtkDelete( pNtkBase );
return;
}
// convert the current network to BLIF-MV
assert( !Abc_NtkIsNetlist(pNtk) );
pNtkResult = Abc_NtkToNetlist( pNtk );
if ( !Abc_NtkConvertToBlifMv( pNtkResult ) )
return;
// reintroduce the network
pNtkResult = Abc_NtkInsertBlifMv( pNtkBase, pNtkTemp = pNtkResult );
Abc_NtkDelete( pNtkTemp );
}
else if ( Abc_NtkBlackboxNum(pNtkBase) > 0 )
{
// derive the netlist
pNtkResult = Abc_NtkToNetlist( pNtk );
pNtkResult = Abc_NtkInsertNewLogic( pNtkBase, pNtkTemp = pNtkResult );
Abc_NtkDelete( pNtkTemp );
if ( pNtkResult )
printf( "Hierarchy writer reintroduced %d instances of blackboxes.\n", Abc_NtkBlackboxNum(pNtkBase) );
}
else
{
printf( "Warning: The output network does not contain blackboxes.\n" );
pNtkResult = Abc_NtkToNetlist( pNtk );
}
Abc_NtkDelete( pNtkBase );
if ( pNtkResult == NULL )
return;
// write the resulting network
if ( Io_ReadFileType(pFileName) == IO_FILE_BLIF )
{
if ( !Abc_NtkHasSop(pNtkResult) && !Abc_NtkHasMapping(pNtkResult) )
Abc_NtkToSop( pNtkResult, 0 );
Io_WriteBlif( pNtkResult, pFileName, 1 );
}
else if ( Io_ReadFileType(pFileName) == IO_FILE_VERILOG )
{
if ( !Abc_NtkHasAig(pNtkResult) && !Abc_NtkHasMapping(pNtkResult) )
Abc_NtkToAig( pNtkResult );
Io_WriteVerilog( pNtkResult, pFileName );
}
else if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV )
{
Io_WriteBlifMv( pNtkResult, pFileName );
}
else
fprintf( stderr, "Unknown output file format.\n" );
Abc_NtkDelete( pNtkResult );
}
/**Function*************************************************************
Synopsis [Transfers names from one netlist to the other.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkDress( Abc_Ntk_t * pNtkLogic, char * pFileName, int fVerbose )
{
Abc_Ntk_t * pNtkOrig, * pNtkLogicOrig;
Abc_Ntk_t * pMiter, * pMiterFraig;
stmm_table * tMapping;
assert( Abc_NtkIsLogic(pNtkLogic) );
// get the original netlist
pNtkOrig = Io_ReadNetlist( pFileName, Io_ReadFileType(pFileName), 1 );
if ( pNtkOrig == NULL )
return;
assert( Abc_NtkIsNetlist(pNtkOrig) );
Abc_NtkCleanCopy(pNtkLogic);
Abc_NtkCleanCopy(pNtkOrig);
// convert it into the logic network
pNtkLogicOrig = Abc_NtkToLogic( pNtkOrig );
// check that the networks have the same PIs/POs/latches
if ( !Abc_NtkCompareSignals( pNtkLogic, pNtkLogicOrig, 1, 1 ) )
{
Abc_NtkDelete( pNtkOrig );
Abc_NtkDelete( pNtkLogicOrig );
return;
}
// convert the current logic network into an AIG
pMiter = Abc_NtkStrash( pNtkLogic, 1, 0, 0 );
// convert it into the AIG and make the netlist point to the AIG
Abc_NtkAppend( pMiter, pNtkLogicOrig, 1 );
Abc_NtkTransferCopy( pNtkOrig );
Abc_NtkDelete( pNtkLogicOrig );
if ( fVerbose )
{
printf( "After mitering:\n" );
printf( "Logic: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkLogic), Abc_NtkCountCopy(pNtkLogic) );
printf( "Orig: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkOrig), Abc_NtkCountCopy(pNtkOrig) );
}
// fraig the miter (miter nodes point to the fraiged miter)
pMiterFraig = Abc_NtkIvyFraig( pMiter, 100, 1, 0, 1, 0 );
// make netlists point to the fraiged miter
Abc_NtkTransferCopy( pNtkLogic );
Abc_NtkTransferCopy( pNtkOrig );
Abc_NtkDelete( pMiter );
if ( fVerbose )
{
printf( "After fraiging:\n" );
printf( "Logic: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkLogic), Abc_NtkCountCopy(pNtkLogic) );
printf( "Orig: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkOrig), Abc_NtkCountCopy(pNtkOrig) );
}
// derive mapping from the fraiged nodes into their prototype nodes in the original netlist
tMapping = Abc_NtkDressDeriveMapping( pNtkOrig );
// transfer the names to the new netlist
Abc_NtkDressTransferNames( pNtkLogic, tMapping, fVerbose );
// clean up
stmm_free_table( tMapping );
Abc_NtkDelete( pMiterFraig );
Abc_NtkDelete( pNtkOrig );
}
/**Function*************************************************************
Synopsis [Print the vital stats of the network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
{
int Num;
// if ( Abc_NtkIsStrash(pNtk) )
// Abc_AigCountNext( pNtk->pManFunc );
fprintf( pFile, "%-13s:", pNtk->pName );
if ( Abc_NtkAssertNum(pNtk) )
fprintf( pFile, " i/o/a = %4d/%4d/%4d", Abc_NtkPiNum(pNtk), Abc_NtkPoNum(pNtk), Abc_NtkAssertNum(pNtk) );
else
fprintf( pFile, " i/o = %4d/%4d", Abc_NtkPiNum(pNtk), Abc_NtkPoNum(pNtk) );
fprintf( pFile, " lat = %4d", Abc_NtkLatchNum(pNtk) );
if ( Abc_NtkIsNetlist(pNtk) )
{
fprintf( pFile, " net = %5d", Abc_NtkNetNum(pNtk) );
fprintf( pFile, " nd = %5d", Abc_NtkNodeNum(pNtk) );
fprintf( pFile, " wbox = %3d", Abc_NtkWhiteboxNum(pNtk) );
fprintf( pFile, " bbox = %3d", Abc_NtkBlackboxNum(pNtk) );
}
else if ( Abc_NtkIsStrash(pNtk) )
{
fprintf( pFile, " and = %5d", Abc_NtkNodeNum(pNtk) );
if ( Num = Abc_NtkGetChoiceNum(pNtk) )
fprintf( pFile, " (choice = %d)", Num );
if ( Num = Abc_NtkGetExorNum(pNtk) )
fprintf( pFile, " (exor = %d)", Num );
// if ( Num2 = Abc_NtkGetMuxNum(pNtk) )
// fprintf( pFile, " (mux = %d)", Num2-Num );
// if ( Num2 )
// fprintf( pFile, " (other = %d)", Abc_NtkNodeNum(pNtk)-3*Num2 );
}
else
{
fprintf( pFile, " nd = %5d", Abc_NtkNodeNum(pNtk) );
fprintf( pFile, " net = %5d", Abc_NtkGetTotalFanins(pNtk) );
}
if ( Abc_NtkIsStrash(pNtk) || Abc_NtkIsNetlist(pNtk) )
{
}
else if ( Abc_NtkHasSop(pNtk) )
{
fprintf( pFile, " cube = %5d", Abc_NtkGetCubeNum(pNtk) );
// fprintf( pFile, " lit(sop) = %5d", Abc_NtkGetLitNum(pNtk) );
if ( fFactored )
fprintf( pFile, " lit(fac) = %5d", Abc_NtkGetLitFactNum(pNtk) );
}
else if ( Abc_NtkHasAig(pNtk) )
fprintf( pFile, " aig = %5d", Abc_NtkGetAigNodeNum(pNtk) );
else if ( Abc_NtkHasBdd(pNtk) )
fprintf( pFile, " bdd = %5d", Abc_NtkGetBddNodeNum(pNtk) );
else if ( Abc_NtkHasMapping(pNtk) )
{
fprintf( pFile, " area = %5.2f", Abc_NtkGetMappedArea(pNtk) );
fprintf( pFile, " delay = %5.2f", Abc_NtkDelayTrace(pNtk) );
}
else if ( !Abc_NtkHasBlackbox(pNtk) )
{
assert( 0 );
}
if ( Abc_NtkIsStrash(pNtk) )
fprintf( pFile, " lev = %3d", Abc_AigLevel(pNtk) );
else
fprintf( pFile, " lev = %3d", Abc_NtkLevel(pNtk) );
fprintf( pFile, "\n" );
// Abc_NtkCrossCut( pNtk );
// print the statistic into a file
/*
{
FILE * pTable;
pTable = fopen( "iscas/seqmap__stats.txt", "a+" );
fprintf( pTable, "%s ", pNtk->pName );
fprintf( pTable, "%d ", Abc_NtkPiNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkPoNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkLatchNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkLevel(pNtk) );
fprintf( pTable, "\n" );
fclose( pTable );
}
*/
/*
// print the statistic into a file
{
FILE * pTable;
pTable = fopen( "stats.txt", "a+" );
fprintf( pTable, "%s ", pNtk->pSpec );
fprintf( pTable, "%.0f ", Abc_NtkGetMappedArea(pNtk) );
fprintf( pTable, "%.2f ", Abc_NtkDelayTrace(pNtk) );
fprintf( pTable, "\n" );
fclose( pTable );
}
*/
/*
// print the statistic into a file
{
FILE * pTable;
pTable = fopen( "x/stats_new.txt", "a+" );
fprintf( pTable, "%s ", pNtk->pName );
// fprintf( pTable, "%d ", Abc_NtkPiNum(pNtk) );
// fprintf( pTable, "%d ", Abc_NtkPoNum(pNtk) );
// fprintf( pTable, "%d ", Abc_NtkLevel(pNtk) );
// fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
// fprintf( pTable, "%d ", Abc_NtkGetTotalFanins(pNtk) );
// fprintf( pTable, "%d ", Abc_NtkLatchNum(pNtk) );
// fprintf( pTable, "%.2f ", (float)(s_MappingMem)/(float)(1<<20) );
fprintf( pTable, "%.2f", (float)(s_MappingTime)/(float)(CLOCKS_PER_SEC) );
// fprintf( pTable, "%.2f", (float)(s_ResynTime)/(float)(CLOCKS_PER_SEC) );
fprintf( pTable, "\n" );
fclose( pTable );
s_ResynTime = 0;
}
*/
/*
// print the statistic into a file
{
static int Counter = 0;
extern int timeRetime;
FILE * pTable;
Counter++;
pTable = fopen( "a/ret__stats.txt", "a+" );
fprintf( pTable, "%s ", pNtk->pName );
fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkLatchNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkLevel(pNtk) );
fprintf( pTable, "%.2f ", (float)(timeRetime)/(float)(CLOCKS_PER_SEC) );
if ( Counter % 4 == 0 )
fprintf( pTable, "\n" );
fclose( pTable );
}
*/
/*
// print the statistic into a file
{
static int Counter = 0;
extern int timeRetime;
FILE * pTable;
Counter++;
pTable = fopen( "d/stats.txt", "a+" );
fprintf( pTable, "%s ", pNtk->pName );
// fprintf( pTable, "%d ", Abc_NtkPiNum(pNtk) );
// fprintf( pTable, "%d ", Abc_NtkPoNum(pNtk) );
// fprintf( pTable, "%d ", Abc_NtkLatchNum(pNtk) );
fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
fprintf( pTable, "%.2f ", (float)(timeRetime)/(float)(CLOCKS_PER_SEC) );
fprintf( pTable, "\n" );
fclose( pTable );
}
*/
/*
s_TotalNodes += Abc_NtkNodeNum(pNtk);
printf( "Total nodes = %6d %6.2f Mb Changes = %6d.\n",
s_TotalNodes, s_TotalNodes * 20.0 / (1<<20), s_TotalChanges );
*/
}
/**Function*************************************************************
Synopsis [Checks the integrity of the network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkDoCheck( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj, * pNet, * pNode;
int i;
// check network types
if ( !Abc_NtkIsNetlist(pNtk) && !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsStrash(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown network type.\n" );
return 0;
}
if ( !Abc_NtkHasSop(pNtk) && !Abc_NtkHasBdd(pNtk) && !Abc_NtkHasAig(pNtk) && !Abc_NtkHasMapping(pNtk) && !Abc_NtkHasBlifMv(pNtk) && !Abc_NtkHasBlackbox(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown functionality type.\n" );
return 0;
}
if ( Abc_NtkHasMapping(pNtk) )
{
if ( pNtk->pManFunc != Abc_FrameReadLibGen() )
{
fprintf( stdout, "NetworkCheck: The library of the mapped network is not the global library.\n" );
return 0;
}
}
if ( Abc_NtkHasOnlyLatchBoxes(pNtk) )
{
// check CI/CO numbers
if ( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCiNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of CIs does not match number of PIs and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
if ( Abc_NtkPoNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCoNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of COs does not match number of POs, asserts, and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
}
// check the names
if ( !Abc_NtkCheckNames( pNtk ) )
return 0;
// check PIs and POs
Abc_NtkCleanCopy( pNtk );
if ( !Abc_NtkCheckPis( pNtk ) )
return 0;
if ( !Abc_NtkCheckPos( pNtk ) )
return 0;
if ( Abc_NtkHasBlackbox(pNtk) )
return 1;
// check the connectivity of objects
Abc_NtkForEachObj( pNtk, pObj, i )
if ( !Abc_NtkCheckObj( pNtk, pObj ) )
return 0;
// if it is a netlist change nets and latches
if ( Abc_NtkIsNetlist(pNtk) )
{
if ( Abc_NtkNetNum(pNtk) == 0 )
fprintf( stdout, "NetworkCheck: Warning! Netlist has no nets.\n" );
// check the nets
Abc_NtkForEachNet( pNtk, pNet, i )
if ( !Abc_NtkCheckNet( pNtk, pNet ) )
return 0;
}
else
{
if ( Abc_NtkNetNum(pNtk) != 0 )
static inline char * Abc_ObjNameNet( Abc_Obj_t * pObj ) { return (Abc_ObjIsNode(pObj) && Abc_NtkIsNetlist(pObj->pNtk)) ? Abc_ObjName(Abc_ObjFanout0(pObj)) : Abc_ObjName(pObj); }
