static int mtk_soc_pcm_dl2_close(struct snd_pcm_substream *substream)
{
pr_warn("%s\n", __func__);
if (mPrepareDone == true) {
/* stop DAC output */
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false);
if (GetI2SDacEnable() == false)
SetI2SDacEnable(false);
RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL2, substream);
EnableAfe(false);
mPrepareDone = false;
}
if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM)
AudDrv_Emi_Clk_Off();
AfeControlSramLock();
ClearSramState(mPlaybackSramState);
mPlaybackSramState = GetSramState();
AfeControlSramUnLock();
AudDrv_Clk_Off();
return 0;
}
static int mtk_pcm_i2s0_open(struct snd_pcm_substream *substream)
{
int ret = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
AfeControlSramLock();
if (GetSramState() == SRAM_STATE_FREE)
{
mtk_i2s0_hardware.buffer_bytes_max = GetPLaybackSramFullSize();
mPlaybackSramState = SRAM_STATE_PLAYBACKFULL;
SetSramState(mPlaybackSramState);
}
else
{
mtk_i2s0_hardware.buffer_bytes_max = GetPLaybackSramPartial();
mPlaybackSramState = SRAM_STATE_PLAYBACKPARTIAL;
SetSramState(mPlaybackSramState);
}
AfeControlSramUnLock();
runtime->hw = mtk_i2s0_hardware;
printk("mtk_pcm_i2s0_open\n");
AudDrv_Clk_On();
memcpy((void *)(&(runtime->hw)), (void *)&mtk_i2s0_hardware , sizeof(struct snd_pcm_hardware));
pI2s0MemControl = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_DL1);
ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_sample_rates);
ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0)
{
printk("snd_pcm_hw_constraint_integer failed\n");
}
//print for hw pcm information
printk("mtk_pcm_i2s0_open runtime rate = %d channels = %d substream->pcm->device = %d\n",
runtime->rate, runtime->channels, substream->pcm->device);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
{
printk("SNDRV_PCM_STREAM_PLAYBACK mtkalsa_i2s0_playback_constraints\n");
}
else
{
}
if (ret < 0)
{
printk("mtk_pcm_i2s0_close\n");
mtk_pcm_i2s0_close(substream);
return ret;
}
printk("mtk_pcm_i2s0_open return\n");
AudDrv_Clk_Off();
return 0;
}
static int mtk_pcm_dl1_open(struct snd_pcm_substream *substream)
{
int ret = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
PRINTK_AUDDRV("mtk_pcm_dl1_open\n");
AfeControlSramLock();
if (GetSramState() == SRAM_STATE_FREE)
{
mtk_pcm_dl1_hardware.buffer_bytes_max = GetPLaybackSramFullSize();
mPlaybackSramState = SRAM_STATE_PLAYBACKFULL;
SetSramState(mPlaybackSramState);
}
else
{
mtk_pcm_dl1_hardware.buffer_bytes_max = GetPLaybackDramSize();
mPlaybackSramState = SRAM_STATE_PLAYBACKDRAM;
}
AfeControlSramUnLock();
if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM)
{
AudDrv_Emi_Clk_On();
}
printk("mtk_pcm_dl1_hardware.buffer_bytes_max = %zu mPlaybackSramState = %d\n", mtk_pcm_dl1_hardware.buffer_bytes_max, mPlaybackSramState);
runtime->hw = mtk_pcm_dl1_hardware;
AudDrv_ANA_Clk_On();
AudDrv_Clk_On();
memcpy((void *)(&(runtime->hw)), (void *)&mtk_pcm_dl1_hardware , sizeof(struct snd_pcm_hardware));
pMemControl = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_DL1);
ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_sample_rates);
if (ret < 0)
{
printk("snd_pcm_hw_constraint_integer failed\n");
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
{
printk("SNDRV_PCM_STREAM_PLAYBACK mtkalsa_dl1playback_constraints\n");
}
else
{
printk("SNDRV_PCM_STREAM_CAPTURE mtkalsa_dl1playback_constraints\n");
}
if (ret < 0)
{
printk("ret < 0 mtk_soc_pcm_dl1_close\n");
mtk_soc_pcm_dl1_close(substream);
return ret;
}
//PRINTK_AUDDRV("mtk_pcm_dl1_open return\n");
return 0;
}
static int mtk_pcm_i2s0_close(struct snd_pcm_substream *substream)
{
printk("%s \n", __func__);
AfeControlSramLock();
ClearSramState(mPlaybackSramState);
mPlaybackSramState = GetSramState();
AfeControlSramUnLock();
return 0;
}
static int mtk_capture_pcm_open(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
int ret = 0;
AudDrv_Clk_On();
AudDrv_ADC_Clk_On();
VUL_Control_context = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_VUL);
// can allocate sram_dbg
AfeControlSramLock();
if (GetSramState() == SRAM_STATE_FREE )
{
printk("mtk_capture_pcm_open use sram \n");
mtk_capture_hardware.buffer_bytes_max = GetCaptureSramSize();
SetSramState(SRAM_STATE_CAPTURE);
mCaptureUseSram = true;
}
else
{
printk("mtk_capture_pcm_open use dram \n");
mtk_capture_hardware.buffer_bytes_max = UL1_MAX_BUFFER_SIZE;
}
AfeControlSramUnLock();
runtime->hw = mtk_capture_hardware;
memcpy((void *)(&(runtime->hw)), (void *)&mtk_capture_hardware , sizeof(struct snd_pcm_hardware));
ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
&constraints_sample_rates);
ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0)
{
printk("snd_pcm_hw_constraint_integer failed\n");
}
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
{
}
else
{
}
if (ret < 0)
{
printk("mtk_capture_pcm_close\n");
mtk_capture_pcm_close(substream);
return ret;
}
if(mCaptureUseSram == false)
{
AudDrv_Emi_Clk_On();
}
printk("mtk_capture_pcm_open return\n");
return 0;
}
static int mtk_Dl1Bt_close(struct snd_pcm_substream *substream)
{
PRINTK_AUDDRV("%s\n", __func__);
AfeControlSramLock();
ClearSramState(mPlaybackSramState);
mPlaybackSramState = GetSramState();
AfeControlSramUnLock();
AudDrv_Clk_Off();
return 0;
}
static int mtk_pcm_I2S0dl1_close(struct snd_pcm_substream *substream)
{
struct snd_pcm_runtime *runtime = substream->runtime;
printk("%s \n", __func__);
if (mPrepareDone == true)
{
// stop DAC output
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false);
if (GetI2SDacEnable() == false)
{
SetI2SDacEnable(false);
}
// stop I2S output
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false);
if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false)
{
Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1);
//Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1);//K2 TODO: fix fm playback then mp3, i2s_con is misconfigured...
}
RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream);
EnableAfe(false);
if (mI2S0dl1_hdoutput_control == true)
{
printk("%s mI2S0dl1_hdoutput_control == %d \n", __func__, mI2S0dl1_hdoutput_control);
EnableI2SDivPower(AUDIO_APLL12_DIV2, false);
EnableI2SDivPower(AUDIO_APLL12_DIV4, false); //Todo do we need open I2S3?
EnableApll(runtime->rate, false);
EnableApllTuner(runtime->rate, false);
}
mPrepareDone = false;
}
if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM)
{
AudDrv_Emi_Clk_Off();
}
AfeControlSramLock();
ClearSramState(mPlaybackSramState);
mPlaybackSramState = GetSramState();
AfeControlSramUnLock();
AudDrv_Clk_Off();
return 0;
}
static int mtk_pcm_fmtx_close(struct snd_pcm_substream *substream)
{
PRINTK_AUD_FMTX("%s \n", __func__);
// mtk_wcn_cmb_stub_audio_ctrl((CMB_STUB_AIF_X)CMB_STUB_AIF_0);
if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM)
{
AudDrv_Emi_Clk_Off();
}
AfeControlSramLock();
ClearSramState(mPlaybackSramState);
mPlaybackSramState = GetSramState();
AfeControlSramUnLock();
AudDrv_Clk_Off();
return 0;
}
static int mtk_pcm_I2S0dl1_close(struct snd_pcm_substream *substream)
{
printk("%s \n", __func__);
if (mPrepareDone == true)
{
// stop DAC output
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false);
if (GetI2SDacEnable() == false)
{
SetI2SDacEnable(false);
}
// stop I2S output
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false);
if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false)
{
Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1);
//Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1);//K2 TODO: fix fm playback then mp3, i2s_con is misconfigured...
}
RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream);
EnableAfe(false);
mPrepareDone = false;
}
if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM)
{
AudDrv_Emi_Clk_Off();
}
AfeControlSramLock();
ClearSramState(mPlaybackSramState);
mPlaybackSramState = GetSramState();
AfeControlSramUnLock();
AudDrv_Clk_Off();
return 0;
}
static int mtk_pcm_I2S0dl1_close(struct snd_pcm_substream *substream)
{
pr_debug("%s \n", __func__);
if (mPrepareDone == true)
{
//Flyme { [email protected] Fix low jitter mode issue that sound will be abnormal when the MediaService reboot
if (mi2s0_sidegen_control) {
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false);
if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false)
{
if (mI2S0dl1_hdoutput_control == true)
{
Afe_Set_Reg(AFE_I2S_CON3, 0, 1 << 12); //Clear Low jitter mode setting
}
Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1);
Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1);
SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O00);
SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O01);
EnableAfe(false);
}
AudDrv_Clk_Off();
mi2s0_sidegen_control = 0;
}
if (mI2S0dl1_hdoutput_control) {
// set APLL clock setting
EnableApll1(false);
EnableApll2(false);
EnableI2SDivPower(AUDIO_APLL1_DIV0, false);
EnableI2SDivPower(AUDIO_APLL2_DIV0, false);
AudDrv_APLL1Tuner_Clk_Off();
AudDrv_APLL2Tuner_Clk_Off();
mI2S0dl1_hdoutput_control = false;
}
// }
// stop DAC output
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false);
if (GetI2SDacEnable() == false)
{
SetI2SDacEnable(false);
}
// stop I2S output
SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false);
if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false)
{
Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1);
Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1);
}
RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1,substream);
EnableAfe(false);
mPrepareDone = false;
}
if(mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM)
{
AudDrv_Emi_Clk_Off();
}
AfeControlSramLock();
ClearSramState(mPlaybackSramState);
mPlaybackSramState = GetSramState();
AfeControlSramUnLock();
AudDrv_Clk_Off();
return 0;
}