void V_Core::StartADMAWrite(u16 *pMem, u32 sz)
{
#ifndef ENABLE_NEW_IOPDMA_SPU2
int size = (sz)&(~511);
if(MsgAutoDMA()) ConLog("* SPU2-X: DMA%c AutoDMA Transfer of %d bytes to %x (%02x %x %04x).\n",
GetDmaIndexChar(), size<<1, TSA, DMABits, AutoDMACtrl, (~Regs.ATTR)&0x7fff);
InputDataProgress = 0;
if((AutoDMACtrl&(Index+1))==0)
{
TSA = 0x2000 + (Index<<10);
DMAICounter = size;
}
else if(size>=512)
{
InputDataLeft = size;
if(AdmaInProgress==0)
{
#ifdef PCM24_S1_INTERLEAVE
if((Index==1)&&((PlayMode&8)==8))
{
AutoDMAReadBuffer(Index,1);
}
else
{
AutoDMAReadBuffer(Index,0);
}
#else
if( ((PlayMode&4)==4) && (Index==0) )
Cores[0].InputPosRead=0;
AutoDMAReadBuffer(0);
#endif
if(size==512)
DMAICounter = size;
}
AdmaInProgress = 1;
}
else
{
InputDataLeft = 0;
DMAICounter = 1;
}
TADR = MADR + (size<<1);
#endif
}
void StartADMAWrite(int core,u16 *pMem, u32 sz)
{
int size=(sz)&(~511);
if(MsgAutoDMA()) ConLog(" * SPU2: DMA%c AutoDMA Transfer of %d bytes to %x (%02x %x %04x).\n",
(core==0)?'4':'7',size<<1,Cores[core].TSA,Cores[core].DMABits,Cores[core].AutoDMACtrl,(~Cores[core].Regs.ATTR)&0x7fff);
Cores[core].InputDataProgress=0;
if((Cores[core].AutoDMACtrl&(core+1))==0)
{
Cores[core].TSA=0x2000+(core<<10);
Cores[core].DMAICounter=size;
}
else if(size>=512)
{
Cores[core].InputDataLeft=size;
if(Cores[core].AdmaInProgress==0)
{
#ifdef PCM24_S1_INTERLEAVE
if((core==1)&&((PlayMode&8)==8))
{
AutoDMAReadBuffer(core,1);
}
else
{
AutoDMAReadBuffer(core,0);
}
#else
if(((PlayMode&4)==4)&&(core==0))
Cores[0].InputPos=0;
AutoDMAReadBuffer(core,0);
#endif
if(size==512)
Cores[core].DMAICounter=size;
}
Cores[core].AdmaInProgress=1;
}
else
{
Cores[core].InputDataLeft=0;
Cores[core].DMAICounter=1;
}
Cores[core].TADR=Cores[core].MADR+(size<<1);
}
