static void brcm_pm_memc1_ddr_params(int restore)
{
int ii = 0;
if (restore) {
/* program ddr iobuf registers */
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_2,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_3,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_5,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_0,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_1,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_0,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_1,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_2,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_3,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_4,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_CNTRLR_CONFIG,
memc1_config.ddr_params[ii++]);
BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL,
memc1_config.ddr_params[ii++]);
} else {
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_2);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_3);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_5);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_0);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_1);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_0);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_1);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_2);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_3);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_4);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_CNTRLR_CONFIG);
memc1_config.ddr_params[ii++] =
BDEV_RD(BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL);
}
BUG_ON(ii > MAX_DDR_PARAMS_NUM);
}
void __init board_pinmux_setup(void)
{
#if !defined(CONFIG_BRCM_IKOS)
#if defined(CONFIG_BCM35230)
#if defined(CONFIG_BCMGENET_0_GPHY)
PINMUX(6, i2ssosck_outd, 2);
PINMUX(6, i2ssd_outd, 2);
PINMUX(6, i2sws_outd, 2);
PINMUX(6, i2ssck_outd, 2);
PINMUX(6, i2ssosck_outc, 2);
PINMUX(6, i2ssd_outc, 2);
PINMUX(6, i2sws_outc, 2);
PINMUX(6, i2ssck_outc, 2);
PINMUX(7, i2ssd_in, 5);
PINMUX(7, i2sws_in, 5);
PINMUX(7, i2ssck_in, 5);
PINMUX(8, gpio_4, 4);
PINMUX(9, gpio_74, 3);
PINMUX(10, gpio_79, 3);
PINMUX(10, gpio_78, 3);
PINMUX(10, gpio_77, 3);
PINMUX(10, gpio_76, 3);
PINMUX(10, gpio_75, 3);
PINMUX(11, dint, 2);
brcm_ext_mii_mode = BRCM_PHY_TYPE_EXT_MII;
#endif
#elif defined(CONFIG_BCM3548B0)
PINMUX(6, gpio_30, 2); /* UARTB TX */
PINMUX(6, gpio_31, 2); /* UARTB RX */
PINMUX(7, gpio_43, 2); /* UARTC TX */
PINMUX(7, gpio_42, 2); /* UARTC RX */
PINMUX(6, gpio_32, 2); /* SPI */
PINMUX(6, gpio_33, 2);
PINMUX(6, gpio_34, 2);
PINMUX(6, gpio_35, 2);
PINMUX(6, gpio_36, 2);
#elif defined(CONFIG_BCM3563C0)
/* UARTB RX requires board mod; UARTC is on RS232 daughtercard */
PINMUX(10, gpio_47, 1); /* UARTB TX */
PINMUX(10, gpio_46, 2); /* UARTB RX */
PINMUX(7, gpio_17, 1); /* UARTC TX */
PINMUX(7, gpio_16, 1); /* UARTC RX */
#elif defined(CONFIG_BCM7038C0)
PINMUX(9, gpio_47, 2); /* UARTB TX */
PINMUX(9, gpio_46, 2); /* UARTB RX */
#elif defined(CONFIG_BCM7118C0)
PINMUX(1, uart_txdb, 0); /* UARTB TX */
PINMUX(1, uart_rxdb, 0); /* UARTB RX */
PINMUX(11, gpio_54, 2); /* UARTC TX */
PINMUX(11, gpio_55, 2); /* UARTC RX */
#elif defined(CONFIG_BCM7125)
PINMUX(8, uart_1_rxd, 0); /* UARTB RX */
PINMUX(9, uart_1_txd, 0); /* UARTB TX */
PINMUX(9, gpio_16, 1); /* UARTC RX */
PINMUX(9, gpio_17, 1); /* UARTC TX */
PINMUX(10, sgpio_02, 1); /* MoCA I2C on BSCB */
PINMUX(10, sgpio_03, 1);
brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCB_REG_START);
brcm_ext_mii_mode = BRCM_PHY_TYPE_EXT_MII;
#elif defined(CONFIG_BCM7231)
PINMUX(11, gpio_94, 1); /* UARTB TX */
PINMUX(11, gpio_95, 1); /* UARTB RX */
if (BRCM_PROD_ID() == 0x7230) {
/* 7230 is not the same ballout as 7231 */
AON_PINMUX(0, aon_gpio_04, 6); /* SDIO */
AON_PINMUX(0, aon_gpio_05, 6);
AON_PINMUX(1, aon_gpio_12, 5);
AON_PINMUX(1, aon_gpio_13, 5);
AON_PINMUX(2, aon_gpio_14, 5);
AON_PINMUX(2, aon_gpio_15, 6);
AON_PINMUX(2, aon_gpio_16, 6);
AON_PINMUX(2, aon_gpio_17, 6);
AON_PINMUX(2, aon_gpio_18, 6);
AON_PINMUX(2, aon_gpio_19, 6);
/* disable GPIO pulldowns */
BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0,
aon_gpio_04_pad_ctrl, 0);
BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0,
aon_gpio_05_pad_ctrl, 0);
BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
aon_gpio_12_pad_ctrl, 0);
BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
aon_gpio_13_pad_ctrl, 0);
BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
aon_gpio_14_pad_ctrl, 0);
BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
aon_gpio_15_pad_ctrl, 0);
BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
aon_gpio_16_pad_ctrl, 0);
BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
aon_gpio_17_pad_ctrl, 0);
BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
aon_gpio_18_pad_ctrl, 0);
BDEV_WR_F_RB(AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1,
aon_gpio_19_pad_ctrl, 0);
/* limit speed to 25MHz due to AON pad timing restrictions */
BDEV_UNSET(BCHP_SDIO_0_CFG_CAP_REG0, 1 << 19); /* Highspd=0 */
BDEV_SET(BCHP_SDIO_0_CFG_CAP_REG1, 1 << 31); /* Override=1 */
} else {
/* set RGMII lines to 2.5V */
BDEV_WR_F(SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0,
rgmii_0_pad_mode, 1);
PINMUX(15, gpio_132, 1); /* RGMII RX */
PINMUX(15, gpio_133, 1);
PINMUX(15, gpio_134, 1);
PINMUX(16, gpio_139, 1);
PINMUX(16, gpio_140, 1);
PINMUX(16, gpio_141, 1);
PINMUX(16, gpio_142, 1);
PINMUX(16, gpio_138, 1); /* RGMII TX */
PINMUX(17, gpio_143, 1);
PINMUX(17, gpio_144, 1);
PINMUX(17, gpio_145, 1);
PINMUX(17, gpio_146, 1);
PINMUX(17, gpio_147, 1);
PINMUX(17, gpio_149, 1); /* RGMII MDIO */
PINMUX(16, gpio_137, 1);
/* no pulldown on RGMII lines */
PADCTRL(8, gpio_132_pad_ctrl, 0);
PADCTRL(8, gpio_133_pad_ctrl, 0);
PADCTRL(8, gpio_134_pad_ctrl, 0);
PADCTRL(8, gpio_137_pad_ctrl, 0);
PADCTRL(8, gpio_138_pad_ctrl, 0);
PADCTRL(9, gpio_139_pad_ctrl, 0);
PADCTRL(9, gpio_140_pad_ctrl, 0);
PADCTRL(9, gpio_141_pad_ctrl, 0);
PADCTRL(9, gpio_142_pad_ctrl, 0);
PADCTRL(9, gpio_143_pad_ctrl, 0);
PADCTRL(9, gpio_144_pad_ctrl, 0);
PADCTRL(9, gpio_145_pad_ctrl, 0);
PADCTRL(9, gpio_146_pad_ctrl, 0);
PADCTRL(9, gpio_147_pad_ctrl, 0);
PADCTRL(9, gpio_149_pad_ctrl, 0);
PINMUX(14, gpio_122, 1); /* SDIO */
PINMUX(14, gpio_123, 1);
PINMUX(14, gpio_124, 1);
PINMUX(14, gpio_125, 1);
PINMUX(14, gpio_126, 1);
PINMUX(15, gpio_127, 1);
PINMUX(15, gpio_128, 1);
PINMUX(15, gpio_129, 1);
PINMUX(15, gpio_130, 1);
PINMUX(15, gpio_131, 1);
/* no pulldown on SDIO lines */
PADCTRL(7, gpio_122_pad_ctrl, 0);
PADCTRL(7, gpio_123_pad_ctrl, 0);
PADCTRL(8, gpio_124_pad_ctrl, 0);
PADCTRL(8, gpio_125_pad_ctrl, 0);
PADCTRL(8, gpio_126_pad_ctrl, 0);
PADCTRL(8, gpio_127_pad_ctrl, 0);
PADCTRL(8, gpio_128_pad_ctrl, 0);
PADCTRL(8, gpio_129_pad_ctrl, 0);
PADCTRL(8, gpio_130_pad_ctrl, 0);
PADCTRL(8, gpio_131_pad_ctrl, 0);
}
#elif defined(CONFIG_BCM7325B0)
PINMUX(11, uart_txdb, 0); /* UARTB TX */
PINMUX(11, uart_rxdb, 0); /* UARTB RX */
#if defined(CONFIG_BCMEMAC_EXTMII)
PINMUX(5, gpio_32, 1); /* MII */
PINMUX(5, gpio_33, 1);
PINMUX(5, gpio_34, 1);
PINMUX(5, gpio_35, 1);
PINMUX(5, gpio_36, 1);
PINMUX(5, gpio_37, 1);
PINMUX(6, gpio_38, 1);
PINMUX(6, gpio_39, 1);
PINMUX(6, gpio_40, 1);
PINMUX(6, gpio_41, 1);
PINMUX(6, gpio_42, 1);
PINMUX(6, gpio_43, 1);
PINMUX(6, gpio_44, 1);
PINMUX(6, gpio_45, 1);
PINMUX(6, gpio_46, 1);
PINMUX(6, gpio_47, 1);
PINMUX(7, gpio_48, 1);
PINMUX(7, gpio_49, 1);
#endif
#elif defined(CONFIG_BCM7335B0)
PINMUX(7, gpio_034, 1); /* UARTB TX */
PINMUX(7, gpio_035, 1); /* UARTB RX */
PINMUX(7, gpio_038, 1); /* UARTC TX */
PINMUX(7, gpio_039, 1); /* UARTC RX */
PINMUX(9, gpio_054, 3); /* MII */
PINMUX(9, gpio_055, 3);
PINMUX(9, gpio_056, 3);
PINMUX(9, gpio_057, 3);
PINMUX(9, gpio_058, 3);
PINMUX(9, gpio_059, 3);
PINMUX(9, gpio_060, 3);
PINMUX(9, gpio_061, 3);
PINMUX(9, gpio_062, 3);
PINMUX(10, gpio_063, 3);
PINMUX(10, gpio_065, 3);
PINMUX(10, gpio_066, 3);
PINMUX(10, gpio_067, 3);
PINMUX(10, gpio_068, 3);
PINMUX(10, gpio_069, 3);
PINMUX(10, gpio_070, 3);
PINMUX(10, gpio_071, 3);
PINMUX(10, gpio_072, 3);
#elif defined(CONFIG_BCM7340)
PINMUX(18, uart_rxdb, 0); /* UARTB RX */
PINMUX(18, uart_txdb, 0); /* UARTB TX */
PINMUX(4, gpio_00, 3); /* UARTC RX */
PINMUX(4, gpio_01, 3); /* UARTC TX */
PINMUX(14, sgpio_00, 1); /* MoCA I2C on BSCA */
PINMUX(14, sgpio_01, 1);
brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCA_REG_START);
#elif defined(CONFIG_BCM7342)
PINMUX(10, gpio_023, 1); /* ENET LEDs */
PINMUX(11, gpio_024, 1);
PINMUX(23, vo_656_7, 1); /* MoCA LEDs */
PINMUX(23, vo_656_clk, 1);
PINMUX(12, gpio_034, 1); /* UARTB TX */
PINMUX(12, gpio_035, 1); /* UARTB RX */
PINMUX(12, gpio_038, 1); /* UARTC TX */
PINMUX(12, gpio_039, 1); /* UARTC RX */
PINMUX(21, sgpio_02, 1); /* MoCA I2C on BSCB */
PINMUX(21, sgpio_03, 1);
brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCB_REG_START);
#elif defined(CONFIG_BCM7344)
AON_PINMUX(0, aon_gpio_00, 3); /* UARTC RX (NC) */
AON_PINMUX(0, aon_gpio_01, 3); /* UARTC TX (NC) */
/* NOTE: this is buggy in A0 */
AON_PINMUX(2, aon_sgpio_00, 1); /* MoCA I2C */
AON_PINMUX(2, aon_sgpio_01, 1);
brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCC_REG_START);
#if defined(CONFIG_BCMGENET_0_GPHY)
/* select MAC0 for RGMII */
BDEV_WR_F(SUN_TOP_CTRL_GENERAL_CTRL_0, mii_genet_mac_select, 0);
PINMUX(9, gpio_31, 1); /* RGMII RX */
PINMUX(9, gpio_28, 1);
PINMUX(9, gpio_27, 1);
PINMUX(9, gpio_26, 1);
PINMUX(8, gpio_25, 1);
PINMUX(8, gpio_24, 1);
PINMUX(8, gpio_23, 1);
PINMUX(9, gpio_34, 1); /* RGMII TX */
PINMUX(9, gpio_35, 1);
PINMUX(10, gpio_36, 1);
PINMUX(10, gpio_40, 1);
PINMUX(10, gpio_39, 1);
PINMUX(10, gpio_38, 1);
PINMUX(10, gpio_37, 1);
PINMUX(10, gpio_32, 1); /* ENET MDIO */
PINMUX(10, gpio_33, 1);
PINMUX(9, gpio_29, 1);
PINMUX(9, gpio_30, 1);
#endif
#elif defined(CONFIG_BCM7346)
PINMUX(15, gpio_068, 2); /* MoCA link */
PINMUX(16, gpio_069, 1); /* MoCA activity */
PINMUX(9, gpio_017, 1); /* UARTB TX */
PINMUX(9, gpio_018, 1); /* UARTB RX */
PINMUX(10, gpio_021, 1); /* UARTC TX */
PINMUX(10, gpio_022, 1); /* UARTC RX */
PINMUX(16, sgpio_02, 1); /* MoCA I2C on BSCB */
PINMUX(16, sgpio_03, 1);
brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCB_REG_START);
#elif defined(CONFIG_BCM7400D0)
PINMUX(3, gpio_008, 2); /* UARTB TX */
PINMUX(3, gpio_007, 2); /* UARTB RX */
PINMUX(3, gpio_012, 2); /* UARTC TX */
PINMUX(3, gpio_011, 2); /* UARTC RX */
/* CFE forgot to set these */
PINMUX(2, gpio_000, 1); /* enet_activity */
PINMUX(2, gpio_001, 1); /* enet_link */
#elif defined(CONFIG_BCM7401C0)
PINMUX(11, gpio_49, 1); /* UARTA TX */
PINMUX(11, gpio_50, 1); /* UARTA RX */
/* default console is on UARTB */
PINMUX(10, gpio_42, 1); /* UARTC TX */
PINMUX(10, gpio_39, 1); /* UARTC RX */
/* CFE forgot to set these */
PINMUX(10, gpio_43, 1); /* enet_link */
PINMUX(10, gpio_45, 1); /* enet_activity */
#elif defined(CONFIG_BCM7403A0)
PINMUX(11, gpio_49, 1); /* UARTA TX */
PINMUX(11, gpio_50, 1); /* UARTA RX */
/* default console is on UARTB */
PINMUX(10, gpio_42, 1); /* UARTC TX */
PINMUX(10, gpio_39, 1); /* UARTC RX */
/* CFE forgot to set these */
PINMUX(10, gpio_43, 1); /* enet_link */
PINMUX(10, gpio_45, 1); /* enet_activity */
#elif defined(CONFIG_BCM7405B0)
#if !defined(CONFIG_KGDB)
/*
* Default: use MII, no UARTB/UARTC.
* BCM97405 SW2801-7 should be OFF
*/
PINMUX(2, gpio_002, 1); /* MII */
PINMUX(2, gpio_003, 1);
PINMUX(3, gpio_004, 1);
PINMUX(3, gpio_005, 1);
PINMUX(3, gpio_006, 1);
PINMUX(3, gpio_007, 1);
PINMUX(3, gpio_008, 1);
PINMUX(3, gpio_009, 1);
PINMUX(3, gpio_010, 1);
PINMUX(3, gpio_011, 1);
PINMUX(3, gpio_012, 1);
PINMUX(3, gpio_013, 1);
PINMUX(4, gpio_014, 1);
PINMUX(4, gpio_015, 1);
PINMUX(4, gpio_016, 1);
PINMUX(4, gpio_017, 1);
PINMUX(4, gpio_018, 1);
PINMUX(4, gpio_019, 1);
#else
/*
* Alternate: use UARTB, UARTC. Required for kgdb.
* BCM97405 SW2801-7 should be ON
*/
PINMUX(3, gpio_008, 2); /* UARTB TX */
PINMUX(3, gpio_007, 2); /* UARTB RX */
PINMUX(3, gpio_012, 2); /* UARTC TX */
PINMUX(3, gpio_011, 2); /* UARTC RX */
printk(KERN_WARNING "%s: disabling MII to enable extra UARTs\n",
__func__);
#endif
#elif defined(CONFIG_BCM7408)
PINMUX(2, gpio_01, 1); /* MoCA LEDs */
PINMUX(2, gpio_02, 1);
PINMUX(3, gpio_06, 1); /* UARTB RX */
PINMUX(3, gpio_05, 1); /* UARTB TX */
PINMUX(3, gpio_12, 1); /* UARTC RX */
PINMUX(3, gpio_11, 1); /* UARTC TX */
PINMUX(7, sgpio_02, 1); /* MoCA I2C on BSCB */
PINMUX(7, sgpio_03, 1);
brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCB_REG_START);
#elif defined(CONFIG_BCM7420)
PINMUX(7, gpio_000, 1); /* ENET LEDs */
PINMUX(7, gpio_001, 1);
PINMUX(9, gpio_017, 1); /* MoCA LEDs */
PINMUX(9, gpio_019, 1);
PINMUX(17, gpio_081, 4); /* UARTB RX */
PINMUX(17, gpio_082, 4); /* UARTB TX */
PINMUX(9, gpio_022, 3); /* UARTC RX */
PINMUX(9, gpio_023, 3); /* UARTC TX */
PINMUX(21, sgpio_02, 1); /* MoCA I2C on BSCB */
PINMUX(21, sgpio_03, 1);
brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCB_REG_START);
#if defined(CONFIG_BCMGENET_0_GPHY)
/* set RGMII lines to 2.5V */
BDEV_WR_F(SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1, rgmii_pad_mode, 1);
PINMUX(7, gpio_002, 1); /* RGMII RX */
PINMUX(7, gpio_003, 1);
PINMUX(7, gpio_004, 1);
PINMUX(7, gpio_005, 1);
PINMUX(7, gpio_006, 1);
PINMUX(7, gpio_007, 1);
PINMUX(8, gpio_009, 1); /* RGMII TX */
PINMUX(8, gpio_010, 1);
PINMUX(8, gpio_011, 1);
PINMUX(8, gpio_012, 1);
PINMUX(8, gpio_013, 1);
PINMUX(8, gpio_014, 1);
PINMUX(20, gpio_108, 3); /* ENET MDIO */
PINMUX(20, gpio_109, 4);
#endif
#elif defined(CONFIG_BCM7422) || defined(CONFIG_BCM7425)
/* Bootloader indicates the availability of SDIO_0 in SCRATCH reg */
if ((BDEV_RD(BCHP_SDIO_0_CFG_SCRATCH) & 0x01) == 0) {
PINMUX(14, gpio_072, 2);
PINMUX(14, gpio_073, 2);
PINMUX(14, gpio_074, 2);
PINMUX(14, gpio_075, 2);
PINMUX(15, gpio_076, 2);
PINMUX(15, gpio_077, 2);
PINMUX(15, gpio_078, 2);
PINMUX(15, gpio_079, 2);
PINMUX(15, gpio_080, 2);
PINMUX(15, gpio_081, 2);
/* enable internal pullups */
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9,
gpio_072_pad_ctrl, 2);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
gpio_073_pad_ctrl, 2);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
gpio_074_pad_ctrl, 2);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
gpio_075_pad_ctrl, 2);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
gpio_076_pad_ctrl, 2);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
gpio_077_pad_ctrl, 2);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
gpio_078_pad_ctrl, 2);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
gpio_079_pad_ctrl, 2);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
gpio_080_pad_ctrl, 2);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10,
gpio_081_pad_ctrl, 2);
/* always use 3.3V (SDIO0_LOW_V_SEL_N=1) */
BDEV_UNSET(BCHP_GIO_AON_IODIR_LO, 1 << 4);
BDEV_SET(BCHP_GIO_AON_DATA_LO, 1 << 4);
}
PINMUX(18, sgpio_00, 1); /* MoCA I2C on BSCA */
PINMUX(19, sgpio_01, 1);
brcm_moca_i2c_base = BPHYSADDR(BCHP_BSCA_REG_START);
#elif defined(CONFIG_BCM7468)
/* NOTE: R1022 and R1023 must be installed to use UARTB */
PINMUX(4, gpio_15, 3); /* UARTB TX */
PINMUX(4, gpio_14, 3); /* UARTB RX */
PINMUX(3, gpio_01, 1); /* SDIO */
PINMUX(3, gpio_02, 1);
PINMUX(3, gpio_03, 1);
PINMUX(3, gpio_04, 1);
PINMUX(3, gpio_05, 1);
PINMUX(3, gpio_06, 1);
PINMUX(3, gpio_07, 1);
PINMUX(3, gpio_08, 1);
PINMUX(4, gpio_09, 1);
PINMUX(4, gpio_10, 1);
/* disable GPIO pulldowns, in order to get 3.3v on SDIO pins */
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2, gpio_01_pad_ctrl, 0);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2, gpio_02_pad_ctrl, 0);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2, gpio_03_pad_ctrl, 0);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2, gpio_04_pad_ctrl, 0);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2, gpio_05_pad_ctrl, 0);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2, gpio_06_pad_ctrl, 0);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2, gpio_07_pad_ctrl, 0);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2, gpio_08_pad_ctrl, 0);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2, gpio_09_pad_ctrl, 0);
BDEV_WR_F_RB(SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2, gpio_10_pad_ctrl, 0);
brcm_ext_mii_mode = BRCM_PHY_TYPE_EXT_MII;
#elif defined(CONFIG_BCM7550)
PINMUX(13, gpio_84, 1); /* UARTB TX */
PINMUX(13, gpio_85, 1); /* UARTB RX */
PINMUX(13, gpio_86, 1); /* UARTC TX */
PINMUX(13, gpio_87, 1); /* UARTC RX */
#elif defined(CONFIG_BCM7630)
PINMUX(7, gpio_02, 1); /* UARTB RX */
PINMUX(7, gpio_03, 1); /* UARTB TX */
PINMUX(7, gpio_04, 1); /* UARTC RX */
PINMUX(7, gpio_05, 1); /* UARTC TX */
/* disable GPIO pulldowns, in order to get 3.3v on SDIO pins */
BDEV_WR_F_RB(CLK_SDIO_PAD_CTRL, SDIO_PDN, 0);
PINMUX(11, gpio_36, 1); /* SDIO */
PINMUX(11, gpio_37, 1);
PINMUX(11, gpio_38, 1);
PINMUX(11, gpio_39, 1);
PINMUX(12, gpio_40, 1);
PINMUX(12, gpio_41, 1);
PINMUX(12, gpio_42, 1);
PINMUX(12, gpio_43, 1);
PINMUX(12, gpio_44, 1);
#elif defined(CONFIG_BCM7635)
PINMUX(7, gpio_02, 1); /* UARTB RX */
PINMUX(8, gpio_03, 1); /* UARTB TX */
PINMUX(8, gpio_04, 1); /* UARTC RX */
PINMUX(8, gpio_05, 1); /* UARTC TX */
/* disable GPIO pulldowns, in order to get 3.3v on SDIO pins */
BDEV_WR_F_RB(VCXO_CTL_MISC_GPIO_PAD_CTRL, GPIO_PDN, 0);
PINMUX(12, gpio_36, 1); /* SDIO */
PINMUX(12, gpio_37, 1);
PINMUX(12, gpio_38, 1);
PINMUX(12, gpio_39, 1);
PINMUX(12, gpio_40, 1);
PINMUX(12, gpio_41, 1);
PINMUX(12, gpio_42, 1);
PINMUX(13, gpio_43, 1);
PINMUX(13, gpio_44, 1);
#endif /* chip type */
#endif /* !defined(CONFIG_BRCM_IKOS) */
}
static void __brcm_pm_memc1_resume(int mode)
{
u32 val, cur_val;
s32 sval, scur_val, inc_val;
DBG(KERN_DEBUG "%s %d\n", __func__, mode);
/* power up LDOs */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG,
LDO_PWRDN, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_WORDSLICE_CNTRL_1,
LDO_PWRDN, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_WORDSLICE_CNTRL_1,
LDO_PWRDN, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL, BYPASS_PHASE, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_DDR_PAD_CNTRL,
IDDQ_MODE_ON_SELFREF, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_DDR_PAD_CNTRL,
IDDQ_MODE_ON_SELFREF, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_WORDSLICE_CNTRL_1,
PWRDN_DLL_ON_SELFREF, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_WORDSLICE_CNTRL_1,
PWRDN_DLL_ON_SELFREF, 0);
BDEV_UNSET(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK |
BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK);
mdelay(1);
/* reset the freq divider */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, FREQ_DIV_RESET, 1);
mdelay(1);
/* reset DATAPATH_216, RD_DATAPATH_RESET, RESET_DATAPATH_DDR */
BDEV_SET_RB(BCHP_MEMC_DDR23_APHY_AC_1_RESET,
BCHP_MEMC_DDR23_APHY_AC_1_RESET_DATAPATH_216_RESET_MASK |
BCHP_MEMC_DDR23_APHY_AC_1_RESET_RD_DATAPATH_RESET_MASK |
BCHP_MEMC_DDR23_APHY_AC_1_RESET_DATAPATH_DDR_RESET_MASK);
mdelay(1);
/* reset the vcxo */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, VCXO_RESET, 1);
mdelay(1);
/* de-assert reset the vcxo */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, VCXO_RESET, 0);
/* de-assert reset the freq divider */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, FREQ_DIV_RESET, 0);
mdelay(1);
/* check for pll lock */
while (!BDEV_RD_F(MEMC_DDR23_APHY_AC_1_DDR_PLL_LOCK_STATUS,
LOCK_STATUS))
;
/* reload shmoo values */
/* set wl0_dq phase */
val = memc1_config.shmoo_value[4];
cur_val = 0;
while (cur_val <= val) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL,
cur_val);
cur_val++;
}
/* set wl1_dq phase */
val = memc1_config.shmoo_value[5];
cur_val = 0;
while (cur_val <= val) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL,
cur_val);
cur_val++;
}
/* set ch2 phase */
val = memc1_config.shmoo_value[6];
cur_val = 0;
while (cur_val < val) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL,
cur_val);
cur_val++;
}
/* set ch6 phase */
val = memc1_config.shmoo_value[7];
cur_val = 0;
while (cur_val < val) {
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL,
BYPASS_PHASE, cur_val);
cur_val++;
}
/* set wl0_dqs0 phases */
sval = memc1_config.shmoo_value[0];
scur_val = 0;
inc_val = sval > 0 ? 1 : -1;
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL,
0);
while (sval != scur_val) {
scur_val += inc_val;
BDEV_WR_RB(
BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL,
scur_val);
}
/* set wl0_dqs1 phases */
sval = memc1_config.shmoo_value[1];
scur_val = 0;
inc_val = sval > 0 ? 1 : -1;
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL,
0);
while (sval != scur_val) {
scur_val += inc_val;
BDEV_WR_RB(
BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL,
scur_val);
}
/* set wl1_dqs0 phases */
sval = memc1_config.shmoo_value[2];
scur_val = 0;
inc_val = sval > 0 ? 1 : -1;
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL,
0);
while (sval != scur_val) {
scur_val += inc_val;
BDEV_WR_RB(
BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL,
scur_val);
}
/* set wl1_dqs1 phases */
sval = memc1_config.shmoo_value[3];
scur_val = 0;
inc_val = sval > 0 ? 1 : -1;
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL,
0);
while (sval != scur_val) {
scur_val += inc_val;
BDEV_WR_RB(
BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL,
scur_val);
}
/* reset the word slice dll */
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_WORD_SLICE_DLL_RESET, 1);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_WORD_SLICE_DLL_RESET, 1);
mdelay(1);
/* reset VCDL values */
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE0_VCDL_PHASE_CNTL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE1_VCDL_PHASE_CNTL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE0_VCDL_PHASE_CNTL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE1_VCDL_PHASE_CNTL, 0);
/* de-assert reset of the word slice dll */
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_WORD_SLICE_DLL_RESET, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_WORD_SLICE_DLL_RESET, 0);
mdelay(1);
/* de-assert reset from DATAPATH_216_RESET */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, DATAPATH_216_RESET, 0);
/* de-assert reset from RD_DATAPATH_RESET */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, RD_DATAPATH_RESET, 0);
/* de-assert reset from DATAPATH_DDR_RESET */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, DATAPATH_DDR_RESET, 0);
mdelay(1);
/*
* Reload VCDL values:
*/
cur_val = 0x0101;
while (cur_val <= memc1_config.vcdl[0]) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE0_VCDL_PHASE_CNTL,
cur_val);
cur_val += 0x0101;
}
cur_val = 0x0101;
while (cur_val <= memc1_config.vcdl[1]) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE1_VCDL_PHASE_CNTL,
cur_val);
cur_val += 0x0101;
}
cur_val = 0x0101;
while (cur_val <= memc1_config.vcdl[2]) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE0_VCDL_PHASE_CNTL,
cur_val);
cur_val += 0x0101;
}
cur_val = 0x0101;
while (cur_val <= memc1_config.vcdl[3]) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE1_VCDL_PHASE_CNTL,
cur_val);
cur_val += 0x0101;
}
if (mode) {
/* Remove CKE_IDDQ */
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
BDEV_RD(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL) & ~4);
BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET,
MEMC_DRAM_INIT, 0);
BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET,
MEMC_CORE, 0);
mdelay(1);
printk(KERN_DEBUG "memc1: powered up\n");
} else
printk(KERN_DEBUG "memc1: resumed\n");
}
static void __brcm_pm_memc1_suspend(int mode)
{
DBG(KERN_DEBUG "%s %d\n", __func__, mode);
if (!memc1_config.shmoo_valid) {
memc1_config.shmoo_value[0] =
BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA0);
memc1_config.shmoo_value[1] =
BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA1);
memc1_config.shmoo_value[2] =
BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA2);
memc1_config.shmoo_value[3] =
BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA3);
memc1_config.shmoo_value[4] =
BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA4);
memc1_config.shmoo_value[5] =
BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA5);
memc1_config.shmoo_value[6] =
BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA6);
memc1_config.shmoo_value[7] =
BDEV_RD(BCHP_MEMC_MISC_1_SCRATCH_0);
memc1_config.shmoo_valid = 1;
DBG(KERN_DEBUG "%s: SHMOO values saved\n", __func__);
}
/* save VCDL values */
memc1_config.vcdl[0] =
BDEV_RD(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE0_VCDL_PHASE_CNTL);
memc1_config.vcdl[1] =
BDEV_RD(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE1_VCDL_PHASE_CNTL);
memc1_config.vcdl[2] =
BDEV_RD(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE0_VCDL_PHASE_CNTL);
memc1_config.vcdl[3] =
BDEV_RD(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE1_VCDL_PHASE_CNTL);
/* MEMC1 */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
DEVCLK_OFF_ON_SELFREF, 1);
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
HIZ_ON_SELFREF, 1);
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
IDDQ_MODE_ON_SELFREF, 1);
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_POWERDOWN,
PLLCLKS_OFF_ON_SELFREF, 1);
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_POWERDOWN,
LOWPWR_EN, 1);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_DDR_PAD_CNTRL,
IDDQ_MODE_ON_SELFREF, 1);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_DDR_PAD_CNTRL,
IDDQ_MODE_ON_SELFREF, 1);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_WORDSLICE_CNTRL_1,
PWRDN_DLL_ON_SELFREF, 1);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_WORDSLICE_CNTRL_1,
PWRDN_DLL_ON_SELFREF, 1);
brcm_pm_memc1_sspd_control(1);
if (mode) {
/* CKE_IDDQ */
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
BDEV_RD(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL) | 4);
BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET,
MEMC_DRAM_INIT, 1);
BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET,
MEMC_CORE, 1);
BDEV_WR_F_RB(MEMC_DDR_1_DRAM_INIT_CNTRL,
DDR3_INIT_MODE, 1);
mdelay(1);
printk(KERN_DEBUG "memc1: powered down\n");
} else
printk(KERN_DEBUG "memc1: suspended\n");
/* Power down LDOs */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG,
LDO_PWRDN, 1);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_WORDSLICE_CNTRL_1,
LDO_PWRDN, 1);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_WORDSLICE_CNTRL_1,
LDO_PWRDN, 1);
}
void __init prom_init(void)
{
#ifdef CONFIG_MIPS_BRCM97XXX
int hasCfeParms = 0;
int res = -1;
char msg[COMMAND_LINE_SIZE];
extern void determineBootFromFlashOrRom(void);
#endif
uart_init(27000000);
/* jipeng - mask out UPG L2 interrupt here */
BDEV_WR(BCHP_IRQ0_IRQEN, 0);
#ifdef CONFIG_TIVO_KONTIKI
board_pinmux_setup();
#endif
/* Fill in platform information */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BRCM_STB;
#ifdef BRCM_SATA_SUPPORTED
brcm_sata_enabled = 1;
#endif
#ifdef BRCM_ENET_SUPPORTED
brcm_enet_enabled = 1;
#endif
#ifdef BRCM_EMAC_1_SUPPORTED
brcm_emac_1_enabled = 1;
#endif
#ifdef BRCM_PCI_SUPPORTED
brcm_pci_enabled = 1;
#endif
#ifdef CONFIG_SMP
brcm_smp_enabled = 1;
#endif
#ifdef CONFIG_MIPS_BCM7118
/* detect 7118RNG board */
if( BDEV_RD(BCHP_CLKGEN_REG_START) == 0x1c )
brcm_sata_enabled = 0;
/* onchip DOCSIS owns the ENET */
brcm_enet_enabled = 0;
#endif
#ifdef CONFIG_MIPS_BCM7405
/* detect 7406 */
if(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) &
BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_sata_disable_MASK)
brcm_sata_enabled = 0;
switch(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) & 0xf) {
case 0x0:
/* 7405/7406 */
break;
case 0x1:
/* 7466 */
brcm_pci_enabled = 0;
brcm_emac_1_enabled = 0;
break;
case 0x3:
/* 7106 */
brcm_emac_1_enabled = 0;
brcm_smp_enabled = 0;
break;
case 0x4:
/* 7205 */
brcm_emac_1_enabled = 0;
break;
}
#endif
#if defined( CONFIG_MIPS_BCM7118 ) || defined( CONFIG_MIPS_BCM7401C0 ) \
|| defined( CONFIG_MIPS_BCM7402C0 ) || defined( CONFIG_MIPS_BCM3563 ) \
|| defined (CONFIG_MIPS_BCM3563C0)
/*need set bus to async mode before enabling the following*/
if(!(read_c0_diag4() & 0x400000))
{
int val=read_c0_diag4();
write_c0_diag4(val | 0x400000);
sprintf(msg, "CP0 reg 22 sel 0 to 5: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", read_c0_diag(), read_c0_diag1(), read_c0_diag2(), read_c0_diag3(), read_c0_diag4(), read_c0_diag5());
uart_puts(msg);
write_c0_config(0x80008083);
sprintf(msg, "CP0 reg 16 sel 0 to 1: 0x%08x 0x%08x \n", read_c0_config(), read_c0_config1());
uart_puts(msg);
}
/* Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT) */
BDEV_WR(0x0000040c, 0x264);
/* Enable Split Mode (BCHP_MISB_BRIDGE_MISB_SPLIT_MODE) */
BDEV_WR(0x00000410, 0x1);
#elif defined( CONFIG_MIPS_BCM7440A0 )
if(!(read_c0_diag4() & 0x400000))
{
int val=read_c0_diag4();
write_c0_diag4(val | 0x400000);
sprintf(msg, "CP0 reg 22 sel 0 to 5: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", read_c0_diag(), read_c0_diag1(), read_c0_diag2(), read_c0_diag3(), read_c0_diag4(), read_c0_diag5());
uart_puts(msg);
write_c0_config(0x80008083);
sprintf(msg, "CP0 reg 16 sel 0 to 1: 0x%08x 0x%08x \n", read_c0_config(), read_c0_config1());
uart_puts(msg);
}
/* Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT) */
BDEV_WR(0x0000040c, 0x2803);
#endif
#ifdef CONFIG_TIVO_MOJAVE
if ( cfe_seal != CFE_SEAL ){
goto noncfe;
}
#endif
/* Kernel arguments */
#ifdef CONFIG_MIPS_BRCM97XXX
/* For the 97xxx series STB, process CFE boot parms */
{
int i;
for (i=0; i<MAX_HWADDR; i++) {
gHwAddrs[i] = &privHwAddrs[i][0];
}
}
#ifdef CONFIG_TIVO_KONTIKI
res = get_cfe_boot_parms();
hasCfeParms = (res == 0);
#if 1 /* ###JLF */
if (gNumHwAddrs > 0)
{
printk("%s(): Got CFE MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x\n",
__FUNCTION__,
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5]);
}
#endif
#ifdef BRCM_MEMORY_STRAPS
get_RAM_size();
#else
if(brcm_dram0_size == 0)
brcm_dram0_size = probe_memsize();
#ifndef CONFIG_DISCONTIGMEM
if(brcm_dram0_size > (256 << 20)) {
printk("Extra RAM beyond 256MB ignored. Please "
"use a kernel that supports DISCONTIG.\n");
brcm_dram0_size = 256 << 20;
}
#endif /* CONFIG_DISCONTIGMEM */
#endif /* BRCM_MEMORY_STRAPS */
// Make sure cfeBootParms is not empty or contains all white space
if (hasCfeParms) {
int i;
hasCfeParms = 0;
for (i=0; i < strlen(cfeBootParms); i++) {
if (isspace(cfeBootParms[i])) {
continue;
}
else if (cfeBootParms[i] == '\0') {
break; // and leave hasCfeParms false
}
else {
hasCfeParms = 1;
break;
}
}
}
#else /* if !defined(CONFIG_TIVO_KONTIKI) */
res = get_cfe_boot_parms(cfeBootParms, &gNumHwAddrs, gHwAddrs);
if(gNumHwAddrs <= 0) {
#if !defined(CONFIG_BRCM_PCI_SLAVE)
unsigned int i, mac = FLASH_MACADDR_ADDR, ok = 0;
for(i = 0; i < 3; i++) {
u16 word = readw((void *)mac);
if(word != 0x0000 && word != 0xffff)
ok = 1;
gHwAddrs[0][(i << 1)] = word & 0xff;
gHwAddrs[0][(i << 1) + 1] = word >> 8;
mac += 2;
}
/* display warning for all 00's, all ff's, or multicast */
if(! ok || (gHwAddrs[0][1] & 1)) {
printk(KERN_WARNING
"WARNING: read invalid MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x from flash @ 0x%08x\n",
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5],
FLASH_MACADDR_ADDR);
}
#else
/* PCI slave mode - no EBI/flash available */
u8 fixed_macaddr[] = { 0x00, 0xc0, 0xa8, 0x74, 0x3b, 0x51 };
memcpy(&gHwAddrs[0][0], fixed_macaddr, sizeof(fixed_macaddr));
#endif
gNumHwAddrs = 1;
}
void prom_putchar(char x)
{
while (!(BDEV_RD(UART_REG(UART_LSR)) & UART_LSR_THRE))
;
BDEV_WR(UART_REG(UART_TX), x);
}
void __init prom_init(void)
{
#ifdef CONFIG_MIPS_BRCM97XXX
int hasCfeParms = 0;
int res = -1;
extern void determineBootFromFlashOrRom(void);
#endif
uart_init(27000000);
/* jipeng - mask out UPG L2 interrupt here */
BDEV_WR(BCHP_IRQ0_IRQEN, 0);
board_pinmux_setup();
/* Fill in platform information */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BRCM_STB;
#ifdef BRCM_SATA_SUPPORTED
brcm_sata_enabled = 1;
#endif
#ifdef BRCM_ENET_SUPPORTED
brcm_enet_enabled = 1;
#endif
#ifdef BRCM_EMAC_1_SUPPORTED
brcm_emac_1_enabled = 1;
#endif
#ifdef BRCM_PCI_SUPPORTED
brcm_pci_enabled = 1;
#endif
#ifdef CONFIG_SMP
brcm_smp_enabled = 1;
#endif
#ifdef CONFIG_MIPS_BCM7118
/* detect 7118RNG board */
if( BDEV_RD(BCHP_CLKGEN_REG_START) == 0x1c )
brcm_sata_enabled = 0;
/* onchip DOCSIS owns the ENET */
brcm_enet_enabled = 0;
#endif
#ifdef CONFIG_MIPS_BCM7405
/* detect 7406 */
if(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) &
BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_sata_disable_MASK)
brcm_sata_enabled = 0;
switch(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) & 0xf) {
case 0x0:
/* 7405/7406 */
break;
case 0x1:
/* 7466 */
brcm_pci_enabled = 0;
brcm_emac_1_enabled = 0;
break;
case 0x3:
/* 7106 */
brcm_emac_1_enabled = 0;
brcm_smp_enabled = 0;
break;
case 0x4:
case 0x6:
/* 7205/7213 */
brcm_emac_1_enabled = 0;
break;
}
#endif
#if defined(CONFIG_BMIPS3300)
// Set BIU to async mode
set_c0_brcm_bus_pll(1 << 22);
// Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT)
BDEV_WR(0x0000040c, 0x264);
// Enable Split Mode (BCHP_MISB_BRIDGE_MISB_SPLIT_MODE)
BDEV_WR(0x00000410, 0x1);
#endif
/* Kernel arguments */
#ifdef CONFIG_MIPS_BRCM97XXX
/* For the 97xxx series STB, process CFE boot parms */
{
int i;
for (i=0; i<MAX_HWADDR; i++) {
gHwAddrs[i] = &privHwAddrs[i][0];
}
}
res = get_cfe_boot_parms();
hasCfeParms = (res == 0);
#ifdef BRCM_MEMORY_STRAPS
get_RAM_size();
#else
if(brcm_dram0_size == 0)
brcm_dram0_size = probe_memsize();
#ifndef CONFIG_DISCONTIGMEM
if(brcm_dram0_size > (256 << 20)) {
printk("Extra RAM beyond 256MB ignored. Please "
"use a kernel that supports DISCONTIG.\n");
brcm_dram0_size = 256 << 20;
}
#endif /* CONFIG_DISCONTIGMEM */
#endif /* BRCM_MEMORY_STRAPS */
if(gNumHwAddrs <= 0) {
#if !defined(CONFIG_BRCM_PCI_SLAVE)
unsigned int i, mac = FLASH_MACADDR_ADDR, ok = 0;
for(i = 0; i < 3; i++) {
u16 word = readw((void *)mac);
if(word != 0x0000 && word != 0xffff)
ok = 1;
gHwAddrs[0][(i << 1)] = word & 0xff;
gHwAddrs[0][(i << 1) + 1] = word >> 8;
mac += 2;
}
/* display warning for all 00's, all ff's, or multicast */
if(! ok || (gHwAddrs[0][0] & 1)) {
u8 fixed_macaddr[] = { 0x00,0x00,0xde,0xad,0xbe,0xef };
printk(KERN_WARNING
"WARNING: read invalid MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x from flash @ 0x%08x\n",
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5],
FLASH_MACADDR_ADDR);
memcpy(&gHwAddrs[0][0], fixed_macaddr,
sizeof(fixed_macaddr));
}
#else
/* PCI slave mode - no EBI/flash available */
u8 fixed_macaddr[] = { 0x00, 0xc0, 0xa8, 0x74, 0x3b, 0x51 };
memcpy(&gHwAddrs[0][0], fixed_macaddr, sizeof(fixed_macaddr));
#endif
gNumHwAddrs = 1;
}
