Ejemplo n.º 1
0
static void __brcm_pm_memc1_suspend(int mode)
{
	DBG(KERN_DEBUG "%s %d\n", __func__, mode);

	memc1_config.shmoo_valid = 1;

	/* power down the pads */
	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
		IDDQ_MODE_ON_SELFREF, 0);
	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
		PHY_IDLE_ENABLE, 1);
	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
		HIZ_ON_SELFREF, 1);
	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL,
		0x132);
	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL,
		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL) |
			0xFFFFF);
	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL,
		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL) |
			0xFFFFF);

	/* enter SSPD */
	brcm_pm_memc1_sspd_control(1);

	/* power down the PLLs */
	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel,
		PWRDN, 1);
	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG, 3);

	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY,
		DDR1_POWER_SWITCH_MEMORY, 3);
	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE,
		DDR1_MEMORY_STANDBY_ENABLE, 1);

#if defined(BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT)
	BDEV_WR_F_RB(CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT,
		MEMSYS_PLL_PWRDN_POWER_MANAGEMENT, 1);
#endif

	if (mode) {
		DBG(KERN_DEBUG "%s reset\n", __func__);
		BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_DRAM_INIT, 1);
		BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_CORE, 1);
		BDEV_WR_F_RB(MEMC_DDR_1_DRAM_INIT_CNTRL, DDR3_INIT_MODE, 1);
		mdelay(1);
	} else
		DBG(KERN_DEBUG "%s suspended\n", __func__);

	memc1_config.valid = 1;
}
Ejemplo n.º 2
0
static void __brcm_pm_memc1_resume(int mode)
{
	DBG(KERN_DEBUG "%s %d\n", __func__, mode);

	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_SYS_PLL_PWRDN_ref_clk_sel,
		PWRDN, 0);
	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_PLL_CONFIG, 0);

	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY,
		DDR1_POWER_SWITCH_MEMORY, 2);
	mdelay(1);
	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY,
		DDR1_POWER_SWITCH_MEMORY, 0);

	BDEV_WR_F_RB(CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE,
		DDR1_MEMORY_STANDBY_ENABLE, 0);
#if defined(BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT)
	BDEV_WR_F_RB(CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT,
		MEMSYS_PLL_PWRDN_POWER_MANAGEMENT, 0);
#endif

	/* power up the pads */
	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
		IDDQ_MODE_ON_SELFREF, 0);
	BDEV_WR_F_RB(MEMC_DDR23_SHIM_ADDR_CNTL_1_DDR_PAD_CNTRL,
		HIZ_ON_SELFREF, 0);
	BDEV_WR_RB(BCHP_DDR40_PHY_CONTROL_REGS_1_IDLE_PAD_CONTROL,
		0);
	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL,
		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_0_1_IDLE_PAD_CONTROL) |
			0);
	BDEV_WR_RB(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL,
		BDEV_RD(BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL) |
			0);

	brcm_pm_memc1_sspd_control(0);

	if (mode) {
		BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_DRAM_INIT, 0);
		BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET, MEMC_CORE, 0);
		mdelay(1);
		printk(KERN_DEBUG "memc1: powered up\n");
	} else
		printk(KERN_DEBUG "memc1: resumed\n");
}
Ejemplo n.º 3
0
static void brcm_pm_memc1_arb_params(int restore)
{
	int ii = 0;

	if (restore) {
		BDEV_WR_RB(BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD,
			memc1_config.arb_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE,
			memc1_config.arb_params[ii++]);
	} else {
		memc1_config.arb_params[ii++] =
			BDEV_RD(BCHP_MEMC_ARB_1_FULLNESS_THRESHOLD);
		memc1_config.arb_params[ii++] =
			BDEV_RD(BCHP_MEMC_ARB_1_MINIMUM_COMMAND_SIZE);
	}

	BUG_ON(ii > MAX_ARB_PARAMS_NUM);
}
Ejemplo n.º 4
0
/***********************************************************************
 * Map the descriptors and write the first descriptor address to the
 * M2M register. Do not initiate transfer yet.
 ***********************************************************************/
static dma_addr_t brcm_mem_dma_prepare_descriptors(
	struct brcm_mem_dma_descr *d, int size)
{
	dma_addr_t pa_d;
	pa_d = dma_map_single(NULL, d, size, DMA_TO_DEVICE);
	brcm_mem_dma_wait_for_ready(0);
	BDEV_WR_RB(BCHP_MEM_DMA_0_FIRST_DESC, pa_d);

	return pa_d;
}
Ejemplo n.º 5
0
static void brcm_pm_memc1_client_info(int restore)
{
	int ii = 0;
	u32 addr = BCHP_MEMC_ARB_1_REG_START + 4;

	if (restore)
		for (ii = 0; ii < MAX_CLIENT_INFO_NUM; ii++) {
			BDEV_WR_RB(addr, memc1_config.client_info[ii]);
			addr += 4;
		}
	else
		/* Save MEMC1 configuration */
		for (ii = 0; ii < MAX_CLIENT_INFO_NUM; ii++) {
			memc1_config.client_info[ii] = BDEV_RD(addr);
			addr += 4;
		}
}
Ejemplo n.º 6
0
static int __brcm_pm_memc1_powerup(void)
{
	int ii = 0;

	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG,
		memc1_config.ddr23_aphy_params[ii++]);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL,
		memc1_config.ddr23_aphy_params[ii++]);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_CONFIG,
		memc1_config.ddr23_aphy_params[ii++]);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PAD_SSTL_DDR2_MODE,
		memc1_config.ddr23_aphy_params[ii++]);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_PAD_SSTL_DDR2_MODE,
		memc1_config.ddr23_aphy_params[ii++]);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_PAD_SSTL_DDR2_MODE,
		memc1_config.ddr23_aphy_params[ii++]);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG,
		memc1_config.ddr23_aphy_params[ii++]);

	return 0;
}
Ejemplo n.º 7
0
static void brcm_pm_memc1_ddr_params(int restore)
{
	int ii = 0;

	if (restore) {
		/* program ddr iobuf registers */
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_2,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_3,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_5,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_0,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_MODE_1,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_0,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_1,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_2,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_3,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_TIMING_4,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_CNTRLR_CONFIG,
			memc1_config.ddr_params[ii++]);
		BDEV_WR_RB(BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL,
			memc1_config.ddr_params[ii++]);
	} else {
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_2);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_3);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_5);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_0);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_MODE_1);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_0);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_1);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_2);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_3);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_TIMING_4);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_CNTRLR_CONFIG);
		memc1_config.ddr_params[ii++] =
			BDEV_RD(BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL);
	}
	BUG_ON(ii > MAX_DDR_PARAMS_NUM);
}
Ejemplo n.º 8
0
static void __brcm_pm_memc1_resume(int mode)
{
	u32 val, cur_val;
	s32 sval, scur_val, inc_val;

	DBG(KERN_DEBUG "%s %d\n", __func__, mode);

	/* power up LDOs */
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG,
		LDO_PWRDN, 0);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_WORDSLICE_CNTRL_1,
		LDO_PWRDN, 0);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_WORDSLICE_CNTRL_1,
		LDO_PWRDN, 0);

	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL, 0);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL, 0);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL, 0);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL, 0);

	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL, 0);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL, 0);

	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL, 0);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL, BYPASS_PHASE, 0);

	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_DDR_PAD_CNTRL,
		IDDQ_MODE_ON_SELFREF, 0);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_DDR_PAD_CNTRL,
		IDDQ_MODE_ON_SELFREF, 0);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_WORDSLICE_CNTRL_1,
		PWRDN_DLL_ON_SELFREF, 0);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_WORDSLICE_CNTRL_1,
		PWRDN_DLL_ON_SELFREF, 0);

	BDEV_UNSET(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
	BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK |
	BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK);
	mdelay(1);

	/* reset the freq divider */
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, FREQ_DIV_RESET, 1);
	mdelay(1);
	/* reset DATAPATH_216, RD_DATAPATH_RESET, RESET_DATAPATH_DDR  */
	BDEV_SET_RB(BCHP_MEMC_DDR23_APHY_AC_1_RESET,
		BCHP_MEMC_DDR23_APHY_AC_1_RESET_DATAPATH_216_RESET_MASK |
		BCHP_MEMC_DDR23_APHY_AC_1_RESET_RD_DATAPATH_RESET_MASK |
		BCHP_MEMC_DDR23_APHY_AC_1_RESET_DATAPATH_DDR_RESET_MASK);
	mdelay(1);
	/* reset the vcxo */
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, VCXO_RESET, 1);
	mdelay(1);
	/* de-assert reset the vcxo */
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, VCXO_RESET, 0);

	/* de-assert reset the freq divider */
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, FREQ_DIV_RESET, 0);
	mdelay(1);

	/* check for pll lock */
	while (!BDEV_RD_F(MEMC_DDR23_APHY_AC_1_DDR_PLL_LOCK_STATUS,
		LOCK_STATUS))
		;

	/* reload shmoo values */
	/* set wl0_dq phase */
	val = memc1_config.shmoo_value[4];
	cur_val = 0;
	while (cur_val <= val) {
		BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL,
			cur_val);
		cur_val++;
	}

	/* set wl1_dq phase */
	val = memc1_config.shmoo_value[5];
	cur_val = 0;
	while (cur_val <= val) {
		BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL,
			cur_val);
		cur_val++;
	}
	/* set ch2 phase */
	val = memc1_config.shmoo_value[6];
	cur_val = 0;
	while (cur_val < val) {
		BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL,
			cur_val);
		cur_val++;
	}

	/* set ch6 phase */
	val = memc1_config.shmoo_value[7];
	cur_val = 0;
	while (cur_val < val) {
		BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL,
			BYPASS_PHASE, cur_val);
		cur_val++;
	}

	/* set wl0_dqs0 phases */
	sval = memc1_config.shmoo_value[0];
	scur_val = 0;
	inc_val = sval > 0 ? 1 : -1;
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL,
		0);
	while (sval != scur_val) {
		scur_val += inc_val;
		BDEV_WR_RB(
			BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL,
			scur_val);
	}

	/* set wl0_dqs1 phases */
	sval = memc1_config.shmoo_value[1];
	scur_val = 0;
	inc_val = sval > 0 ? 1 : -1;
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL,
		0);
	while (sval != scur_val) {
		scur_val += inc_val;
		BDEV_WR_RB(
			BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL,
			scur_val);
	}

	/* set wl1_dqs0 phases */
	sval = memc1_config.shmoo_value[2];
	scur_val = 0;
	inc_val = sval > 0 ? 1 : -1;
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL,
		0);
	while (sval != scur_val) {
		scur_val += inc_val;
		BDEV_WR_RB(
			BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL,
			scur_val);
	}

	/* set wl1_dqs1 phases */
	sval = memc1_config.shmoo_value[3];
	scur_val = 0;
	inc_val = sval > 0 ? 1 : -1;
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL,
		0);
	while (sval != scur_val) {
		scur_val += inc_val;
		BDEV_WR_RB(
			BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL,
			scur_val);
	}

	/* reset the word slice dll */
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_WORD_SLICE_DLL_RESET, 1);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_WORD_SLICE_DLL_RESET, 1);
	mdelay(1);

	/* reset VCDL values */
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE0_VCDL_PHASE_CNTL, 0);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE1_VCDL_PHASE_CNTL, 0);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE0_VCDL_PHASE_CNTL, 0);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE1_VCDL_PHASE_CNTL, 0);

	/* de-assert reset of the word slice dll */
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_WORD_SLICE_DLL_RESET, 0);
	BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_WORD_SLICE_DLL_RESET, 0);
	mdelay(1);

	/* de-assert reset from DATAPATH_216_RESET */
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, DATAPATH_216_RESET, 0);
	/* de-assert reset from RD_DATAPATH_RESET */
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, RD_DATAPATH_RESET, 0);
	/* de-assert reset from DATAPATH_DDR_RESET */
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, DATAPATH_DDR_RESET, 0);
	mdelay(1);

	/*
	 * Reload VCDL values:
	 */
	cur_val = 0x0101;
	while (cur_val <= memc1_config.vcdl[0]) {
		BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE0_VCDL_PHASE_CNTL,
			cur_val);
		cur_val += 0x0101;
	}
	cur_val = 0x0101;
	while (cur_val <= memc1_config.vcdl[1]) {
		BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE1_VCDL_PHASE_CNTL,
			cur_val);
		cur_val += 0x0101;
	}
	cur_val = 0x0101;
	while (cur_val <= memc1_config.vcdl[2]) {
		BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE0_VCDL_PHASE_CNTL,
			cur_val);
		cur_val += 0x0101;
	}
	cur_val = 0x0101;
	while (cur_val <= memc1_config.vcdl[3]) {
		BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE1_VCDL_PHASE_CNTL,
			cur_val);
		cur_val += 0x0101;
	}

	if (mode) {
		/* Remove CKE_IDDQ */
		BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
			BDEV_RD(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL) & ~4);

		BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET,
			MEMC_DRAM_INIT, 0);
		BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET,
			MEMC_CORE, 0);
		mdelay(1);
		printk(KERN_DEBUG "memc1: powered up\n");
	} else
		printk(KERN_DEBUG "memc1: resumed\n");

}
Ejemplo n.º 9
0
static void __brcm_pm_memc1_suspend(int mode)
{
	DBG(KERN_DEBUG "%s %d\n", __func__, mode);

	if (!memc1_config.shmoo_valid) {
		memc1_config.shmoo_value[0] =
			BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA0);
		memc1_config.shmoo_value[1] =
			BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA1);
		memc1_config.shmoo_value[2] =
			BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA2);
		memc1_config.shmoo_value[3] =
			BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA3);
		memc1_config.shmoo_value[4] =
			BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA4);
		memc1_config.shmoo_value[5] =
			BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA5);
		memc1_config.shmoo_value[6] =
			BDEV_RD(BCHP_MEMC_GEN_1_MSA_WR_DATA6);
		memc1_config.shmoo_value[7] =
			BDEV_RD(BCHP_MEMC_MISC_1_SCRATCH_0);
		memc1_config.shmoo_valid = 1;
		DBG(KERN_DEBUG "%s: SHMOO values saved\n", __func__);
	}

	/* save VCDL values */
	memc1_config.vcdl[0] =
		BDEV_RD(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE0_VCDL_PHASE_CNTL);
	memc1_config.vcdl[1] =
		BDEV_RD(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE1_VCDL_PHASE_CNTL);
	memc1_config.vcdl[2] =
		BDEV_RD(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE0_VCDL_PHASE_CNTL);
	memc1_config.vcdl[3] =
		BDEV_RD(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE1_VCDL_PHASE_CNTL);

	/* MEMC1 */
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
		DEVCLK_OFF_ON_SELFREF, 1);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
		HIZ_ON_SELFREF, 1);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
		IDDQ_MODE_ON_SELFREF, 1);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_POWERDOWN,
		PLLCLKS_OFF_ON_SELFREF, 1);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_POWERDOWN,
		LOWPWR_EN, 1);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_DDR_PAD_CNTRL,
		IDDQ_MODE_ON_SELFREF, 1);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_DDR_PAD_CNTRL,
		IDDQ_MODE_ON_SELFREF, 1);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_WORDSLICE_CNTRL_1,
		PWRDN_DLL_ON_SELFREF, 1);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_WORDSLICE_CNTRL_1,
		PWRDN_DLL_ON_SELFREF, 1);

	brcm_pm_memc1_sspd_control(1);


	if (mode) {
		/* CKE_IDDQ */
		BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
			BDEV_RD(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL) | 4);

		BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET,
			MEMC_DRAM_INIT, 1);
		BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET,
			MEMC_CORE, 1);
		BDEV_WR_F_RB(MEMC_DDR_1_DRAM_INIT_CNTRL,
			DDR3_INIT_MODE, 1);
		mdelay(1);
		printk(KERN_DEBUG "memc1: powered down\n");
	} else
		printk(KERN_DEBUG "memc1: suspended\n");

	/* Power down LDOs */
	BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG,
		LDO_PWRDN, 1);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_WORDSLICE_CNTRL_1,
		LDO_PWRDN, 1);
	BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_WORDSLICE_CNTRL_1,
		LDO_PWRDN, 1);

}
Ejemplo n.º 10
0
void __init arch_init_irq(void)
{
	int irq;

	mips_cpu_irq_init();

	L1_WR_ALL(W0, MASK_SET, 0xffffffff);
	L1_WR_ALL(W1, MASK_SET, 0xffffffff);
	L1_WR_ALL(W2, MASK_SET, 0xffffffff);
	
	clear_c0_status(ST0_IE | ST0_IM);

	/* Set up all L1 IRQs */
	for (irq = 1; irq < BRCM_VIRTIRQ_BASE; irq++)
		set_irq_chip_and_handler(irq, &brcm_intc_type,
			handle_level_irq);

#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS)
	/* default affinity: 1 (TP0 only) */
	cpumask_clear(irq_default_affinity);
	cpumask_set_cpu(0, irq_default_affinity);
#endif

	/* enable IRQ2 (this runs on TP0).  IRQ3 enabled during TP1 boot. */
	set_c0_status(STATUSF_IP2);

#if ! defined(CONFIG_BRCM_SHARED_UART_IRQ)

	/* enable non-shared UART interrupts in the L2 */

#if defined(BCHP_IRQ0_UART_IRQEN_uarta_MASK)
	/* 3548 style - separate register */
	BDEV_WR(BCHP_IRQ0_UART_IRQEN, BCHP_IRQ0_UART_IRQEN_uarta_MASK |
		BCHP_IRQ0_UART_IRQEN_uartb_MASK |
		BCHP_IRQ0_UART_IRQEN_uartc_MASK);
	BDEV_WR(BCHP_IRQ0_IRQEN, 0);
#elif defined(BCHP_IRQ0_IRQEN_uarta_irqen_MASK)
	/* 7405 style - shared with L2 */
	BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
		| BCHP_IRQ0_IRQEN_uartb_irqen_MASK
#if defined(BCHP_IRQ0_IRQEN_uartc_irqen_MASK)
		| BCHP_IRQ0_IRQEN_uartc_irqen_MASK
#endif
		);
#endif

#if defined(CONFIG_BRCM_HAS_PCU_UARTS)
	BDEV_WR(BCHP_TVM_MAIN_INT_CNTL, 0);
	BDEV_WR_F(TVM_MAIN_INT_CNTL, MAIN_UART1_INT_EN, 1);
#endif

#else /* CONFIG_BRCM_SHARED_UART_IRQ */

	/* Set up all UPG L2 interrupts */

	BDEV_WR_RB(BCHP_IRQ0_IRQEN, 0);
	for (irq = BRCM_UPG_L2_BASE; irq <= BRCM_UPG_L2_LAST; irq++)
		set_irq_chip_and_handler(irq, &brcm_upg_type, handle_level_irq);

#endif /* CONFIG_BRCM_SHARED_UART_IRQ */

#if defined(BCHP_HIF_INTR2_CPU_MASK_SET)
	/* mask and clear all HIF L2 interrupts */
	BDEV_WR_RB(BCHP_HIF_INTR2_CPU_MASK_SET, 0xffffffff);
	BDEV_WR_RB(BCHP_HIF_INTR2_CPU_CLEAR, 0xffffffff);
#endif
}