static inline void stmi2c_clear_pending_interrupts(I2C_TypeDef *regs)
{
uint16_t SR1 = regs->SR1;
regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN; // Disable TXE, RXNE
// Start Condition Was Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
{
// SB: cleared by software when reading SR1 and writing to DR
regs->DR = 0x00;
}
// Address Was Sent
if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
{
// ADDR: Cleared by software when reading SR1 and then SR2
uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
}
// Byte Transfer Finished
if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
{
// SB: cleared by software when reading SR1 and reading/writing to DR
uint8_t dummy __attribute__ ((unused)) = regs->DR;
regs->DR = 0x00;
}
}
static inline void stmi2c_clear_pending_interrupts(uint32_t i2c)
{
uint16_t SR1 = I2C_SR1(i2c);
// Certainly do not wait for buffer interrupts:
// -------------------------------------------
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN); // Disable TXE, RXNE
// Error interrupts are handled separately:
// ---------------------------------------
// Clear Event interrupt conditions:
// --------------------------------
// Start Condition Was Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
{
// SB: cleared by software when reading SR1 and writing to DR
i2c_send_data(i2c, 0x00);
}
// Address Was Sent
if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
{
// ADDR: Cleared by software when reading SR1 and then SR2
uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
}
// Byte Transfer Finished
if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
{
// SB: cleared by software when reading SR1 and reading/writing to DR
uint8_t dummy __attribute__ ((unused)) = i2c_get_data(i2c);
i2c_send_data(i2c, 0x00);
}
}
// Doc ID 13902 Rev 11 p 714/1072
// Transfer Sequence Diagram for Master Receiver for N=1
static inline enum STMI2CSubTransactionStatus stmi2c_read1(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
{
uint16_t SR1 = I2C_SR1(i2c);
// Start Condition Was Just Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
{
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
i2c_send_data(i2c, trans->slave_addr | 0x01);
// Document the current Status
periph->status = I2CAddrRdSent;
}
// Address Was Sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
{
// First Clear the ACK bit: after the next byte we do not want new bytes
i2c_nack_current(i2c);
i2c_disable_ack(i2c);
// --- next to steps MUST be executed together to avoid missing the stop
__I2C_REG_CRITICAL_ZONE_START;
// Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
// Schedule a Stop
PPRZ_I2C_SEND_STOP(i2c);
__I2C_REG_CRITICAL_ZONE_STOP;
// --- end of critical zone -----------
// Enable the RXNE: it will trigger as soon as the 1 byte is received to get the result
i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
// Document the current Status
periph->status = I2CReadingLastByte;
}
// As soon as there is 1 byte ready to read, we have our byte
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1) )
{
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
trans->buf[0] = I2C_DR(i2c);
// We got all the results (stop condition might still be in progress but this is the last interrupt)
trans->status = I2CTransSuccess;
// Document the current Status:
// -the stop was actually already requested in the previous step
periph->status = I2CStopRequested;
return STMI2C_SubTra_Ready_StopRequested;
}
else // Event Logic Error
{
return STMI2C_SubTra_Error;
}
return STMI2C_SubTra_Busy;
}
static inline enum STMI2CSubTransactionStatus stmi2c_read2(I2C_TypeDef *regs, struct i2c_transaction *trans)
{
uint16_t SR1 = regs->SR1;
// Start Condition Was Just Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
{
regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
regs->CR1 |= I2C_CR1_BIT_ACK;
regs->CR1 |= I2C_CR1_BIT_POS;
regs->DR = trans->slave_addr | 0x01;
}
// Address Was Sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
{
// BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
// clearing ACK after the byte transfer has already started will NACK the next (2nd)
uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
// --- make absolutely sure this command is not delayed too much after the previous:
__I2C_REG_CRITICAL_ZONE_START;
// if transfer of DR was finished already then we will get too many bytes
// NOT First Clear the ACK bit but only AFTER clearing ADDR
regs->CR1 &= ~ I2C_CR1_BIT_ACK;
// Disable the RXNE and wait for BTF
regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
__I2C_REG_CRITICAL_ZONE_STOP;
// --- end of critical zone -----------
}
// Receive buffer if full, master is halted: BTF
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
{
// Stop condition MUST be set BEFORE reading the DR
// otherwise since there is new buffer space a new byte will be read
PPRZ_I2C_SEND_STOP(regs);
trans->buf[0] = regs->DR;
trans->buf[1] = regs->DR;
// We got all the results
trans->status = I2CTransSuccess;
return STMI2C_SubTra_Ready_StopRequested;
}
else // Hardware error
{
return STMI2C_SubTra_Error;
}
return STMI2C_SubTra_Busy;
}
static inline enum STMI2CSubTransactionStatus stmi2c_read1(I2C_TypeDef *regs, struct i2c_transaction *trans)
{
uint16_t SR1 = regs->SR1;
// Start Condition Was Just Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
{
regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
regs->DR = trans->slave_addr | 0x01;
}
// Address Was Sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
{
// First Clear the ACK bit: after the next byte we do not want new bytes
regs->CR1 &= ~ I2C_CR1_BIT_POS;
regs->CR1 &= ~ I2C_CR1_BIT_ACK;
// --- next to steps MUST be executed together to avoid missing the stop
__I2C_REG_CRITICAL_ZONE_START;
// Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
// Schedule a Stop
PPRZ_I2C_SEND_STOP(regs);
__I2C_REG_CRITICAL_ZONE_STOP;
// --- end of critical zone -----------
// Enable the RXNE to get the result
regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
}
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_RXNE, SR1) )
{
regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
trans->buf[0] = regs->DR;
// We got all the results (stop condition might still be in progress but this is the last interrupt)
trans->status = I2CTransSuccess;
return STMI2C_SubTra_Ready_StopRequested;
}
else // Hardware error
{
return STMI2C_SubTra_Error;
}
return STMI2C_SubTra_Busy;
}
bool_t i2c_idle(struct i2c_periph* periph)
{
I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
#ifdef I2C_DEBUG_LED
if (periph == &i2c1)
{
return TRUE;
}
#endif
if (periph->status == I2CIdle)
return ! (BIT_X_IS_SET_IN_REG( I2C_SR2_BIT_BUSY, regs->SR2 ) );
else
return FALSE;
}
bool_t i2c_idle(struct i2c_periph* periph)
{
// This is actually a difficult function:
// -simply reading the status flags can clear bits and corrupt the transaction
uint32_t i2c = (uint32_t) periph->reg_addr;
#ifdef I2C_DEBUG_LED
#if USE_I2C1
if (periph == &i2c1)
{
return TRUE;
}
#endif
#endif
// First we check if the software thinks it is ready
if (periph->status == I2CIdle)
return ! (BIT_X_IS_SET_IN_REG( I2C_SR2_BUSY, I2C_SR2(i2c) ) );
else
return FALSE;
}
static inline enum STMI2CSubTransactionStatus stmi2c_readmany(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
{
uint16_t SR1 = regs->SR1;
// Start Condition Was Just Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
{
regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
// The first data byte will be acked in read many so the slave knows it should send more
regs->CR1 &= ~ I2C_CR1_BIT_POS;
regs->CR1 |= I2C_CR1_BIT_ACK;
// Clear the SB flag
regs->DR = trans->slave_addr | 0x01;
}
// Address Was Sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
{
periph->idx_buf = 0;
// Enable RXNE: receive an interrupt any time a byte is available
// only enable if MORE than 3 bytes need to be read
if (periph->idx_buf < (trans->len_r - 3))
{
regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
}
// ACK is still on to get more DATA
// Read SR2 to clear the ADDR (next byte will start arriving)
uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
}
// one or more bytes are available AND we were interested in Buffer interrupts
else if ( (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_RXNE, SR1) ) && (BIT_X_IS_SET_IN_REG(I2C_CR2_BIT_ITBUFEN, regs->CR2)) )
{
// read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
if (periph->idx_buf < (trans->len_r - 3))
{
trans->buf[periph->idx_buf] = regs->DR;
periph->idx_buf ++;
}
// from : 3bytes -> last byte: do nothing
//
// finally: this was the last byte
else if (periph->idx_buf >= (trans->len_r - 1))
{
regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
// Last Value
trans->buf[periph->idx_buf] = regs->DR;
periph->idx_buf ++;
// We got all the results
trans->status = I2CTransSuccess;
return STMI2C_SubTra_Ready_StopRequested;
}
// Check for end of transaction: start waiting for BTF instead of RXNE
if (periph->idx_buf < (trans->len_r - 3))
{
regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
}
else // idx >= len-3: there are 3 bytes to be read
{
// We want to halt I2C to have sufficient time to clear ACK, so:
// Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
// on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
}
}
// Buffer is full while this was not a RXNE interrupt
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
{
// Now the shift register and data register contain data(n-2) and data(n-1)
// And I2C is halted so we have time
// --- Make absolutely sure the next 2 I2C actions are performed with no delay
__I2C_REG_CRITICAL_ZONE_START;
// First we clear the ACK while the SCL is held low by BTF
regs->CR1 &= ~ I2C_CR1_BIT_ACK;
// Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
trans->buf[periph->idx_buf] = regs->DR;
periph->idx_buf ++;
// Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
PPRZ_I2C_SEND_STOP(regs);
__I2C_REG_CRITICAL_ZONE_STOP;
// --- end of critical zone -----------
// read the byte2 we had in the buffer (BTF means 2 bytes available)
trans->buf[periph->idx_buf] = regs->DR;
periph->idx_buf ++;
// Ask for an interrupt to read the last byte (which is normally still busy now)
// The last byte will be received with RXNE
regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
}
else // Hardware error
{
// Error
#ifdef I2C_DEBUG_LED
LED2_ON();
LED1_ON();
LED2_OFF();
LED1_OFF();
#endif
return STMI2C_SubTra_Error;
}
return STMI2C_SubTra_Busy;
}
static inline enum STMI2CSubTransactionStatus stmi2c_send(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
{
uint16_t SR1 = regs->SR1;
// Start Condition Was Just Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
{
// Disable buffer interrupt
regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
// Send Slave address and wait for ADDR interrupt
regs->DR = trans->slave_addr;
}
// Address Was Sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
{
// Now read SR2 to clear the ADDR
uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
// Maybe check we are transmitting (did not loose arbitration for instance)
// if (! BIT_X_IS_SET_IN_REG(I2C_SR2_BIT_TRA, SR2)) { }
// Send First max 2 bytes
regs->DR = trans->buf[0];
if (trans->len_w > 1)
{
regs->DR = trans->buf[1];
periph->idx_buf = 2;
}
else
{
periph->idx_buf = 1;
}
// Enable buffer-space available interrupt
// only if there is more to send: wait for TXE, no more to send: wait for BTF
if ( periph->idx_buf < trans->len_w)
regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
}
// The buffer is not full anymore AND we were not waiting for BTF
else if ((BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_TXE, SR1) ) && (BIT_X_IS_SET_IN_REG(I2C_CR2_BIT_ITBUFEN, regs->CR2)) )
{
// Send the next byte
regs->DR = trans->buf[periph->idx_buf];
periph->idx_buf++;
// All bytes Sent? Then wait for BTF instead
if ( periph->idx_buf >= trans->len_w)
{
// Not interested anymore to know the buffer has space left
regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
// Next interrupt will be BTF (or error)
}
}
// BTF: means last byte was sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
{
if (trans->type == I2CTransTx)
{
// Tell the driver we are ready
trans->status = I2CTransSuccess;
}
return STMI2C_SubTra_Ready;
}
else // Hardware error
{
return STMI2C_SubTra_Error;
}
return STMI2C_SubTra_Busy;
}
static inline void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
{
uint16_t CR1 = regs->CR1;
uint16_t SR1 = regs->SR1;
uint16_t SR2 = regs->SR2;
// Note: reading SR1 and then SR2 will clear ADDR bits
LED1_ON();
// 1 Start
if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
LED2_ON();
else
LED2_OFF();
LED2_OFF();
// 2 Addr
if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_ADDR, SR1 ) )
LED2_ON();
else
LED2_OFF();
LED2_OFF();
// 3 BTF
if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_BTF, SR1 ) )
LED2_ON();
else
LED2_OFF();
LED2_OFF();
// 4 ERROR
if (( SR1 & I2C_SR1_BITS_ERR ) != 0x0000)
LED2_ON();
else
LED2_OFF();
LED2_OFF();
// Anything?
if (( SR1 + SR2) != 0x0000)
LED2_ON();
else
LED2_OFF();
LED2_OFF();
LED1_OFF();
LED1_ON();
// 1 Start
if (BIT_X_IS_SET_IN_REG( I2C_CR1_BIT_START, CR1 ) )
LED2_ON();
else
LED2_OFF();
LED2_OFF();
// 2 Stop
if (BIT_X_IS_SET_IN_REG( I2C_CR1_BIT_STOP, CR1 ) )
LED2_ON();
else
LED2_OFF();
LED2_OFF();
// 3 Busy
if (BIT_X_IS_SET_IN_REG( I2C_SR2_BIT_BUSY, SR2 ) )
LED2_ON();
else
LED2_OFF();
LED2_OFF();
// 4 Tra
if (BIT_X_IS_SET_IN_REG( I2C_SR2_BIT_TRA, SR2 ) )
LED2_ON();
else
LED2_OFF();
LED2_OFF();
// 5 Master
if (BIT_X_IS_SET_IN_REG( I2C_SR2_BIT_MSL, SR2 ) )
LED2_ON();
else
LED2_OFF();
LED2_OFF();
LED1_OFF();
//#define I2C_DEBUG_LED_CONTROL
#ifdef I2C_DEBUG_LED_CONTROL
LED1_ON();
// 1 Anything CR?
if (( CR1) != 0x0000)
LED2_ON();
else
LED2_OFF();
LED2_OFF();
// 2 PE
if (BIT_X_IS_SET_IN_REG( I2C_CR1_BIT_PE, CR1 ) )
LED2_ON();
else
LED2_OFF();
LED2_OFF();
// 3 SWRESET
if (BIT_X_IS_SET_IN_REG( I2C_CR1_BIT_SWRST, CR1 ) )
LED2_ON();
else
LED2_OFF();
LED2_OFF();
LED1_OFF();
#endif
}
// Doc ID 13902 Rev 11 p 713/1072
// Transfer Sequence Diagram for Master Receiver for N=2
static inline enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
{
uint16_t SR1 = I2C_SR1(i2c);
// Start Condition Was Just Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
{
// according to the datasheet: instantly shedule a NAK on the second received byte:
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
i2c_enable_ack(i2c);
i2c_nack_next(i2c);
i2c_send_data(i2c, trans->slave_addr | 0x01);
// Document the current Status
periph->status = I2CAddrRdSent;
}
// Address Was Sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
{
// --- make absolutely sure this command is not delayed too much after the previous:
// --- the NAK bits must be set before the first byte arrived: allow other interrupts here
__I2C_REG_CRITICAL_ZONE_START;
// if transfer of DR was finished already then we will get too many bytes
// BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
// clearing ACK after the byte transfer has already started will NACK the next (2nd)
uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
// NOT First Clear the ACK bit but only AFTER clearing ADDR
i2c_disable_ack(i2c);
// Disable the RXNE and wait for BTF
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
__I2C_REG_CRITICAL_ZONE_STOP;
// --- end of critical zone -----------
// We do not set the RxE but wait for both bytes to arrive using BTF
// Document the current Status
periph->status = I2CReadingByte;
}
// Receive buffer if full, master is halted: BTF
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
{
// Stop condition MUST be set BEFORE reading the DR
// otherwise since there is new buffer space a new byte will be read
PPRZ_I2C_SEND_STOP(i2c);
// Document the current Status
periph->status = I2CStopRequested;
trans->buf[0] = I2C_DR(i2c);
trans->buf[1] = I2C_DR(i2c);
// We got all the results
trans->status = I2CTransSuccess;
return STMI2C_SubTra_Ready_StopRequested;
}
else // Event Logic Error
{
return STMI2C_SubTra_Error;
}
return STMI2C_SubTra_Busy;
}
// Doc ID 13902 Rev 11 p 710/1072
// Transfer Sequence Diagram for Master Transmitter
static inline enum STMI2CSubTransactionStatus stmi2c_send(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
{
uint16_t SR1 = I2C_SR1(i2c);
// Start Condition Was Just Generated
if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
{
// Disable buffer interrupt
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
// Send Slave address and wait for ADDR interrupt
i2c_send_data(i2c, trans->slave_addr);
// Document the current Status
periph->status = I2CAddrWrSent;
}
// Address Was Sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
{
// Now read SR2 to clear the ADDR status Bit
uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
// Maybe check we are transmitting (did not loose arbitration for instance)
// if (! BIT_X_IS_SET_IN_REG(I2C_SR2_TRA, SR2)) { }
// update: this should be caught by the ARLO error: so we will not arrive here
// Send First max 2 bytes
i2c_send_data(i2c, trans->buf[0]);
if (trans->len_w > 1)
{
i2c_send_data(i2c, trans->buf[1]);
periph->idx_buf = 2;
}
else
{
periph->idx_buf = 1;
}
// Enable buffer-space available interrupt
// only if there is more to send: wait for TXE, no more to send: wait for BTF
if ( periph->idx_buf < trans->len_w)
i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
// Document the current Status
periph->status = I2CSendingByte;
}
// The buffer is not full anymore AND we were not waiting for BTF
else if ((BIT_X_IS_SET_IN_REG(I2C_SR1_TxE, SR1) ) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c))) )
{
// Send the next byte
i2c_send_data(i2c, trans->buf[periph->idx_buf]);
periph->idx_buf++;
// All bytes Sent? Then wait for BTF instead
if ( periph->idx_buf >= trans->len_w)
{
// Not interested anymore to know the buffer has space left
i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
// Next interrupt will be BTF (or error)
}
}
// BTF: means last byte was sent
else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
{
if (trans->type == I2CTransTx)
{
// Tell the driver we are ready
trans->status = I2CTransSuccess;
}
// Otherwise we still need to do the receiving part
return STMI2C_SubTra_Ready;
}
else // Event Logic Error
{
return STMI2C_SubTra_Error;
}
return STMI2C_SubTra_Busy;
}
