Ejemplo n.º 1
0
//!  Target power has been externally cycled. Holds BKPT/BKGD low while Vdd rises
//!
//! @return
//!    \ref BDM_RC_OK                 => Success           \n
//!    \ref BDM_RC_VDD_NOT_PRESENT    => various errors
//      
U8 bdmCF_powerOnReset(void) {
U8 rc = 0;

#if (HW_CAPABILITY&CAP_VDDSENSE)
   bdmcf_interfaceIdle();  // Make sure BDM interface is idle
   BKPT_LOW();

   // Wait for Vdd to rise within 50% of 3V and RESET to return high
   // RESET rise may be delayed by target POR
   WAIT_WITH_TIMEOUT_MS( 250 /* ms */, (bdm_targetVddMeasure()>75)&&
                                     (!bdm_option.useResetSignal)||RESET_IS_HIGH);

   // Let signals settle & CPU to finish reset (with BKGD held low)
   WAIT_MS(BKGD_WAITus);

   if (bdm_targetVddMeasure()<=70) // Vpp didn't turn on!
      rc = BDM_RC_VDD_NOT_PRESENT;

   if (bdm_option.useResetSignal && (!RESET_IS_HIGH)) // RESET didn't rise
      rc = BDM_RC_RESET_TIMEOUT_RISE;

   bdmcf_interfaceIdle();  // Make sure BDM interface is idle (BKGD now high)

   // Let signals settle
   WAIT_MS(RESET_SETTLEms);

   cable_status.reset = RESET_DETECTED;    // Record the fact that reset was asserted

#endif // (HW_CAPABILITY&CAP_VDDSENSE)
   return(rc);
}
Ejemplo n.º 2
0
//!  Cycle power ON to target
//!
//! @param mode
//!    - \ref RESET_SPECIAL => Power on in special mode,
//!    - \ref RESET_NORMAL  => Power on in normal mode
//!
//!  BKGD/BKPT is held low when power is re-applied to start
//!  target with BDM active if RESET_SPECIAL
//!
//!  @return
//!   \ref BDM_RC_OK                	=> Target Vdd confirmed on target \n
//!   \ref BDM_RC_VDD_WRONG_MODE    	=> Target Vdd not controlled by BDM interface \n
//!   \ref BDM_RC_VDD_NOT_PRESENT   	=> Target Vdd failed to rise 		\n
//!   \ref BDM_RC_RESET_TIMEOUT_RISE    => RESET signal failed to rise 		\n
//!   \ref BDM_RC_BKGD_TIMEOUT      	=> BKGD signal failed to rise
//!
uint8_t bdm_cycleTargetVddOn(uint8_t mode) {
uint8_t rc = BDM_RC_OK;

   mode &= RESET_MODE_MASK;

#if (HW_CAPABILITY&CAP_VDDCONTROL)

   switch(cable_status.target_type) {
#if (HW_CAPABILITY&CAP_CFVx_HW)
   case T_CFVx:
      bdmcf_interfaceIdle();  // Make sure BDM interface is idle
      if (mode == RESET_SPECIAL)
         BKPT_LOW();
      break;
#endif
#if (HW_CAPABILITY&CAP_BDM)     
   case T_HC12:
   case T_HCS08:
   case T_RS08:
   case T_CFV1:
      bdmHCS_interfaceIdle();  // Make sure BDM interface is idle
      if (mode == RESET_SPECIAL) {
         BDM_LOW();  // BKGD pin=L
      }
      break;
#endif      
#if (HW_CAPABILITY&CAP_JTAG_HW)     
   case T_JTAG:
   case T_MC56F80xx:
   case T_ARM_JTAG:
      jtag_interfaceIdle();  // Make sure BDM interface is idle
#endif      
      break;
   default:
      swd_interfaceIdle();
      break;
   }
#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN     = 0;
   DEBUG_PIN     = 1;
   DEBUG_PIN     = 0;
   DEBUG_PIN     = 1;
#endif //  (DEBUG&CYCLE_DEBUG)

   // Power on with TargetVdd monitoring off
   rc = bdm_setTargetVdd();
   if (rc != BDM_RC_OK) // No target Vdd
      goto cleanUp;

#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN     = 1;
   DEBUG_PIN     = 0;
#endif //  (DEBUG&CYCLE_DEBUG)
#if (HW_CAPABILITY&CAP_RST_IN)
   // RESET rise may be delayed by target POR
   if (bdm_option.useResetSignal) {
      WAIT_WITH_TIMEOUT_S( 2 /* s */, (RESET_IN!=0) );
   }
#endif
#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN   = 0;
   DEBUG_PIN   = 1;
#endif // (DEBUG&CYCLE_DEBUG)

   // Let signals settle & CPU to finish reset (with BKGD held low)
   WAIT_US(BKGD_WAITus);

#if (HW_CAPABILITY&CAP_RST_IN)
   if (bdm_option.useResetSignal && (RESET_IN==0)) {
      // RESET didn't rise
      rc = BDM_RC_RESET_TIMEOUT_RISE;
      goto cleanUp;
      }
#endif //(HW_CAPABILITY&CAP_RST_IO)

#if (DEBUG&CYCLE_DEBUG)
   DEBUG_PIN     = 1;
   DEBUG_PIN     = 0;
#endif // (DEBUG&CYCLE_DEBUG)

#if (HW_CAPABILITY&CAP_CFVx_HW)
   if  (cable_status.target_type == T_CFVx)
      bdmcf_interfaceIdle();  // Release BKPT etc
   else
#endif
#if (HW_CAPABILITY&CAP_BDM)     
      bdmHCS_interfaceIdle();  // Release BKGD
#endif
   // Let processor start up
   WAIT_MS(RESET_RECOVERYms);

#if 0
// Removed - some targets may be holding BKGD low (e.g. used as port pin)
// This situation is handled elsewhere (requires power cycle)
   if (BDM_IN==0) { // BKGD didn't rise!
      rc = BDM_RC_BKGD_TIMEOUT;
      goto cleanUp;
      }
#endif // 0

   cable_status.reset  = RESET_DETECTED; // Cycling the power should have reset it!

cleanUp:
#if (HW_CAPABILITY&CAP_CFVx_HW)
   if  (cable_status.target_type == T_CFVx)
      bdmcf_interfaceIdle();  // Release BKPT etc
   else
#endif
#if (HW_CAPABILITY&CAP_BDM)     
      bdmHCS_interfaceIdle();  // Release BKGD
#endif
   
   WAIT_MS( 250 /* ms */);

//   EnableInterrupts;
#endif // CAP_VDDCONTROL

   (void)bdm_checkTargetVdd(); // Update Target Vdd LED & power status

   return(rc);
}