static struct sal_ret_values
sal_emulator (long index, unsigned long in1, unsigned long in2,
unsigned long in3, unsigned long in4, unsigned long in5,
unsigned long in6, unsigned long in7)
{
long r9 = 0;
long r10 = 0;
long r11 = 0;
long status;
/*
* Don't do a "switch" here since that gives us code that
* isn't self-relocatable.
*/
status = 0;
if (index == SAL_FREQ_BASE) {
switch (in1) {
case SAL_FREQ_BASE_PLATFORM:
r9 = 200000000;
break;
case SAL_FREQ_BASE_INTERVAL_TIMER:
/*
* Is this supposed to be the cr.itc frequency
* or something platform specific? The SAL
* doc ain't exactly clear on this...
*/
r9 = 700000000;
break;
case SAL_FREQ_BASE_REALTIME_CLOCK:
r9 = 1;
break;
default:
status = -1;
break;
}
} else if (index == SAL_SET_VECTORS) {
;
} else if (index == SAL_GET_STATE_INFO) {
;
} else if (index == SAL_GET_STATE_INFO_SIZE) {
;
} else if (index == SAL_CLEAR_STATE_INFO) {
;
} else if (index == SAL_MC_RENDEZ) {
;
} else if (index == SAL_MC_SET_PARAMS) {
;
} else if (index == SAL_CACHE_FLUSH) {
;
} else if (index == SAL_CACHE_INIT) {
;
#ifdef CONFIG_PCI
} else if (index == SAL_PCI_CONFIG_READ) {
/*
* in1 contains the PCI configuration address and in2
* the size of the read. The value that is read is
* returned via the general register r9.
*/
outl(BUILD_CMD(in1), 0xCF8);
if (in2 == 1) /* Reading byte */
r9 = inb(0xCFC + ((REG_OFFSET(in1) & 3)));
else if (in2 == 2) /* Reading word */
r9 = inw(0xCFC + ((REG_OFFSET(in1) & 2)));
else /* Reading dword */
r9 = inl(0xCFC);
status = PCIBIOS_SUCCESSFUL;
} else if (index == SAL_PCI_CONFIG_WRITE) {
/*
* in1 contains the PCI configuration address, in2 the
* size of the write, and in3 the actual value to be
* written out.
*/
outl(BUILD_CMD(in1), 0xCF8);
if (in2 == 1) /* Writing byte */
outb(in3, 0xCFC + ((REG_OFFSET(in1) & 3)));
else if (in2 == 2) /* Writing word */
outw(in3, 0xCFC + ((REG_OFFSET(in1) & 2)));
else /* Writing dword */
outl(in3, 0xCFC);
status = PCIBIOS_SUCCESSFUL;
#endif /* CONFIG_PCI */
} else if (index == SAL_UPDATE_PAL) {
;
} else {
status = -1;
}
return ((struct sal_ret_values) {status, r9, r10, r11});
static void
nvmf_test_process_admin_cmd(void)
{
struct spdk_nvme_cmd nvmf_cmd = {};
struct nvmf_session *sess;
struct nvmf_request nvmf_req = {};
struct spdk_nvmf_subsystem *subsystem;
int buf_len = sizeof(struct spdk_nvme_ns_data);
uint8_t *buf;
sess = nvmf_find_session_by_id("subsystem1", SS_SC_CNTLID);
nvmf_req.rsp = malloc(sizeof(union nvmf_c2h_msg));
nvmf_req.cb_fn = admin_nvmf_cmd_complete;
#define BUILD_CMD(cmd_opc, cmd_nsid, cmd_cid, cmd_cdw10) \
do { \
nvmf_cmd.opc = cmd_opc; \
nvmf_cmd.nsid = cmd_nsid; \
nvmf_cmd.cid = cmd_cid; \
nvmf_cmd.cdw10 = cmd_cdw10; \
} while (0)
#define RUN_AND_CHECK_PROPERT_GET_RESULT(expect_ret, cmd_cid, sts) \
do { \
CU_ASSERT_EQUAL(nvmf_process_admin_cmd(sess, &nvmf_cmd, buf, buf_len, &nvmf_req), expect_ret); \
CU_ASSERT_EQUAL(nvmf_req.rsp->nvme_cpl.cid, cmd_cid); \
CU_ASSERT_EQUAL(nvmf_req.rsp->nvme_cpl.status.sc, sts); \
} while (0)
/* check subsys=NULL condition */
buf = malloc(buf_len);
subsystem = sess->subsys;
sess->subsys = NULL;
BUILD_CMD(SPDK_NVME_OPC_IDENTIFY, 2, 100, 0);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 100, SPDK_NVME_SC_INTERNAL_DEVICE_ERROR);
sess->subsys = subsystem;
/* identify namespace, namespace id = MAX_PER_SUBSYSTEM_NAMESPACES */
BUILD_CMD(SPDK_NVME_OPC_IDENTIFY, MAX_PER_SUBSYSTEM_NAMESPACES, 101, 0);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 101, SPDK_NVME_SC_INVALID_NAMESPACE_OR_FORMAT);
/* namespace id > MAX_PER_SUBSYSTEM_NAMESPACES */
BUILD_CMD(SPDK_NVME_OPC_IDENTIFY, MAX_PER_SUBSYSTEM_NAMESPACES + 1, 102, 0);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 102, SPDK_NVME_SC_INVALID_NAMESPACE_OR_FORMAT);
/* namespace id = 0 */
BUILD_CMD(SPDK_NVME_OPC_IDENTIFY, 0, 103, 0);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 103, SPDK_NVME_SC_INVALID_NAMESPACE_OR_FORMAT);
/* identify namespace */
BUILD_CMD(SPDK_NVME_OPC_IDENTIFY, 2, 8, 0);
RUN_AND_CHECK_PROPERT_GET_RESULT(0, 8, SPDK_NVME_SC_SUCCESS);
free(buf);
/* identify controller */
buf_len = sizeof(struct spdk_nvme_ctrlr_data);
buf = malloc(buf_len);
BUILD_CMD(SPDK_NVME_OPC_IDENTIFY, 2, 9, 1);
RUN_AND_CHECK_PROPERT_GET_RESULT(0, 9, SPDK_NVME_SC_SUCCESS);
free(buf);
/* identify controller with invalid cdw10=2 */
buf_len = sizeof(struct spdk_nvme_ctrlr_data);
buf = malloc(buf_len);
BUILD_CMD(SPDK_NVME_OPC_IDENTIFY, 2, 9, 2);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 9, SPDK_NVME_SC_INVALID_OPCODE);
/* create IO SQ whose qid > MAX_SESSION_IO_QUEUES */
BUILD_CMD(SPDK_NVME_OPC_CREATE_IO_SQ, 2, 110, 0xff00ff);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 110, SPDK_NVME_SC_INVALID_FIELD);
CU_ASSERT_EQUAL(sess->active_queues, 0);
/* create IO SQ */
BUILD_CMD(SPDK_NVME_OPC_CREATE_IO_SQ, 2, 10, 0xff0001);
RUN_AND_CHECK_PROPERT_GET_RESULT(1, 10, SPDK_NVME_SC_SUCCESS);
CU_ASSERT_EQUAL(sess->active_queues, 0);
/* create same IO SQ again*/
BUILD_CMD(SPDK_NVME_OPC_CREATE_IO_SQ, 2, 101, 0xff0001);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 101, SPDK_NVME_SC_INVALID_FIELD);
CU_ASSERT_EQUAL(sess->active_queues, 0);
/* create CO SQ whose qid > MAX_SESSION_IO_QUEUES */
BUILD_CMD(SPDK_NVME_OPC_CREATE_IO_CQ, 2, 112, 0xff00ff);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 112, SPDK_NVME_SC_INVALID_FIELD);
CU_ASSERT_EQUAL(sess->active_queues, 0);
/* create IO CQ */
BUILD_CMD(SPDK_NVME_OPC_CREATE_IO_CQ, 2, 11, 0xff0001);
RUN_AND_CHECK_PROPERT_GET_RESULT(1, 11, SPDK_NVME_SC_SUCCESS);
CU_ASSERT_EQUAL(sess->active_queues, 1);
/* create same IO CQ again*/
BUILD_CMD(SPDK_NVME_OPC_CREATE_IO_SQ, 2, 103, 0xff0001);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 103, SPDK_NVME_SC_INVALID_FIELD);
CU_ASSERT_EQUAL(sess->active_queues, 1);
/* del IO SQ whose id > MAX_SESSION_IO_QUEUES */
BUILD_CMD(SPDK_NVME_OPC_DELETE_IO_SQ, 2, 105, 0xff0fff);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 105, SPDK_NVME_SC_INVALID_FIELD);
CU_ASSERT_EQUAL(sess->active_queues, 1);
/* del IO SQ who is not active */
BUILD_CMD(SPDK_NVME_OPC_DELETE_IO_SQ, 2, 106, 0xff0002);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 106, SPDK_NVME_SC_INVALID_FIELD);
CU_ASSERT_EQUAL(sess->active_queues, 1);
/* del IO SQ */
BUILD_CMD(SPDK_NVME_OPC_DELETE_IO_SQ, 2, 12, 0xff0001);
RUN_AND_CHECK_PROPERT_GET_RESULT(1, 12, SPDK_NVME_SC_SUCCESS);
CU_ASSERT_EQUAL(sess->active_queues, 0);
/* del IO CQ whose id > MAX_SESSION_IO_QUEUES */
BUILD_CMD(SPDK_NVME_OPC_DELETE_IO_CQ, 2, 107, 0xff0fff);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 107, SPDK_NVME_SC_INVALID_FIELD);
/* del IO SQ who is not active */
BUILD_CMD(SPDK_NVME_OPC_DELETE_IO_CQ, 2, 108, 0xff0002);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 108, SPDK_NVME_SC_INVALID_FIELD);
/* del IO CQ */
BUILD_CMD(SPDK_NVME_OPC_DELETE_IO_CQ, 2, 13, 0xff0001);
RUN_AND_CHECK_PROPERT_GET_RESULT(1, 13, SPDK_NVME_SC_SUCCESS);
CU_ASSERT_EQUAL(sess->active_queues, 0);
/* del same IO SQ again, should fail */
BUILD_CMD(SPDK_NVME_OPC_DELETE_IO_SQ, 2, 15, 0xff0001);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 15, SPDK_NVME_SC_INVALID_FIELD);
/* del same CQ again, should fail */
BUILD_CMD(SPDK_NVME_OPC_DELETE_IO_CQ, 2, 16, 0xff0001);
RUN_AND_CHECK_PROPERT_GET_RESULT(-1, 16, SPDK_NVME_SC_INVALID_FIELD);
/* get max io queue number */
BUILD_CMD(SPDK_NVME_OPC_GET_FEATURES, 2, 17, SPDK_NVME_FEAT_NUMBER_OF_QUEUES);
RUN_AND_CHECK_PROPERT_GET_RESULT(1, 17, SPDK_NVME_SC_SUCCESS);
CU_ASSERT_EQUAL(nvmf_req.rsp->nvme_cpl.cdw0 & 0xffff, 63);
/* set max io queue number failed due to active queue */
sess->active_queues = 1;
BUILD_CMD(SPDK_NVME_OPC_SET_FEATURES, 2, 18, SPDK_NVME_FEAT_NUMBER_OF_QUEUES);
RUN_AND_CHECK_PROPERT_GET_RESULT(1, 18, SPDK_NVME_SC_COMMAND_SEQUENCE_ERROR);
sess->active_queues = 0;
/* set max io queue number, these are not completed*/
BUILD_CMD(SPDK_NVME_OPC_SET_FEATURES, 2, 19, SPDK_NVME_FEAT_NUMBER_OF_QUEUES);
RUN_AND_CHECK_PROPERT_GET_RESULT(1, 19, SPDK_NVME_SC_SUCCESS);
CU_ASSERT_EQUAL(nvmf_req.rsp->nvme_cpl.cdw0 & 0xffff, 63);
free(buf);
buf = NULL;
}
static struct sal_ret_values
sal_emulator (long index, unsigned long in1, unsigned long in2,
unsigned long in3, unsigned long in4, unsigned long in5,
unsigned long in6, unsigned long in7)
{
long r9 = 0;
long r10 = 0;
long r11 = 0;
long status;
status = 0;
if (index == SAL_FREQ_BASE) {
if (in1 == SAL_FREQ_BASE_PLATFORM)
r9 = 200000000;
else if (in1 == SAL_FREQ_BASE_INTERVAL_TIMER) {
r9 = 700000000;
} else if (in1 == SAL_FREQ_BASE_REALTIME_CLOCK)
r9 = 1;
else
status = -1;
} else if (index == SAL_SET_VECTORS) {
;
} else if (index == SAL_GET_STATE_INFO) {
;
} else if (index == SAL_GET_STATE_INFO_SIZE) {
;
} else if (index == SAL_CLEAR_STATE_INFO) {
;
} else if (index == SAL_MC_RENDEZ) {
;
} else if (index == SAL_MC_SET_PARAMS) {
;
} else if (index == SAL_CACHE_FLUSH) {
;
} else if (index == SAL_CACHE_INIT) {
;
#ifdef CONFIG_PCI
} else if (index == SAL_PCI_CONFIG_READ) {
outl(BUILD_CMD(in1), 0xCF8);
if (in2 == 1)
r9 = inb(0xCFC + ((REG_OFFSET(in1) & 3)));
else if (in2 == 2)
r9 = inw(0xCFC + ((REG_OFFSET(in1) & 2)));
else
r9 = inl(0xCFC);
status = PCIBIOS_SUCCESSFUL;
} else if (index == SAL_PCI_CONFIG_WRITE) {
/*
* in1 contains the PCI configuration address, in2 the
* size of the write, and in3 the actual value to be
* written out.
*/
outl(BUILD_CMD(in1), 0xCF8);
if (in2 == 1)
outb(in3, 0xCFC + ((REG_OFFSET(in1) & 3)));
else if (in2 == 2)
outw(in3, 0xCFC + ((REG_OFFSET(in1) & 2)));
else
outl(in3, 0xCFC);
status = PCIBIOS_SUCCESSFUL;
#endif
} else if (index == SAL_UPDATE_PAL) {
;
} else {
status = -1;
}
return ((struct sal_ret_values) {status, r9, r10, r11});
//portTASK_FUNCTION(vCmdParserTask, pvParameters) {
void CmdParserTask(void const *argument){
// portBASE_TYPE xHigherPriorityTaskWoken;
cmdParserMessageQueue = xQueueCreate(5, 20);
uint8_t message[20];
uint8_t cmdIn[5];
uint8_t chr;
uint8_t byteRead;
command tempCmd;
while(1){
xQueueReceive(cmdParserMessageQueue, message, portMAX_DELAY);
///commsSendString("PARS_Run\r\n");
if(message[0] == '1'){//parsing of command
do{
cmdIn[0] = cmdIn[1];
cmdIn[1] = cmdIn[2];
cmdIn[2] = cmdIn[3];
cmdIn[3] = chr;
byteRead = commBufferReadByte(&chr);
}while(byteRead==0 && chr != ':' && chr != ';');
if(byteRead==0){
switch (BUILD_CMD(cmdIn)){
case CMD_IDN: //send IDN
xQueueSendToBack(messageQueue, STR_ACK, portMAX_DELAY);
xQueueSendToBack (messageQueue, IDN_STRING, portMAX_DELAY);
break;
case CMD_VERSION:
xQueueSendToBack(messageQueue, "9SendSystVersion", portMAX_DELAY);
break;
case CMD_SYSTEM:
tempCmd = parseSystemCmd();
printErrResponse(tempCmd);
break;
case CMD_COMMS:
tempCmd = parseCommsCmd();
printErrResponse(tempCmd);
break;
#ifdef USE_SCOPE
case CMD_SCOPE: //parse scope command
tempCmd = parseScopeCmd();
printErrResponse(tempCmd);
break;
#endif //USE_SCOPE
#ifdef USE_GEN
case CMD_GENERATOR: //parse generator command
tempCmd = parseGeneratorCmd();
printErrResponse(tempCmd);
break;
#endif //USE_GEN
default:
xQueueSendToBack(messageQueue, UNSUPORTED_FUNCTION_ERR_STR, portMAX_DELAY);
while(commBufferReadByte(&chr)==0 && chr!=';');
//// commsSendUint32(cmdIn);
}
}
}
/* if (getBytesAvailable()>=15){
xQueueSendToBackFromISR(cmdParserMessageQueue, "1TryParseCmd", &xHigherPriorityTaskWoken);
}*/
}
}
