void __init boardLedInit(void)
{
PBP_LED_INFO pInfo;
ETHERNET_MAC_INFO EnetInfo;
unsigned short i;
short gpio;
spin_lock_init(&brcm_ledlock);
#if !(defined(CONFIG_BCM96328) || defined(CONFIG_BCM96362))
/* Set blink rate for hardware LEDs. */
GPIO->LEDCtrl &= ~LED_INTERVAL_SET_MASK;
GPIO->LEDCtrl |= LED_INTERVAL_SET_80MS;
#endif
gLedCtrl = (PLED_CTRL) kmalloc((kLedEnd * sizeof(LED_CTRL)), GFP_KERNEL);
if( gLedCtrl == NULL ) {
printk( "LED memory allocation error.\n" );
return;
}
/* Initialize LED control */
for (i = 0; i < kLedEnd; i++) {
gLedCtrl[i].ledHwFunc = NULL;
gLedCtrl[i].ledGreenGpio = -1;
gLedCtrl[i].ledRedGpio = -1;
gLedCtrl[i].ledState = kLedStateOff;
gLedCtrl[i].blinkCountDown = 0; // reset the blink count down
}
for( pInfo = bpLedInfo; pInfo->ledName != kLedEnd; pInfo++ ) {
if( pInfo->bpFunc && (*pInfo->bpFunc) (&gpio) == BP_SUCCESS )
{
gLedCtrl[pInfo->ledName].ledGreenGpio = gpio;
}
if( pInfo->bpFuncFail && (*pInfo->bpFuncFail)(&gpio)==BP_SUCCESS )
{
gLedCtrl[pInfo->ledName].ledRedGpio = gpio;
}
setLed(&gLedCtrl[pInfo->ledName], kLedOff, kLedGreen);
setLed(&gLedCtrl[pInfo->ledName], kLedOff, kLedRed);
}
if( BpGetEthernetMacInfo( &EnetInfo, 1 ) == BP_SUCCESS ) {
if( EnetInfo.usGpioLedPhyLinkSpeed != BP_NOT_DEFINED ) {
/* The internal Ethernet PHY has a GPIO for 10/100 link speed. */
gLedCtrl[kLedEphyLinkSpeed].ledGreenGpio = EnetInfo.usGpioLedPhyLinkSpeed;
setLed(&gLedCtrl[kLedEphyLinkSpeed], kLedOff, kLedGreen);
}
}
#if defined(DEBUG_LED)
for (i=0; i < kLedEnd; i++)
printk("initLed: led[%d]: Gpio=0x%04x, FailGpio=0x%04x\n", i, gLedCtrl[i].ledGreenGpio, gLedCtrl[i].ledRedGpio);
#endif
}
/*
* init_emac: Initializes the Ethernet control registers
*/
static int init_emac(bcmenet_softc *softc)
{
ETHERNET_MAC_INFO EnetInfos[BP_MAX_ENET_MACS];
#if defined(_BCM96348_)
uint32 gpiomode;
#endif
/* disable ethernet MAC while updating its registers */
EMAC->config = EMAC_DISABLE ;
while(EMAC->config & EMAC_DISABLE);
/* issue soft reset, wait for it to complete */
EMAC->config = EMAC_SOFT_RESET;
while (EMAC->config & EMAC_SOFT_RESET);
BpGetEthernetMacInfo( EnetInfos, BP_MAX_ENET_MACS );
memcpy(&softc->EnetInfo,&EnetInfos[EMAC_INFO_INDEX],sizeof(softc->EnetInfo));
softc->emac = EMAC;
#if defined(_BCM96348_)
if (softc->emac == EMAC2) {
if (softc->EnetInfo.ucPhyType != BP_ENET_INTERNAL_PHY) {
gpiomode = GPIO->GPIOMode;
gpiomode |= (GROUP3_EXT_MII|GROUP0_EXT_MII); /* External MII */
if ((softc->EnetInfo.usConfigType == BP_ENET_CONFIG_SPI_SSB_1) ||
(softc->EnetInfo.usConfigType == BP_ENET_CONFIG_SPI_SSB_2) ||
(softc->EnetInfo.usConfigType == BP_ENET_CONFIG_SPI_SSB_3)) {
gpiomode &= ~GROUP1_SPI_MASTER;
gpiomode |= GROUP1_SPI_MASTER;
}
GPIO->GPIOMode = gpiomode;
}
}
#endif
if (mii_init(softc))
return -1;
/* Initialize emac registers */
EMAC->rxControl = EMAC_FC_EN; // //EMAC_PROM; NO Promiscuous > 5.0
#ifdef MAC_LOOPBACK
EMAC->rxControl |= EMAC_LOOPBACK;
#endif
EMAC->rxMaxLength = ENET_MAX_MTU_SIZE;
EMAC->txMaxLength = ENET_MAX_MTU_SIZE;
/* tx threshold = abs(63-(0.63*DMA_MAX_BURST_LENGTH)) */
EMAC->txThreshold = EMAC_TX_WATERMARK;
EMAC->mibControl = EMAC_NO_CLEAR; /* clear MIBs on read */
EMAC->intMask = 0; /* mask all EMAC interrupts*/
EMAC->config |= EMAC_ENABLE;
softc->dmaCtrl->controller_cfg |= DMA_MASTER_EN;
return 0;
}
static int bcmPktDma_calc_txbds( void )
{
uint32_t chnl;
#if defined(CONFIG_BCM_FAP) || defined(CONFIG_BCM_FAP_MODULE)
int iudmaIdx;
#else
#if !defined(CONFIG_BCM96368)
uint32_t tot_mem_size = kerSysGetSdramSize();
#endif
#endif
chnl = 0; /* to avoid compiler warning */
#if defined(CONFIG_BCM_FAP) || defined(CONFIG_BCM_FAP_MODULE)
/* Host config */
for (chnl=0; chnl < ENET_TX_CHANNELS_MAX; chnl++)
{
if (g_Eth_tx_iudma_ownership[chnl] == HOST_OWNED)
bcmPktDma_Bds_p->host.eth_txbds[chnl] = HOST_ENET_NR_TXBDS;
else
bcmPktDma_Bds_p->host.eth_txbds[chnl] = 0;
}
for (chnl=0; chnl < ENET_TX_CHANNELS_MAX; chnl++)
{
if (g_Eth_tx_iudma_ownership[chnl] == HOST_OWNED)
bcmPktDma_Bds_p->host.eth_txdqm[chnl] = 0;
else
bcmPktDma_Bds_p->host.eth_txdqm[chnl] = DQM_HOST2FAP_ETH_XMIT_DEPTH_LOW;
}
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
for (chnl=0; chnl < XTM_TX_CHANNELS_MAX; chnl++)
{
bcmPktDma_Bds_p->host.xtm_txbds[chnl] = 0;
}
for (chnl=0; chnl < XTM_TX_CHANNELS_MAX; chnl++)
{
if (g_Xtm_tx_iudma_ownership[chnl] == HOST_OWNED)
bcmPktDma_Bds_p->host.xtm_txdqm[chnl] = 0;
else
bcmPktDma_Bds_p->host.xtm_txdqm[chnl] = DQM_HOST2FAP_XTM_XMIT_DEPTH_LOW;
}
#endif /* defined(CONFIG_BCM_XTMCFG) */
/* FAP config */
for (iudmaIdx = 0; iudmaIdx < CONFIG_BCM_DEF_NR_TX_DMA_CHANNELS; iudmaIdx++)
{
if (g_Eth_tx_iudma_ownership[iudmaIdx] == HOST_OWNED)
bcmPktDma_Bds_p->fap.eth_txbds[iudmaIdx] = 0;
else
bcmPktDma_Bds_p->fap.eth_txbds[iudmaIdx] = FAP_ENET_NR_TXBDS;
}
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
for (chnl=0; chnl < XTM_TX_CHANNELS_MAX; chnl++)
{
if (g_Xtm_tx_iudma_ownership[chnl] == HOST_OWNED)
bcmPktDma_Bds_p->fap.xtm_txbds[chnl] = 0;
else
bcmPktDma_Bds_p->fap.xtm_txbds[chnl] = FAP_XTM_NR_TXBDS;
}
#endif /* defined(CONFIG_BCM_XTMCFG) */
#endif
#if defined(CONFIG_BCM96368)
bcmPktDma_Bds_p->host.eth_txbds[0] = HOST_ENET_NR_TXBDS;
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
for (chnl=0; chnl < XTM_TX_CHANNELS_MAX; chnl++)
{
bcmPktDma_Bds_p->host.xtm_txbds[chnl] = HOST_XTM_NR_TXBDS;
}
#endif
bcmPktDma_Bds_p->fwd.eth_txbds[0] = FWD_ENET_NR_TXBDS;
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
bcmPktDma_Bds_p->fwd.xtm_txbds[0] = FWD_XTM_NR_TXBDS;
#endif
#endif
#if defined(CONFIG_BCM960333)
/*
* For Duna: read the number of network interfaces from Boardparms.
* Currently we assign the same number of TX buffers to each interface.
*/
{
ETHERNET_MAC_INFO EnetInfo;
int num_channels = 0;
if (BpGetEthernetMacInfo(&EnetInfo, 1) != BP_SUCCESS)
{
return -ENODEV;
}
bitcount(num_channels, EnetInfo.sw.port_map);
for (chnl = 0; chnl < num_channels; chnl++)
{
/* Setup the PLC TX ring size to hold up to 60% of BPM buffers */
if (EnetInfo.sw.phyconn[chnl] == PHY_CONN_TYPE_PLC)
{
uint32_t tx_ring_size;
tx_ring_size = kerSysGetSdramSize() / 100
* CONFIG_BCM_BPM_BUF_MEM_PRCNT * 60 / 100
/ BCM_PKTBUF_SIZE;
tx_ring_size = tx_ring_size & (uint32_t)(0xFFFFFFFE);
if (tx_ring_size > 8192)
{
tx_ring_size = 8192;
}
bcmPktDma_Bds_p->host.eth_txbds[chnl] = tx_ring_size;
}
/* Every other channel has a TX ring of default size */
else
{
if (tot_mem_size <= 0x1600000) // less than or equal to 16MB
bcmPktDma_Bds_p->host.eth_txbds[chnl] = HOST_ENET_NR_TXBDS/4;
else
bcmPktDma_Bds_p->host.eth_txbds[chnl] = HOST_ENET_NR_TXBDS;
}
}
}
#endif
#if !(defined(CONFIG_BCM96368) || defined(CONFIG_BCM960333)\
|| defined(CONFIG_BCM_FAP) || defined(CONFIG_BCM_FAP_MODULE))
for (chnl=0; chnl < ENET_TX_CHANNELS_MAX; chnl++)
{
if (tot_mem_size <= 0x1600000) // less than or equal to 16MB
bcmPktDma_Bds_p->host.eth_txbds[chnl] = HOST_ENET_NR_TXBDS/4;
else
bcmPktDma_Bds_p->host.eth_txbds[chnl] = HOST_ENET_NR_TXBDS;
}
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
for (chnl=0; chnl < XTM_TX_CHANNELS_MAX; chnl++)
{
if (tot_mem_size <= 0x1600000) // less than or equal to 16MB
bcmPktDma_Bds_p->host.xtm_txbds[chnl] = HOST_XTM_NR_TXBDS/4;
else
bcmPktDma_Bds_p->host.xtm_txbds[chnl] = HOST_XTM_NR_TXBDS;
}
#endif
#endif
#if defined(BCM_PKTDMA_DUMP_BDS)
bcmPktDma_dump_txbds();
#endif /* defined(BCM_PKTDMA_DUMP_BDS) */
return 0;
}
static int bcmPktDma_calc_rxbds( void )
{
uint32_t __attribute__((unused)) tot_mem_size = kerSysGetSdramSize();
#if (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE))
uint32_t buf_mem_size = (tot_mem_size/100) * CONFIG_BCM_BPM_BUF_MEM_PRCNT;
uint32_t tot_num_bufs=0;
#endif
uint32_t chnl;
uint32_t host_eth_rxbds;
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
uint32_t host_xtm_rxbds;
#endif
chnl = 0; /* to avoid compiler warning */
#if (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE))
tot_num_bufs = (buf_mem_size/BCM_PKTBUF_SIZE);
#endif
#if defined(CONFIG_BCM_FAP) || defined(CONFIG_BCM_FAP_MODULE)
/* ----------- FAP RX channel ---------- */
#if (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE))
/* Channel-0 is default */
host_eth_rxbds = (ENET_DEF_RXBDS_BUF_PRCNT * tot_num_bufs/200);
if (host_eth_rxbds < HOST_ENET_NR_RXBDS_MIN)
host_eth_rxbds = HOST_ENET_NR_RXBDS_MIN;
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
host_xtm_rxbds = (XTM_DEF_RXBDS_BUF_PRCNT * tot_num_bufs/200);
if (host_xtm_rxbds < HOST_XTM_NR_RXBDS_MIN)
host_xtm_rxbds = HOST_XTM_NR_RXBDS_MIN;
#endif
#else /* (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE)) */
host_eth_rxbds = HOST_ENET_NR_RXBDS;
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
host_xtm_rxbds = HOST_XTM_NR_RXBDS;
#endif
#endif /* (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE)) */
#if defined(CONFIG_BCM_GMAC)
host_eth_rxbds /= 2;
#endif
for (chnl=0; chnl < ENET_RX_CHANNELS_MAX; chnl++)
{
if (g_Eth_rx_iudma_ownership[chnl] == HOST_OWNED )
bcmPktDma_Bds_p->host.eth_rxbds[chnl] = host_eth_rxbds;
else
bcmPktDma_Bds_p->host.eth_rxbds[chnl] = 0;
bcmPktDma_tot_rxbds_g += bcmPktDma_Bds_p->host.eth_rxbds[chnl];
}
for (chnl=0; chnl < ENET_RX_CHANNELS_MAX; chnl++)
{
if (g_Eth_rx_iudma_ownership[chnl] == HOST_OWNED )
bcmPktDma_Bds_p->host.eth_rxdqm[chnl] = 0;
else
{
bcmPktDma_Bds_p->host.eth_rxdqm[chnl] =
DQM_FAP2HOST_ETH_RX_DEPTH_LOW + DQM_FAP2HOST_ETH_RX_DEPTH_HI;
}
}
/* XTM config */
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
for (chnl=0; chnl < XTM_RX_CHANNELS_MAX; chnl++)
{
if (g_Xtm_rx_iudma_ownership[chnl] == HOST_OWNED)
{
bcmPktDma_Bds_p->host.xtm_rxbds[chnl] = host_xtm_rxbds;
}
else
bcmPktDma_Bds_p->host.xtm_rxbds[chnl] =
FAP_XTM_NON_DEF_CHNL_NR_RXBDS;
bcmPktDma_tot_rxbds_g += bcmPktDma_Bds_p->host.xtm_rxbds[chnl];
}
for (chnl=0; chnl < XTM_RX_CHANNELS_MAX; chnl++)
{
if (g_Xtm_rx_iudma_ownership[chnl] == HOST_OWNED)
bcmPktDma_Bds_p->host.xtm_rxdqm[chnl] = 0;
else
{
if (chnl == 0)
{
bcmPktDma_Bds_p->host.xtm_rxdqm[chnl] =
DQM_FAP2HOST_XTM_RX_DEPTH_LOW + DQM_FAP2HOST_XTM_RX_DEPTH_HI;
}
else
{
/* currently we using only 1 channel even when 2 channels are
* intialized, so keep the other channel size very low
*/
bcmPktDma_Bds_p->host.xtm_rxdqm[chnl] = 16;
}
}
}
#endif /* #if defined(CONFIG_BCM_XTMCFG) */
/* FAP config */
for (chnl=0; chnl < ENET_RX_CHANNELS_MAX; chnl++)
{
if (g_Eth_rx_iudma_ownership[chnl] == HOST_OWNED)
bcmPktDma_Bds_p->fap.eth_rxbds[chnl] = 0;
else
bcmPktDma_Bds_p->fap.eth_rxbds[chnl] = FAP_ENET_NR_RXBDS;
bcmPktDma_tot_rxbds_g += bcmPktDma_Bds_p->fap.eth_rxbds[chnl];
}
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
for (chnl=0; chnl < XTM_RX_CHANNELS_MAX; chnl++)
{
if (g_Xtm_rx_iudma_ownership[chnl] == HOST_OWNED)
bcmPktDma_Bds_p->fap.xtm_rxbds[chnl] = 0;
else
{
if (chnl == 0)
bcmPktDma_Bds_p->fap.xtm_rxbds[chnl] = FAP_XTM_NR_RXBDS;
else
bcmPktDma_Bds_p->fap.xtm_rxbds[chnl] =
FAP_XTM_NON_DEF_CHNL_NR_RXBDS;
}
bcmPktDma_tot_rxbds_g += bcmPktDma_Bds_p->fap.xtm_rxbds[chnl];
}
#endif /* defined(CONFIG_BCM_XTMCFG) */
#endif /* defined(CONFIG_BCM_FAP) || defined(CONFIG_BCM_FAP_MODULE) */
#if defined(CONFIG_BCM96368)
#if (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE))
/* ----------- CMF FWD RX ---------- */
/* In case of 6368 because of CMF the number of RXBDs is divided
* equally between Eth driver and CMF FWD */
host_eth_rxbds = (ENET_DEF_RXBDS_BUF_PRCNT * tot_num_bufs/200);
if (host_eth_rxbds < HOST_ENET_NR_RXBDS_MIN)
host_eth_rxbds = HOST_ENET_NR_RXBDS_MIN;
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
host_xtm_rxbds = (XTM_DEF_RXBDS_BUF_PRCNT * tot_num_bufs/200);
if (host_xtm_rxbds < HOST_XTM_NR_RXBDS_MIN)
host_xtm_rxbds = HOST_XTM_NR_RXBDS_MIN;
#endif
#else /* (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE)) */
host_eth_rxbds = HOST_ENET_NR_RXBDS;
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
host_xtm_rxbds = HOST_XTM_NR_RXBDS;
#endif
#endif /* (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE)) */
bcmPktDma_Bds_p->host.eth_rxbds[0] = host_eth_rxbds;
bcmPktDma_tot_rxbds_g += bcmPktDma_Bds_p->host.eth_rxbds[0];
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
bcmPktDma_Bds_p->host.xtm_rxbds[0] = host_xtm_rxbds;
for (chnl=1; chnl < XTM_RX_CHANNELS_MAX; chnl++)
{
bcmPktDma_Bds_p->host.xtm_rxbds[chnl] = HOST_XTM_NON_DEF_CHNL_NR_RXBDS;
}
for (chnl=0; chnl < XTM_RX_CHANNELS_MAX; chnl++)
{
bcmPktDma_tot_rxbds_g += bcmPktDma_Bds_p->host.xtm_rxbds[chnl];
}
#endif
/* Note: The # of FWD RXBDs is equal to host RXBDs */
bcmPktDma_Bds_p->fwd.eth_rxbds[0] = host_eth_rxbds;
bcmPktDma_tot_rxbds_g += bcmPktDma_Bds_p->fwd.eth_rxbds[0];
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
bcmPktDma_Bds_p->fwd.xtm_rxbds[0] = host_xtm_rxbds;
bcmPktDma_tot_rxbds_g += bcmPktDma_Bds_p->fwd.xtm_rxbds[0];
#endif
#endif
#if !(defined(CONFIG_BCM96368) || defined(CONFIG_BCM_FAP) || defined(CONFIG_BCM_FAP_MODULE))
/* ----------- Eth RX channel ---------- */
#if (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE))
host_eth_rxbds = ENET_DEF_RXBDS_BUF_PRCNT * tot_num_bufs/100;
#else /* (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE)) */
if (tot_mem_size <= 0x1600000) // less than or equal to 16MB
host_eth_rxbds = HOST_ENET_NR_RXBDS/4;
else
host_eth_rxbds = HOST_ENET_NR_RXBDS;
#endif /* (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE)) */
for (chnl=1; chnl < ENET_RX_CHANNELS_MAX; chnl++)
{
bcmPktDma_Bds_p->host.eth_rxbds[chnl] =
HOST_ENET_NON_DEF_CHNL_NR_RXBDS;
}
#if defined(CONFIG_BCM_GMAC)
host_eth_rxbds /= 2;
bcmPktDma_Bds_p->host.eth_rxbds[0] = host_eth_rxbds;
bcmPktDma_Bds_p->host.eth_rxbds[ENET_RX_CHANNELS_MAX-1] = host_eth_rxbds;
#else
#if defined(CONFIG_BCM960333)
/*
* For Duna: read the number of network interfaces from Boardparms.
* Currently we assign the same number of RX buffers to each interface.
*/
{
ETHERNET_MAC_INFO EnetInfo;
int num_channels = 0;
if (BpGetEthernetMacInfo(&EnetInfo, 1) != BP_SUCCESS)
{
return -ENODEV;
}
bitcount(num_channels, EnetInfo.sw.port_map);
for (chnl = 0; chnl < num_channels; chnl++)
{
bcmPktDma_Bds_p->host.eth_rxbds[chnl] =
host_eth_rxbds / num_channels;
}
}
#else
bcmPktDma_Bds_p->host.eth_rxbds[0] = host_eth_rxbds;
#endif
#endif
for (chnl=0; chnl < ENET_RX_CHANNELS_MAX; chnl++)
{
bcmPktDma_tot_rxbds_g += bcmPktDma_Bds_p->host.eth_rxbds[chnl];
}
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
/* ----------- XTM RX channel ---------- */
#if (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE))
host_xtm_rxbds = XTM_DEF_RXBDS_BUF_PRCNT * tot_num_bufs/100;
#else /* (defined(CONFIG_BCM_INGQOS) || defined(CONFIG_BCM_INGQOS_MODULE) || defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE)) */
/* ----------- XTM RX channel ---------- */
{
uint32_t tot_mem_size = kerSysGetSdramSize();
if (tot_mem_size <= 0x800000) // less than or equal to 8MB
host_xtm_rxbds = 60;
else if (tot_mem_size <= 0x1600000) // less than or equal to 16MB
host_xtm_rxbds = HOST_XTM_NR_RXBDS/4;
else
host_xtm_rxbds = HOST_XTM_NR_RXBDS;
}
#endif /* (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE)) */
#if defined(CONFIG_BCM_XTMCFG) || defined(CONFIG_BCM_XTMCFG_MODULE)
bcmPktDma_Bds_p->host.xtm_rxbds[0] = host_xtm_rxbds;
for (chnl=1; chnl < XTM_RX_CHANNELS_MAX; chnl++)
{
bcmPktDma_Bds_p->host.xtm_rxbds[chnl] = HOST_XTM_NON_DEF_CHNL_NR_RXBDS;
}
for (chnl=0; chnl < XTM_RX_CHANNELS_MAX; chnl++)
{
bcmPktDma_tot_rxbds_g += bcmPktDma_Bds_p->host.xtm_rxbds[chnl];
}
#endif
#endif
#endif
#if defined(BCM_PKTDMA_DUMP_BDS)
bcmPktDma_dump_rxbds();
#endif /* defined(BCM_PKTDMA_DUMP_BDS) */
#if (defined(CONFIG_BCM_BPM) || defined(CONFIG_BCM_BPM_MODULE))
printk( "Total # RxBds=%d\n", bcmPktDma_tot_rxbds_g);
if (bcmPktDma_tot_rxbds_g > tot_num_bufs)
{
printk( "ERROR!!!!: Not enough buffers available\n" );
printk( "ERROR!!!!: Either increase the %% of buffer memory "
"using make menuconfig\n" );
printk( "ERROR!!!!: Or reduce the # of RxBDs (bcmPktDma_bds.h)\n" );
return -1;
}
else if (bcmPktDma_tot_rxbds_g > (tot_num_bufs*2/3))
{
printk( "WARNING: # of RXBDs > (buffers*2/3)\n" );
printk( "WARNING: less buffers available for BPM\n" );
}
#endif
return 0;
}
