Ejemplo n.º 1
0
/* clock startup for Jellybean with Lemondrop attached
Configure PLL1 to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */ 
void cpu_clock_init(void)
{
	/* use IRC as clock source for APB1 (including I2C0) */
	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);

	/* use IRC as clock source for APB3 */
	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);

	//FIXME disable I2C
	/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
	i2c1_init(255);

	/*
	 * 12MHz clock is entering LPC XTAL1/OSC input now.  On
	 * Jellybean/Lemondrop, this is a signal from the clock generator.  On
	 * Jawbreaker, there is a 12 MHz crystal at the LPC.
	 * Set up PLL1 to run from XTAL1 input.
	 */

	//FIXME a lot of the details here should be in a CGU driver

	/* set xtal oscillator to low frequency mode */
	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;

	/* power on the oscillator and wait until stable */
	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;

	/* Wait about 100us after Crystal Power ON */
	delay(WAIT_CPU_CLOCK_INIT_DELAY);

	/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1));

	/* use XTAL_OSC as clock source for APB1 */
	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);

	/* use XTAL_OSC as clock source for APB3 */
	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);

	cpu_clock_pll1_low_speed();

	/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));

	/* use XTAL_OSC as clock source for PLL0USB */
	CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
			| CGU_PLL0USB_CTRL_AUTOBLOCK(1)
			| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
	while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK);

	/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
	/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
	CGU_PLL0USB_MDIV = 0x06167FFA;
	CGU_PLL0USB_NP_DIV = 0x00302062;
	CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD(1)
			| CGU_PLL0USB_CTRL_DIRECTI(1)
			| CGU_PLL0USB_CTRL_DIRECTO(1)
			| CGU_PLL0USB_CTRL_CLKEN(1));

	/* power on PLL0USB and wait until stable */
	CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
	while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK));

	/* use PLL0USB as clock source for USB0 */
	CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1)
			| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);

	/* Switch peripheral clock over to use PLL1 (204MHz) */
	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1)
			| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);

	/* Switch APB1 clock over to use PLL1 (204MHz) */
	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);

	/* Switch APB3 clock over to use PLL1 (204MHz) */
	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);

    ///XXX: Disable ADCHS clock
    CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_PD(1);

    CGU_PLL0AUDIO_CTRL = CGU_PLL0AUDIO_CTRL_PD(1)
        | CGU_PLL0AUDIO_CTRL_AUTOBLOCK(1)
        | CGU_PLL0AUDIO_CTRL_CLK_SEL(CGU_SRC_GP_CLKIN);
    while (CGU_PLL0AUDIO_STAT & CGU_PLL0AUDIO_STAT_LOCK_MASK);

    /* configure PLL0AUDIO to produce xxMHz */
    /* PLL Register settings (SEL_EXT=1):
       Mdec=31=PLL0_MDIV[16:0] => CGU_PLL0AUDIO_MDIV
       Ndec=0=PLL0_NPDIV[21:12], Pdec=21=PLL0_NPDIV[6:0] => CGU_PLL0AUDIO_NP_DIV
   */

    CGU_PLL0AUDIO_MDIV = 0;
    CGU_PLL0AUDIO_NP_DIV = 0;

    CGU_PLL0AUDIO_CTRL |= (CGU_PLL0AUDIO_CTRL_PD(1)
        | CGU_PLL0AUDIO_CTRL_SEL_EXT(1)
        | CGU_PLL1_CTRL_NSEL(0)
        | CGU_PLL1_CTRL_PSEL(0)
        | CGU_PLL0AUDIO_CTRL_CLKEN(1));

    ///* power on PLL0AUDIO and wait until stable */
    CGU_PLL0AUDIO_CTRL &= ~CGU_PLL0AUDIO_CTRL_PD(1);
    while (!(CGU_PLL0AUDIO_STAT & CGU_PLL0AUDIO_STAT_LOCK_MASK));

    ///* use PLL0AUDIO as clock source for ADCHS */
    CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_AUTOBLOCK(1)
        | CGU_BASE_VADC_CLK_CLK_SEL(CGU_SRC_PLL0AUDIO);


    //For Clock debugging. Connects PLL0Audio to CLK0 output
    //CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_CLK_SEL(CGU_SRC_PLL0AUDIO);

    /* ****************************************** */
    /* Disable/PowerDown unused clock/peripherals */
    /* ****************************************** */
    CREG_CREG6 |= (1<<17); // PowerDown RNG

    // CGU_BASE_SAFE_CLK = CGU_BASE_USB1_CLK_PD(1);

    // CGU_BASE_USB0_CLK is used for USB0 HS
    // CGU_BASE_M0_CLK is used
    /* Switch off USB1 clock */
    CGU_BASE_USB1_CLK = CGU_BASE_USB1_CLK_PD(1);
    // CGU_BASE_M4_CLK is used
    // CGU_BASE_SPIFI_CLK = CGU_BASE_SPIFI_CLK_PD(1);
    /* Switch off SPI clock */
    CGU_BASE_SPI_CLK = CGU_BASE_SPI_CLK_PD(1);
    /* Switch off PHY RX & TX clock */
    CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD(1);
    CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD(1);
    // CGU_BASE_APB1_CLK is used for I2C0
    // CGU_BASE_APB3_CLK is used for I2C1
    /* Switch off LCD clock */
    CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD(1);
    // CGU_BASE_ADCHS_CLK is used
    /* Switch off SDIO clock */
    CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD(1);
//    CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_PD(1);
    /* Switch off SSP1 clock */
    //CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_PD(1);
    /* Switch off UART0 to 3 clock */
    CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD(1);
    CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD(1);
    CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD(1);
    CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD(1);
    /*  Switch off OUT clocks */
    CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD(1);
    /* Reserved/Undocumented clocks power down */
    CGU_OUTCLK_21_CTRL = 1;
    CGU_OUTCLK_22_CTRL = 1;
    CGU_OUTCLK_23_CTRL = 1;
    CGU_OUTCLK_24_CTRL = 1;
    /* Switch off AUDIO clock */
    //CGU_BASE_AUDIO_CLK = CGU_BASE_AUDIO_CLK_PD(1);
    CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD(1);
    CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD(1);
    /* Switch off IDIV C,D,E disabled */
    CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD(1);
    CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD(1);
    CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD(1);
    /*
    // Power down M4 branches, but not BUS, GPIO, CREG and M0 & M4 CORE clock
    */
    //CCU1_CLK_M4_BUS_CFG &= ~(1);
    //CCU1_CLK_M4_SPIFI_CFG &= ~(1);
    //CCU1_CLK_M4_GPIO_CFG &= ~(1);
    CCU1_CLK_M4_LCD_CFG &= ~(1);
    CCU1_CLK_M4_ETHERNET_CFG &= ~(1);
    //CCU1_CLK_M4_USB0_CFG &= ~(1);
    CCU1_CLK_M4_EMC_CFG &= ~(1);
    CCU1_CLK_M4_SDIO_CFG &= ~(1);
    //CCU1_CLK_M4_DMA_CFG &= ~(1);
    //CCU1_CLK_M4_M4CORE_CFG &= ~(1);
    CCU1_CLK_M4_SCT_CFG &= ~(1);
    CCU1_CLK_M4_USB1_CFG &= ~(1);
    CCU1_CLK_M4_EMCDIV_CFG &= ~(1);
    //CCU1_CLK_M4_M0APP_CFG &= ~(1);
    //CCU1_CLK_M4_VADC_CFG &= ~(1);
    //CCU1_CLK_M4_WWDT_CFG &= ~(1);
    CCU1_CLK_M4_USART0_CFG &= ~(1);
    CCU1_CLK_M4_UART1_CFG &= ~(1);
    //CCU1_CLK_M4_SSP0_CFG &= ~(1);
    //CCU1_CLK_M4_SSP1_CFG &= ~(1);
    CCU1_CLK_M4_TIMER0_CFG &= ~(1);
    CCU1_CLK_M4_TIMER1_CFG &= ~(1);
    //CCU1_CLK_M4_SCU_CFG &= ~(1);
    //CCU1_CLK_M4_CREG_CFG &= ~(1);
    //CCU1_CLK_M4_RITIMER_CFG &= ~(1);
    CCU1_CLK_M4_USART2_CFG &= ~(1);
    CCU1_CLK_M4_USART3_CFG &= ~(1);
    CCU1_CLK_M4_TIMER2_CFG &= ~(1);
    CCU1_CLK_M4_TIMER3_CFG &= ~(1);

    CCU1_CLK_M4_QEI_CFG &= ~(1);

    //CCU1_CLK_PERIPH_SGPIO_CFG &= ~(1);
}
Ejemplo n.º 2
0
void doSpeed(){
	SETUPgout(LCD_BL_EN);
	SETUPgout(EN_1V8);
	SETUPgout(LED4);
	int mhz=102;
	while(1){
		TOGGLE(LED1);
		lcdClear(0xff);
		lcdPrint("speed: "); lcdPrint(IntToStr(mhz,3,0));lcdNl();
		lcdDisplay(); 
		switch(getInput()){
			case BTN_UP:
//				mhz=204;
//				cpu_clock_set(mhz);
#define PD0_SLEEP0_HW_ENA MMIO32(0x40042000)
#define PD0_SLEEP0_MODE   MMIO32(0x4004201C)

		PD0_SLEEP0_HW_ENA = 1; 
		PD0_SLEEP0_MODE = 0x003000AA;
		SCB_SCR|=SCB_SCR_SLEEPDEEP;

		ON(LED1);
		CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_IRC) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
		CGU_PLL1_CTRL= CGU_PLL1_CTRL_PD(1);
		CGU_PLL0USB_CTRL= CGU_PLL1_CTRL_PD(1);
		CGU_PLL0AUDIO_CTRL= CGU_PLL1_CTRL_PD(1);

		CGU_XTAL_OSC_CTRL &= ~(CGU_XTAL_OSC_CTRL_ENABLE_MASK);



#define __WFI() __asm__("wfi")
		while(1){
			TOGGLE(LED1);
			__WFI();
		};
				break;
			case BTN_DOWN:
				mhz=12;
				cpu_clock_set(mhz);
				break;
			case BTN_LEFT:
				while(1){
					cpu_clock_set(102);
					TOGGLE(LED1);
					delayNop(1000);
					cpu_clock_set(12);
					TOGGLE(LED1);
					delayNop(1000);
				};
				break;
			case BTN_RIGHT:
				TOGGLE(LCD_BL_EN);
						OFF(BY_MIX_N);
						OFF(BY_MIX);
						OFF(BY_AMP_N);
						OFF(BY_AMP);
						OFF(TX_RX_N);
						OFF(TX_RX);
						OFF(LOW_HIGH_FILT_N);
						OFF(LOW_HIGH_FILT);
							OFF(TX_AMP);
							OFF(RX_LNA);
						OFF(MIXER_EN);
						OFF(CE_VCO);
//				cpu_clock_set(mhz);
				break;
			case BTN_ENTER:

//			turnoff(&CCU1_CLK_APB3_BUS_CFG);
				turnoff(&CCU1_CLK_APB3_I2C1_CFG);
				turnoff(&CCU1_CLK_APB3_DAC_CFG);
				turnoff(&CCU1_CLK_APB3_ADC0_CFG);
				turnoff(&CCU1_CLK_APB3_ADC1_CFG);
				turnoff(&CCU1_CLK_APB3_CAN0_CFG);
//			turnoff(&CCU1_CLK_APB1_BUS_CFG);
				turnoff(&CCU1_CLK_APB1_MOTOCONPWM_CFG);
				turnoff(&CCU1_CLK_APB1_I2C0_CFG);
				turnoff(&CCU1_CLK_APB1_I2S_CFG);
				turnoff(&CCU1_CLK_APB1_CAN1_CFG);
				turnoff(&CCU1_CLK_SPIFI_CFG);
//				turnoff(&CCU1_CLK_M4_BUS_CFG);
				turnoff(&CCU1_CLK_M4_SPIFI_CFG);
//				turnoff(&CCU1_CLK_M4_GPIO_CFG);
				turnoff(&CCU1_CLK_M4_LCD_CFG);
				turnoff(&CCU1_CLK_M4_ETHERNET_CFG);
				turnoff(&CCU1_CLK_M4_USB0_CFG);
				turnoff(&CCU1_CLK_M4_EMC_CFG);
				turnoff(&CCU1_CLK_M4_SDIO_CFG);
				turnoff(&CCU1_CLK_M4_DMA_CFG);
//				turnoff(&CCU1_CLK_M4_M4CORE_CFG);
				turnoff(&CCU1_CLK_M4_SCT_CFG);
				turnoff(&CCU1_CLK_M4_USB1_CFG);
				turnoff(&CCU1_CLK_M4_EMCDIV_CFG);
				turnoff(&CCU1_CLK_M4_M0APP_CFG);
				turnoff(&CCU1_CLK_M4_VADC_CFG);
				turnoff(&CCU1_CLK_M4_WWDT_CFG);
				turnoff(&CCU1_CLK_M4_USART0_CFG);
				turnoff(&CCU1_CLK_M4_UART1_CFG);
				turnoff(&CCU1_CLK_M4_SSP0_CFG);
				turnoff(&CCU1_CLK_M4_TIMER0_CFG);
				turnoff(&CCU1_CLK_M4_TIMER1_CFG);
//				turnoff(&CCU1_CLK_M4_SCU_CFG);
//				turnoff(&CCU1_CLK_M4_CREG_CFG);
				turnoff(&CCU1_CLK_M4_RITIMER_CFG);
				turnoff(&CCU1_CLK_M4_USART2_CFG);
				turnoff(&CCU1_CLK_M4_USART3_CFG);
				turnoff(&CCU1_CLK_M4_TIMER2_CFG);
				turnoff(&CCU1_CLK_M4_TIMER3_CFG);
//			turnoff(&CCU1_CLK_M4_SSP1_CFG);
				turnoff(&CCU1_CLK_M4_QEI_CFG);
//				turnoff(&CCU1_CLK_PERIPH_BUS_CFG);
				turnoff(&CCU1_CLK_PERIPH_CORE_CFG);
				turnoff(&CCU1_CLK_PERIPH_SGPIO_CFG);
				turnoff(&CCU1_CLK_USB0_CFG);
				turnoff(&CCU1_CLK_USB1_CFG);
//			turnoff(&CCU1_CLK_SPI_CFG);
				turnoff(&CCU1_CLK_VADC_CFG);
				turnoff(&CCU2_CLK_APLL_CFG);
				turnoff(&CCU2_CLK_APB2_USART3_CFG);
				turnoff(&CCU2_CLK_APB2_USART2_CFG);
				turnoff(&CCU2_CLK_APB0_UART1_CFG);
				turnoff(&CCU2_CLK_APB0_USART0_CFG);
//			turnoff(&CCU2_CLK_APB2_SSP1_CFG);
				turnoff(&CCU2_CLK_APB0_SSP0_CFG);
				turnoff(&CCU2_CLK_SDIO_CFG);

// clkoff(& CGU_BASE_SAFE_CLK);
clkoff(& CGU_BASE_USB0_CLK);
 clkoff(& CGU_BASE_PERIPH_CLK);
clkoff(& CGU_BASE_USB1_CLK);
// clkoff(& CGU_BASE_M4_CLK);
clkoff(& CGU_BASE_SPIFI_CLK);
clkoff(& CGU_BASE_SPI_CLK);
clkoff(& CGU_BASE_PHY_RX_CLK);
clkoff(& CGU_BASE_PHY_TX_CLK);
 clkoff(& CGU_BASE_APB1_CLK);
 clkoff(& CGU_BASE_APB3_CLK);
clkoff(& CGU_BASE_LCD_CLK);
clkoff(& CGU_BASE_VADC_CLK);
clkoff(& CGU_BASE_SDIO_CLK);
clkoff(& CGU_BASE_SSP0_CLK);
 clkoff(& CGU_BASE_SSP1_CLK);
clkoff(& CGU_BASE_UART0_CLK);
clkoff(& CGU_BASE_UART1_CLK);
clkoff(& CGU_BASE_UART2_CLK);
clkoff(& CGU_BASE_UART3_CLK);
clkoff(& CGU_BASE_AUDIO_CLK);
 clkoff(& CGU_BASE_CGU_OUT0_CLK);
 clkoff(& CGU_BASE_CGU_OUT1_CLK);

//				return;
				break;
		};
	};
};
/* clock startup for Jellybean with Lemondrop attached
Configure PLL1 to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */ 
void cpu_clock_init(void)
{
	/* use IRC as clock source for APB1 (including I2C0) */
	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);

	/* use IRC as clock source for APB3 */
	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);

	//FIXME a lot of the details here should be in a CGU driver

	/* set xtal oscillator to low frequency mode */
	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;

	/* power on the oscillator and wait until stable */
	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;

	/* Wait about 100us after Crystal Power ON */
	delay(WAIT_CPU_CLOCK_INIT_DELAY);

	/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1));

	/* use XTAL_OSC as clock source for APB1 */
	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);

	/* use XTAL_OSC as clock source for APB3 */
	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);

	cpu_clock_pll1_low_speed();

	/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));

	/* use XTAL_OSC as clock source for PLL0USB */
	CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
			| CGU_PLL0USB_CTRL_AUTOBLOCK(1)
			| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
	while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK);

	/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
	/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
	CGU_PLL0USB_MDIV = 0x06167FFA;
	CGU_PLL0USB_NP_DIV = 0x00302062;
	CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD(1)
			| CGU_PLL0USB_CTRL_DIRECTI(1)
			| CGU_PLL0USB_CTRL_DIRECTO(1)
			| CGU_PLL0USB_CTRL_CLKEN(1));

	/* power on PLL0USB and wait until stable */
	CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
	while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK));

	/* use PLL0USB as clock source for USB0 */
	CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1)
			| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);

	/* use PLL0USB as clock source for IDIVA */
	/* divide by 4 */
	CGU_IDIVA_CTRL = CGU_IDIVA_CTRL_IDIV(3)
			| CGU_IDIVA_CTRL_AUTOBLOCK(1)
			| CGU_IDIVA_CTRL_CLK_SEL(CGU_SRC_PLL0USB);

	/* use IDIVA as clock source for IDIVB */
	/* divide by 2 */
	CGU_IDIVB_CTRL = CGU_IDIVB_CTRL_IDIV(1)
			| CGU_IDIVB_CTRL_AUTOBLOCK(1)
			| CGU_IDIVA_CTRL_CLK_SEL(CGU_SRC_IDIVA);

	/* Use IDIVB for CLKOUT */
	CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_AUTOBLOCK(1)
			| CGU_BASE_OUT_CLK_CLK_SEL(CGU_SRC_IDIVB);

	/* use IDIVB as clock source for USB1 */
	CGU_BASE_USB1_CLK = CGU_BASE_USB1_CLK_AUTOBLOCK(1)
			| CGU_BASE_USB1_CLK_CLK_SEL(CGU_SRC_IDIVB);

	/* Switch peripheral clock over to use PLL1 (204MHz) */
	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1)
			| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);

	/* Switch APB1 clock over to use PLL1 (204MHz) */
	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);

	/* Switch APB3 clock over to use PLL1 (204MHz) */
	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);

	CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_AUTOBLOCK(1)
			| CGU_BASE_SSP0_CLK_CLK_SEL(CGU_SRC_PLL1);

	CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_AUTOBLOCK(1)
			| CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1);
}
Ejemplo n.º 4
0
/* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */ 
void cpu_clock_init(void)
{
	/* use IRC as clock source for APB1 (including I2C0) */
	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);

	/* use IRC as clock source for APB3 */
	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);

	i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_slow_clock);

	si5351c_disable_all_outputs(&clock_gen);
	si5351c_disable_oeb_pin_control(&clock_gen);
	si5351c_power_down_all_clocks(&clock_gen);
	si5351c_set_crystal_configuration(&clock_gen);
	si5351c_enable_xo_and_ms_fanout(&clock_gen);
	si5351c_configure_pll_sources(&clock_gen);
	si5351c_configure_pll_multisynth(&clock_gen);

	/*
	 * Clocks:
	 *   CLK0 -> MAX5864/CPLD
	 *   CLK1 -> CPLD
	 *   CLK2 -> SGPIO
	 *   CLK3 -> External Clock Output (power down at boot)
	 *   CLK4 -> RFFC5072 (MAX2837 on rad1o)
	 *   CLK5 -> MAX2837 (MAX2871 on rad1o)
	 *   CLK6 -> none
	 *   CLK7 -> LPC43xx (uses a 12MHz crystal by default)
	 */

	/* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */
	si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
 	/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
	si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */

	/* MS6/CLK6 is unused. */
	/* MS7/CLK7 is unused. */

	/* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */
	sample_rate_set(10000000);

	si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL);
	// soft reset
	// uint8_t resetdata[] = { 177, 0xac };
	// si5351c_write(&clock_gen, resetdata, sizeof(resetdata));
	si5351c_reset_pll(&clock_gen);
	si5351c_enable_clock_outputs(&clock_gen);

	//FIXME disable I2C
	/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
	i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);

	/*
	 * 12MHz clock is entering LPC XTAL1/OSC input now.
	 * On HackRF One and Jawbreaker, there is a 12 MHz crystal at the LPC.
	 * Set up PLL1 to run from XTAL1 input.
	 */

	//FIXME a lot of the details here should be in a CGU driver

	/* set xtal oscillator to low frequency mode */
	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;

	/* power on the oscillator and wait until stable */
	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;

	/* Wait about 100us after Crystal Power ON */
	delay(WAIT_CPU_CLOCK_INIT_DELAY);

	/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1));

	/* use XTAL_OSC as clock source for APB1 */
	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);

	/* use XTAL_OSC as clock source for APB3 */
	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);

	cpu_clock_pll1_low_speed();

	/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
	CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));

	/* use XTAL_OSC as clock source for PLL0USB */
	CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
			| CGU_PLL0USB_CTRL_AUTOBLOCK(1)
			| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
	while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK);

	/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
	/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
	CGU_PLL0USB_MDIV = 0x06167FFA;
	CGU_PLL0USB_NP_DIV = 0x00302062;
	CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD(1)
			| CGU_PLL0USB_CTRL_DIRECTI(1)
			| CGU_PLL0USB_CTRL_DIRECTO(1)
			| CGU_PLL0USB_CTRL_CLKEN(1));

	/* power on PLL0USB and wait until stable */
	CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
	while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK));

	/* use PLL0USB as clock source for USB0 */
	CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1)
			| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);

	/* Switch peripheral clock over to use PLL1 (204MHz) */
	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1)
			| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);

	/* Switch APB1 clock over to use PLL1 (204MHz) */
	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);

	/* Switch APB3 clock over to use PLL1 (204MHz) */
	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
			| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);

	CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_AUTOBLOCK(1)
			| CGU_BASE_SSP0_CLK_CLK_SEL(CGU_SRC_PLL1);

	CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_AUTOBLOCK(1)
			| CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1);

#if (defined JAWBREAKER || defined HACKRF_ONE)
	/* Disable unused clocks */
	/* Start with PLLs */
	CGU_PLL0AUDIO_CTRL = CGU_PLL0AUDIO_CTRL_PD(1);

	/* Dividers */
	CGU_IDIVA_CTRL = CGU_IDIVA_CTRL_PD(1);
	CGU_IDIVB_CTRL = CGU_IDIVB_CTRL_PD(1);
	CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD(1);
	CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD(1);
	CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD(1);

	/* Base clocks */
	CGU_BASE_SPIFI_CLK =  CGU_BASE_SPIFI_CLK_PD(1); /* SPIFI is only used at boot */
	CGU_BASE_USB1_CLK = CGU_BASE_USB1_CLK_PD(1); /* USB1 is not exposed on HackRF */
	CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD(1);
	CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD(1);
	CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD(1);
	CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_PD(1);
	CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD(1);
	CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD(1);
	CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD(1);
	CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD(1);
	CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD(1);
	CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD(1);
	CGU_BASE_AUDIO_CLK = CGU_BASE_AUDIO_CLK_PD(1);
	CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD(1);
	CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD(1);

	/* Disable unused peripheral clocks */
	CCU1_CLK_APB1_CAN1_CFG = 0;
	CCU1_CLK_APB1_I2S_CFG = 0;
	CCU1_CLK_APB1_MOTOCONPWM_CFG = 0;
	CCU1_CLK_APB3_ADC0_CFG = 0;
	CCU1_CLK_APB3_ADC1_CFG = 0;
	CCU1_CLK_APB3_CAN0_CFG = 0;
	CCU1_CLK_APB3_DAC_CFG = 0;
	CCU1_CLK_M4_DMA_CFG = 0;
	CCU1_CLK_M4_EMC_CFG = 0;
	CCU1_CLK_M4_EMCDIV_CFG = 0;
	CCU1_CLK_M4_ETHERNET_CFG = 0;
	CCU1_CLK_M4_LCD_CFG = 0;
	CCU1_CLK_M4_QEI_CFG = 0;
	CCU1_CLK_M4_RITIMER_CFG = 0;
	CCU1_CLK_M4_SCT_CFG = 0;
	CCU1_CLK_M4_SDIO_CFG = 0;
	CCU1_CLK_M4_SPIFI_CFG = 0;
	CCU1_CLK_M4_TIMER0_CFG = 0;
	CCU1_CLK_M4_TIMER1_CFG = 0;
	CCU1_CLK_M4_TIMER2_CFG = 0;
	CCU1_CLK_M4_TIMER3_CFG = 0;
	CCU1_CLK_M4_UART1_CFG = 0;
	CCU1_CLK_M4_USART0_CFG = 0;
	CCU1_CLK_M4_USART2_CFG = 0;
	CCU1_CLK_M4_USART3_CFG = 0;
	CCU1_CLK_M4_USB1_CFG = 0;
	CCU1_CLK_M4_VADC_CFG = 0;
	// CCU1_CLK_SPIFI_CFG = 0;
	// CCU1_CLK_USB1_CFG = 0;
	// CCU1_CLK_VADC_CFG = 0;
	// CCU2_CLK_APB0_UART1_CFG = 0;
	// CCU2_CLK_APB0_USART0_CFG = 0;
	// CCU2_CLK_APB2_USART2_CFG = 0;
	// CCU2_CLK_APB2_USART3_CFG = 0;
	// CCU2_CLK_APLL_CFG = 0;
	// CCU2_CLK_SDIO_CFG = 0;
#endif

#ifdef RAD1O
	/* Disable unused clock outputs. They generate noise. */
	scu_pinmux(CLK0, SCU_CLK_IN | SCU_CONF_FUNCTION7);
	scu_pinmux(CLK2, SCU_CLK_IN | SCU_CONF_FUNCTION7);
#endif
}