/*
Configure PLL1 (Main MCU Clock) to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
This function shall be called after cpu_clock_init().
*/
void cpu_clock_pll1_max_speed(void)
{
uint32_t pll_reg;
/* Configure PLL1 to Intermediate Clock (between 90 MHz and 110 MHz) */
/* Integer mode:
FCLKOUT = M*(FCLKIN/N)
FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
*/
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 8 = 96MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(7)
| CGU_PLL1_CTRL_FBSEL(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
/* Wait before to switch to max speed */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
/* Configure PLL1 Max Speed */
/* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 17 = 204MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(9) //XXX: 16
| CGU_PLL1_CTRL_FBSEL(1)
| CGU_PLL1_CTRL_DIRECT(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
}
/*
Configure PLL1 to low speed (48MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
This function shall be called after cpu_clock_init().
This function is mainly used to lower power consumption.
*/
void cpu_clock_pll1_low_speed(void)
{
uint32_t pll_reg;
/* Configure PLL1 Clock (48MHz) */
/* Integer mode:
FCLKOUT = M*(FCLKIN/N)
FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
*/
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD_MASK | CGU_PLL1_CTRL_FBSEL_MASK | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS_MASK | /* BYPASS */
CGU_PLL1_CTRL_DIRECT_MASK | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 up to 12MHz * 4 = 48MHz. */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(3)
| CGU_PLL1_CTRL_FBSEL(1)
| CGU_PLL1_CTRL_DIRECT(1);
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK));
/* Wait a delay after switch to new frequency with Direct mode */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
}
/*
Configure PLL1 to low speed with CGU_SRC_GP_CLKIN.
Connect PLL1 to M4/M0 core, Peripheral, APB1, APB3.
Init I2C0 & I2C1.
This function is mainly used to lower power consumption.
*/
void cpu_clock_pll1_low_speed(const airspy_pll1_ls_t* const pt_airspy_pll1_ls_conf)
{
uint32_t pll_reg;
uint32_t pll1_psel;
uint32_t pll1_nsel;
uint32_t pll1_msel;
pll1_psel = pt_airspy_pll1_ls_conf->pll1_ls_psel;
pll1_nsel = pt_airspy_pll1_ls_conf->pll1_ls_nsel;
pll1_msel = pt_airspy_pll1_ls_conf->pll1_ls_msel;
/* Configure PLL1 Clock */
/* Integer mode:
FCLKOUT = M*(FCLKIN/N)
FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
*/
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD | CGU_PLL1_CTRL_FBSEL | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS | /* BYPASS */
CGU_PLL1_CTRL_DIRECT | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_GP_CLKIN)
| CGU_PLL1_CTRL_PSEL(pll1_psel)
| CGU_PLL1_CTRL_NSEL(pll1_nsel)
| CGU_PLL1_CTRL_MSEL(pll1_msel)
| CGU_PLL1_CTRL_FBSEL
| CGU_PLL1_CTRL_DIRECT;
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
}
/* clock startup for Jellybean with Lemondrop attached
Configure PLL1 to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */
void cpu_clock_init(void)
{
/* use IRC as clock source for APB1 (including I2C0) */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
/* use IRC as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
//FIXME disable I2C
/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
i2c1_init(255);
/*
* 12MHz clock is entering LPC XTAL1/OSC input now. On
* Jellybean/Lemondrop, this is a signal from the clock generator. On
* Jawbreaker, there is a 12 MHz crystal at the LPC.
* Set up PLL1 to run from XTAL1 input.
*/
//FIXME a lot of the details here should be in a CGU driver
/* set xtal oscillator to low frequency mode */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;
/* power on the oscillator and wait until stable */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;
/* Wait about 100us after Crystal Power ON */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
/* use XTAL_OSC as clock source for APB1 */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
/* use XTAL_OSC as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
cpu_clock_pll1_low_speed();
/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
/* use XTAL_OSC as clock source for PLL0USB */
CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
| CGU_PLL0USB_CTRL_AUTOBLOCK(1)
| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK);
/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
CGU_PLL0USB_MDIV = 0x06167FFA;
CGU_PLL0USB_NP_DIV = 0x00302062;
CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD(1)
| CGU_PLL0USB_CTRL_DIRECTI(1)
| CGU_PLL0USB_CTRL_DIRECTO(1)
| CGU_PLL0USB_CTRL_CLKEN(1));
/* power on PLL0USB and wait until stable */
CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK));
/* use PLL0USB as clock source for USB0 */
CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1)
| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
/* Switch peripheral clock over to use PLL1 (204MHz) */
CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1)
| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB1 clock over to use PLL1 (204MHz) */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB3 clock over to use PLL1 (204MHz) */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
///XXX: Disable ADCHS clock
CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_PD(1);
CGU_PLL0AUDIO_CTRL = CGU_PLL0AUDIO_CTRL_PD(1)
| CGU_PLL0AUDIO_CTRL_AUTOBLOCK(1)
| CGU_PLL0AUDIO_CTRL_CLK_SEL(CGU_SRC_GP_CLKIN);
while (CGU_PLL0AUDIO_STAT & CGU_PLL0AUDIO_STAT_LOCK_MASK);
/* configure PLL0AUDIO to produce xxMHz */
/* PLL Register settings (SEL_EXT=1):
Mdec=31=PLL0_MDIV[16:0] => CGU_PLL0AUDIO_MDIV
Ndec=0=PLL0_NPDIV[21:12], Pdec=21=PLL0_NPDIV[6:0] => CGU_PLL0AUDIO_NP_DIV
*/
CGU_PLL0AUDIO_MDIV = 0;
CGU_PLL0AUDIO_NP_DIV = 0;
CGU_PLL0AUDIO_CTRL |= (CGU_PLL0AUDIO_CTRL_PD(1)
| CGU_PLL0AUDIO_CTRL_SEL_EXT(1)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL0AUDIO_CTRL_CLKEN(1));
///* power on PLL0AUDIO and wait until stable */
CGU_PLL0AUDIO_CTRL &= ~CGU_PLL0AUDIO_CTRL_PD(1);
while (!(CGU_PLL0AUDIO_STAT & CGU_PLL0AUDIO_STAT_LOCK_MASK));
///* use PLL0AUDIO as clock source for ADCHS */
CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_AUTOBLOCK(1)
| CGU_BASE_VADC_CLK_CLK_SEL(CGU_SRC_PLL0AUDIO);
//For Clock debugging. Connects PLL0Audio to CLK0 output
//CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_CLK_SEL(CGU_SRC_PLL0AUDIO);
/* ****************************************** */
/* Disable/PowerDown unused clock/peripherals */
/* ****************************************** */
CREG_CREG6 |= (1<<17); // PowerDown RNG
// CGU_BASE_SAFE_CLK = CGU_BASE_USB1_CLK_PD(1);
// CGU_BASE_USB0_CLK is used for USB0 HS
// CGU_BASE_M0_CLK is used
/* Switch off USB1 clock */
CGU_BASE_USB1_CLK = CGU_BASE_USB1_CLK_PD(1);
// CGU_BASE_M4_CLK is used
// CGU_BASE_SPIFI_CLK = CGU_BASE_SPIFI_CLK_PD(1);
/* Switch off SPI clock */
CGU_BASE_SPI_CLK = CGU_BASE_SPI_CLK_PD(1);
/* Switch off PHY RX & TX clock */
CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD(1);
CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD(1);
// CGU_BASE_APB1_CLK is used for I2C0
// CGU_BASE_APB3_CLK is used for I2C1
/* Switch off LCD clock */
CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD(1);
// CGU_BASE_ADCHS_CLK is used
/* Switch off SDIO clock */
CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD(1);
// CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_PD(1);
/* Switch off SSP1 clock */
//CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_PD(1);
/* Switch off UART0 to 3 clock */
CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD(1);
CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD(1);
CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD(1);
CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD(1);
/* Switch off OUT clocks */
CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD(1);
/* Reserved/Undocumented clocks power down */
CGU_OUTCLK_21_CTRL = 1;
CGU_OUTCLK_22_CTRL = 1;
CGU_OUTCLK_23_CTRL = 1;
CGU_OUTCLK_24_CTRL = 1;
/* Switch off AUDIO clock */
//CGU_BASE_AUDIO_CLK = CGU_BASE_AUDIO_CLK_PD(1);
CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD(1);
CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD(1);
/* Switch off IDIV C,D,E disabled */
CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD(1);
CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD(1);
CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD(1);
/*
// Power down M4 branches, but not BUS, GPIO, CREG and M0 & M4 CORE clock
*/
//CCU1_CLK_M4_BUS_CFG &= ~(1);
//CCU1_CLK_M4_SPIFI_CFG &= ~(1);
//CCU1_CLK_M4_GPIO_CFG &= ~(1);
CCU1_CLK_M4_LCD_CFG &= ~(1);
CCU1_CLK_M4_ETHERNET_CFG &= ~(1);
//CCU1_CLK_M4_USB0_CFG &= ~(1);
CCU1_CLK_M4_EMC_CFG &= ~(1);
CCU1_CLK_M4_SDIO_CFG &= ~(1);
//CCU1_CLK_M4_DMA_CFG &= ~(1);
//CCU1_CLK_M4_M4CORE_CFG &= ~(1);
CCU1_CLK_M4_SCT_CFG &= ~(1);
CCU1_CLK_M4_USB1_CFG &= ~(1);
CCU1_CLK_M4_EMCDIV_CFG &= ~(1);
//CCU1_CLK_M4_M0APP_CFG &= ~(1);
//CCU1_CLK_M4_VADC_CFG &= ~(1);
//CCU1_CLK_M4_WWDT_CFG &= ~(1);
CCU1_CLK_M4_USART0_CFG &= ~(1);
CCU1_CLK_M4_UART1_CFG &= ~(1);
//CCU1_CLK_M4_SSP0_CFG &= ~(1);
//CCU1_CLK_M4_SSP1_CFG &= ~(1);
CCU1_CLK_M4_TIMER0_CFG &= ~(1);
CCU1_CLK_M4_TIMER1_CFG &= ~(1);
//CCU1_CLK_M4_SCU_CFG &= ~(1);
//CCU1_CLK_M4_CREG_CFG &= ~(1);
//CCU1_CLK_M4_RITIMER_CFG &= ~(1);
CCU1_CLK_M4_USART2_CFG &= ~(1);
CCU1_CLK_M4_USART3_CFG &= ~(1);
CCU1_CLK_M4_TIMER2_CFG &= ~(1);
CCU1_CLK_M4_TIMER3_CFG &= ~(1);
CCU1_CLK_M4_QEI_CFG &= ~(1);
//CCU1_CLK_PERIPH_SGPIO_CFG &= ~(1);
}
/*
Configure PLL1 to high speed with CGU_SRC_GP_CLKIN.
(PLL1 High Speed compliant with UM10503 Rev. 1.8 — 28 January 2014 Fig 30. BASE_M4_CLK ramp-up procedure)
Connect PLL1 to M4/M0 core, Peripheral, APB1, APB3.
*/
void cpu_clock_pll1_high_speed(const airspy_pll1_hs_t* const pt_airspy_pll1_hs_conf)
{
uint32_t pll_reg;
uint32_t pll1_psel;
uint32_t pll1_nsel;
uint32_t pll1_msel;
pll1_psel = pt_airspy_pll1_hs_conf->pll1_hs_psel;
pll1_nsel = pt_airspy_pll1_hs_conf->pll1_hs_nsel;
pll1_msel = pt_airspy_pll1_hs_conf->pll1_hs_msel;
/* Configure PLL1 to Intermediate Clock final freq / 2 (because DIRECT=1) */
/* Integer mode:
FCLKOUT = M*(FCLKIN/N)
FCCO = 2*P*FCLKOUT = 2*P*M*(FCLKIN/N)
*/
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD | CGU_PLL1_CTRL_FBSEL | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS | /* BYPASS */
CGU_PLL1_CTRL_DIRECT | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
#ifdef USE_PACKING
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_GP_CLKIN)
| CGU_PLL1_CTRL_PSEL(pll1_psel)
| CGU_PLL1_CTRL_NSEL(pll1_nsel)
| CGU_PLL1_CTRL_MSEL(4)
| CGU_PLL1_CTRL_FBSEL
| CGU_PLL1_CTRL_DIRECT;
#else
/* Set PLL1 to High Speed/2 */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_GP_CLKIN)
| CGU_PLL1_CTRL_PSEL(pll1_psel)
| CGU_PLL1_CTRL_NSEL(pll1_nsel)
| CGU_PLL1_CTRL_MSEL(pll1_msel)
| CGU_PLL1_CTRL_FBSEL;
CGU_PLL1_CTRL = pll_reg;
#endif
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
/*
Wait before to switch to max speed (at least 50us)
See UM10503 Rev1.8 Fig 30. BASE_M4_CLK ramp-up procedure Page 150 / 1420
*/
delay(WAIT_CPU_CLOCK_INIT_DELAY);
/* Configure PLL1 High Speed (DIRECT=1) */
/* Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
pll_reg = CGU_PLL1_CTRL;
/* Clear PLL1 bits */
pll_reg &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK | CGU_PLL1_CTRL_PD | CGU_PLL1_CTRL_FBSEL | /* CLK SEL, PowerDown , FBSEL */
CGU_PLL1_CTRL_BYPASS | /* BYPASS */
CGU_PLL1_CTRL_DIRECT | /* DIRECT */
CGU_PLL1_CTRL_PSEL_MASK | CGU_PLL1_CTRL_MSEL_MASK | CGU_PLL1_CTRL_NSEL_MASK ); /* PSEL, MSEL, NSEL- divider ratios */
/* Set PLL1 to HighSpeed */
pll_reg |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_GP_CLKIN)
| CGU_PLL1_CTRL_PSEL(pll1_psel)
| CGU_PLL1_CTRL_NSEL(pll1_nsel)
| CGU_PLL1_CTRL_MSEL(pll1_msel)
| CGU_PLL1_CTRL_FBSEL
| CGU_PLL1_CTRL_DIRECT;
CGU_PLL1_CTRL = pll_reg;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
}
