/** * t3_mc5_intr_handler - MC5 interrupt handler * @mc5: the MC5 handle * * The MC5 interrupt handler. */ void t3_mc5_intr_handler(struct mc5 *mc5) { adapter_t *adap = mc5->adapter; u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE); if ((cause & F_PARITYERR) && mc5->parity_enabled) { CH_ALERT(adap, "MC5 parity error\n"); mc5->stats.parity_err++; } if (cause & F_REQQPARERR) { CH_ALERT(adap, "MC5 request queue parity error\n"); mc5->stats.reqq_parity_err++; } if (cause & F_DISPQPARERR) { CH_ALERT(adap, "MC5 dispatch queue parity error\n"); mc5->stats.dispq_parity_err++; } if (cause & F_ACTRGNFULL) mc5->stats.active_rgn_full++; if (cause & F_NFASRCHFAIL) mc5->stats.nfa_srch_err++; if (cause & F_UNKNOWNCMD) mc5->stats.unknown_cmd++; if (cause & F_DELACTEMPTY) mc5->stats.del_act_empty++; if (cause & MC5_INT_FATAL) t3_fatal_err(adap); t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause); }
void t1_fatal_err(struct adapter *adapter) { if (adapter->flags & FULL_INIT_DONE) { t1_sge_stop(adapter->sge); t1_interrupts_disable(adapter); } CH_ALERT("%s: encountered fatal error, operation suspended\n", adapter->name); }
int t1_mc4_intr_handler(struct pemc4 *mc4) { adapter_t *adapter = mc4->adapter; u32 cause = t1_read_reg_4(adapter, A_MC4_INT_CAUSE); if (cause & F_MC4_CORR_ERR) { mc4->intr_cnt.corr_err++; CH_WARN("%s: MC4 correctable error at addr 0x%x, " "data 0x%x 0x%x 0x%x 0x%x 0x%x\n", adapter_name(adapter), G_MC4_CE_ADDR(t1_read_reg_4(adapter, A_MC4_CE_ADDR)), t1_read_reg_4(adapter, A_MC4_CE_DATA0), t1_read_reg_4(adapter, A_MC4_CE_DATA1), t1_read_reg_4(adapter, A_MC4_CE_DATA2), t1_read_reg_4(adapter, A_MC4_CE_DATA3), t1_read_reg_4(adapter, A_MC4_CE_DATA4)); } if (cause & F_MC4_UNCORR_ERR) { mc4->intr_cnt.uncorr_err++; CH_ALERT("%s: MC4 uncorrectable error at addr 0x%x, " "data 0x%x 0x%x 0x%x 0x%x 0x%x\n", adapter_name(adapter), G_MC4_UE_ADDR(t1_read_reg_4(adapter, A_MC4_UE_ADDR)), t1_read_reg_4(adapter, A_MC4_UE_DATA0), t1_read_reg_4(adapter, A_MC4_UE_DATA1), t1_read_reg_4(adapter, A_MC4_UE_DATA2), t1_read_reg_4(adapter, A_MC4_UE_DATA3), t1_read_reg_4(adapter, A_MC4_UE_DATA4)); } if (cause & F_MC4_ADDR_ERR) { mc4->intr_cnt.addr_err++; CH_ALERT("%s: MC4 address error\n", adapter_name(adapter)); } if (cause & MC4_INT_FATAL) t1_fatal_err(adapter); t1_write_reg_4(mc4->adapter, A_MC4_INT_CAUSE, cause); return 0; }
/* * Write a register over the TPI interface (unlocked and locked versions). */ int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value) { int tpi_busy; writel(addr, adapter->regs + A_TPI_ADDR); writel(value, adapter->regs + A_TPI_WR_DATA); writel(F_TPIWR, adapter->regs + A_TPI_CSR); tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1, TPI_ATTEMPTS, 3); if (tpi_busy) CH_ALERT("%s: TPI write to 0x%x failed\n", adapter->name, addr); return tpi_busy; }
/* * Wait until Elmer's MI1 interface is ready for new operations. */ static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg) { int attempts = 100, busy; do { u32 val; __t1_tpi_read(adapter, mi1_reg, &val); busy = val & F_MI1_OP_BUSY; if (busy) udelay(10); } while (busy && --attempts); if (busy) CH_ALERT("%s: MDIO operation timed out\n", adapter->name); return busy; }
/* * Read a register over the TPI interface (unlocked and locked versions). */ int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp) { int tpi_busy; writel(addr, adapter->regs + A_TPI_ADDR); writel(0, adapter->regs + A_TPI_CSR); tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1, TPI_ATTEMPTS, 3); if (tpi_busy) CH_ALERT("%s: TPI read from 0x%x failed\n", adapter->name, addr); else *valp = readl(adapter->regs + A_TPI_RD_DATA); return tpi_busy; }
int t1_mc3_intr_handler(struct pemc3 *mc3) { adapter_t *adapter = mc3->adapter; int cause_reg = A_MC3_INT_CAUSE; u32 cause; #ifdef CONFIG_CHELSIO_T1_1G if (!t1_is_asic(adapter)) cause_reg = FPGA_MC3_REG_INTRCAUSE; #endif cause = t1_read_reg_4(adapter, cause_reg); if (cause & F_MC3_CORR_ERR) { mc3->intr_cnt.corr_err++; CH_WARN("%s: MC3 correctable error at addr 0x%x, " "data 0x%x 0x%x 0x%x 0x%x 0x%x\n", adapter_name(adapter), G_MC3_CE_ADDR(t1_read_reg_4(adapter, A_MC3_CE_ADDR)), t1_read_reg_4(adapter, A_MC3_CE_DATA0), t1_read_reg_4(adapter, A_MC3_CE_DATA1), t1_read_reg_4(adapter, A_MC3_CE_DATA2), t1_read_reg_4(adapter, A_MC3_CE_DATA3), t1_read_reg_4(adapter, A_MC3_CE_DATA4)); } if (cause & F_MC3_UNCORR_ERR) { mc3->intr_cnt.uncorr_err++; CH_ALERT("%s: MC3 uncorrectable error at addr 0x%x, " "data 0x%x 0x%x 0x%x 0x%x 0x%x\n", adapter_name(adapter), G_MC3_UE_ADDR(t1_read_reg_4(adapter, A_MC3_UE_ADDR)), t1_read_reg_4(adapter, A_MC3_UE_DATA0), t1_read_reg_4(adapter, A_MC3_UE_DATA1), t1_read_reg_4(adapter, A_MC3_UE_DATA2), t1_read_reg_4(adapter, A_MC3_UE_DATA3), t1_read_reg_4(adapter, A_MC3_UE_DATA4)); } if (G_MC3_PARITY_ERR(cause)) { mc3->intr_cnt.parity_err++; CH_ALERT("%s: MC3 parity error 0x%x\n", adapter_name(adapter), G_MC3_PARITY_ERR(cause)); } if (cause & F_MC3_ADDR_ERR) { mc3->intr_cnt.addr_err++; CH_ALERT("%s: MC3 address error\n", adapter_name(adapter)); } if (cause & MC3_INTR_FATAL) t1_fatal_err(adapter); if (t1_is_T1B(adapter)) { /* * Workaround for T1B bug: we must write to enable register to * clear interrupts. */ t1_write_reg_4(adapter, A_MC3_INT_ENABLE, cause); /* restore enable */ t1_write_reg_4(adapter, A_MC3_INT_ENABLE, MC3_INTR_MASK); } else t1_write_reg_4(adapter, cause_reg, cause); return 0; }