// ---------------------------------------------------------------------------------------
// Gas ADC initialize setting
// Set PB2 as ADC converter
// Select APB0/8 as ADC module clock source
// ---------------------------------------------------------------------------------------
void ID_Init()
{
SYS_UnlockReg();
/* Enable EADC module clock */
CLK_EnableModuleClock(EADC_MODULE);
/* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */
CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
SYS_LockReg();
/* Configure the GPB0 - GPB3 ADC analog input pins. */
SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB0MFP_Msk;
SYS->GPB_MFPL |= SYS_GPB_MFPL_PB0MFP_EADC_CH0;
GPIO_DISABLE_DIGITAL_PATH(PB, BIT0);
/* Set the ADC internal sampling time, input mode as single-end and enable the A/D converter */
EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END);
EADC_SetInternalSampleTime(EADC, 6);
/* Configure the sample module 0 for analog input channel 1 and software trigger source.*/
EADC_ConfigSampleModule(EADC, 0, EADC_SOFTWARE_TRIGGER, 0);
/* Clear the A/D ADINT0 interrupt flag for safe */
EADC_CLR_INT_FLAG(EADC, 0x1);
/* Enable the sample module 0 interrupt. */
EADC_ENABLE_INT(EADC, 0x1);//Enable sample module A/D ADINT0 interrupt.
EADC_ENABLE_SAMPLE_MODULE_INT(EADC, 0, 0x1);//Enable sample module 0 interrupt.
}
/**
* Initializes the system.
* System control registers must be unlocked.
*/
void SYS_Init() {
// TODO: why is SYS_UnlockReg() needed? Should be already unlocked.
SYS_UnlockReg();
// HIRC clock (internal RC 22.1184MHz)
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
// HCLK clock source: HIRC, HCLK source divider: 1
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
// HXT clock (external XTAL 12MHz)
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
// Enable 72MHz optimization
FMC_EnableFreqOptimizeMode(FMC_FTCTL_OPTIMIZE_72MHZ);
// Core clock: PLL
CLK_SetCoreClock(PLL_CLOCK);
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
// SPI0 clock: PCLK0
CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, 0);
CLK_EnableModuleClock(SPI0_MODULE);
// TMR0 clock: HXT
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);
CLK_EnableModuleClock(TMR0_MODULE);
// USBD clock
CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3));
CLK_EnableModuleClock(USBD_MODULE);
// Enable USB 3.3V LDO
SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk;
// EADC clock: 72Mhz / 8
CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
CLK_EnableModuleClock(EADC_MODULE);
// Enable BOD (reset, 2.2V)
SYS_EnableBOD(SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V);
// Update system core clock
SystemCoreClockUpdate();
// Initialize dataflash
Dataflash_Init();
// Initialize I/O
Display_SetupSPI();
Button_Init();
ADC_Init();
// Initialize display
Display_Init();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock (Internal RC 22.1184MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Select HCLK clock source as HIRC and and HCLK source divider as 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Set PLL to Power-down mode and PLLSTB bit in CLK_STATUS register will be cleared by hardware.*/
CLK_DisablePLL();
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source as HXT and UART module clock divider as 1 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
/* Enable EADC module clock */
CLK_EnableModuleClock(EADC_MODULE);
/* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */
CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PD multi-function pins for UART0 RXD and TXD */
SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk);
SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);
/* Configure the GPB0 - GPB3 ADC analog input pins. */
SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk |
SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk);
SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 |
SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB3MFP_EADC_CH3);
/* Disable the GPB0 - GPB3 digital input path to avoid the leakage current. */
GPIO_DISABLE_DIGITAL_PATH(PB, 0xF);
}
void Battery_Init(void)
{
#ifdef M451
SYS_UnlockReg();
/* Enable EADC module clock */
CLK_EnableModuleClock(EADC_MODULE);
/* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */
CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
SYS_LockReg();
/* Configure the GPB0 - GPB3 ADC analog input pins. */
SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB2MFP_Msk;
SYS->GPB_MFPL |= SYS_GPB_MFPL_PB2MFP_EADC_CH2;
GPIO_DISABLE_DIGITAL_PATH(PB, 0x4);
/* Set the ADC internal sampling time, input mode as single-end and enable the A/D converter */
EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END);
EADC_SetInternalSampleTime(EADC, 6);
/* Configure the sample module 0 for analog input channel 2 and software trigger source.*/
EADC_ConfigSampleModule(EADC, 0, EADC_SOFTWARE_TRIGGER, 2);
/* Clear the A/D ADINT0 interrupt flag for safe */
EADC_CLR_INT_FLAG(EADC, 0x1);
/* Enable the sample module 0 interrupt. */
EADC_ENABLE_INT(EADC, 0x1);//Enable sample module A/D ADINT0 interrupt.
EADC_ENABLE_SAMPLE_MODULE_INT(EADC, 0, 0x1);//Enable sample module 0 interrupt.
/* Reset the ADC interrupt indicator and trigger sample module 0 to start A/D conversion */
g_u32AdcIntFlag = 0;
/* Enable battery detect circuit (PA3=1)*/
GPIO_SetMode(PA, BIT3, GPIO_MODE_OUTPUT);
PA3=1;
#else
/* TBD.. */
#endif
}
//=========================================================================
//----- (0000652C) --------------------------------------------------------
void InitDevices()
{
SYS_UnlockReg();
// Internal 22.1184MHz oscillator
CLK_EnableXtalRC( CLK_PWRCTL_HIRCEN_Msk );
CLK_WaitClockReady( CLK_STATUS_HIRCSTB_Msk );
CLK_SetHCLK( CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK( 1 ) );
// 12.000MHz external crystal
CLK_EnableXtalRC( CLK_PWRCTL_HXTEN_Msk );
CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk );
// FMC Frequency Optimisation mode <= 72MHz
FMC_EnableFreqOptimizeMode( FMC_FTCTL_OPTIMIZE_72MHZ );
// Setup PLL to 144MHz and HCLK source to PLL/2
CLK_SetCoreClock( CPU_FREQ );
// UART0 CLK = HXT/1
#if (ENABLE_UART)
CLK_EnableModuleClock( UART0_MODULE );
CLK_SetModuleClock( UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART( 1 ) );
#endif
// USB CLK = PLL/3 (48MHz)
CLK_EnableModuleClock( USBD_MODULE );
CLK_SetModuleClock( USBD_MODULE, 0, CLK_CLKDIV0_USB( 3 ) );
SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk;
// WDT CLK = LIRC/1
CLK_EnableModuleClock( WDT_MODULE );
CLK_SetModuleClock( WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0 );
// SPI0 CLK = PCLK0/1
CLK_EnableModuleClock( SPI0_MODULE );
// EADC CLK = PCLK1/8 (9MHz)
CLK_EnableModuleClock( EADC_MODULE );
CLK_SetModuleClock( EADC_MODULE, 0, CLK_CLKDIV0_EADC( 8 ) );
// CRC CLK = HCLK/1
CLK_EnableModuleClock( CRC_MODULE );
// TIMERS CLOCKS
CLK_EnableModuleClock( TMR0_MODULE );
CLK_EnableModuleClock( TMR1_MODULE );
CLK_EnableModuleClock( TMR2_MODULE );
CLK_EnableModuleClock( TMR3_MODULE );
CLK_SetModuleClock( TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0 );
CLK_SetModuleClock( TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0 );
CLK_SetModuleClock( TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HIRC, 0 );
CLK_SetModuleClock( TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_HXT, 0 );
// Enable battery voltage sampling by ADC
SYS->IVSCTL |= SYS_IVSCTL_VBATUGEN_Msk;
// ADC reference voltage
SYS->VREFCTL = SYS_VREFCTL_VREF_2_56V;
// Brown-out detector; interrupts under 2.2V
SYS_EnableBOD( SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V );
// Update clock data
SystemCoreClockUpdate();
WDT_Open( WDT_TIMEOUT_2POW18, WDT_RESET_DELAY_18CLK, TRUE, FALSE );
SYS_LockReg();
}
/* ---------------------------------------------------------------------------------------*/
void Battery_Init()
{
SYS_UnlockReg();
/* Enable EADC module clock */
CLK_EnableModuleClock(EADC_MODULE);
/* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */
CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
SYS_LockReg();
/* Configure the GPB0 - GPB3 ADC analog input pins. */
SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB1MFP_Msk;
SYS->GPB_MFPL |= SYS_GPB_MFPL_PB1MFP_EADC_CH1;
GPIO_DISABLE_DIGITAL_PATH(PB, BIT1);
//LED
SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA2MFP_Msk);
SYS->GPA_MFPL |= SYS_GPA_MFPL_PA2MFP_GPIO;
GPIO_SetMode(PA,BIT2,GPIO_MODE_OUTPUT);
PA2 = 1;
/* Set the ADC internal sampling time, input mode as single-end and enable the A/D converter */
EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END);
EADC_SetInternalSampleTime(EADC, 6);
/* Configure the sample module 0 for analog input channel 1 and software trigger source.*/
EADC_ConfigSampleModule(EADC, 1, EADC_SOFTWARE_TRIGGER, 1);
/* Clear the A/D ADINT0 interrupt flag for safe */
EADC_CLR_INT_FLAG(EADC, 0x2);
/* Enable the sample module 0 interrupt. */
EADC_ENABLE_INT(EADC, 0x2);//Enable sample module A/D ADINT0 interrupt.
EADC_ENABLE_SAMPLE_MODULE_INT(EADC, 1, 0x2);//Enable sample module 0 interrupt.
BatDev.DevDesc.DevDesc_leng = 26; //Report descriptor
BatDev.DevDesc.RptDesc_leng = 36; //Report descriptor
BatDev.DevDesc.InRptLeng = 5; //Input report
BatDev.DevDesc.OutRptLeng = 0; //Output report
BatDev.DevDesc.GetFeatLeng = 6; //Get feature
BatDev.DevDesc.SetFeatLeng = 6; //Set feature
BatDev.DevDesc.CID = 0; //manufacturers ID
BatDev.DevDesc.DID = 0; //Product ID
BatDev.DevDesc.PID = 0; //Device firmware revision
BatDev.DevDesc.UID = 0; //Device Class type
BatDev.DevDesc.UCID = 0; //reserve
/* Feature */
BatDev.Feature.data1.minimum = 0; //Sleep period
BatDev.Feature.data1.maximum = 1024;
BatDev.Feature.data1.value = 100;
BatDev.Feature.data2.minimum = 0; //Battery alerm value
BatDev.Feature.data2.maximum = 100;
BatDev.Feature.data2.value = 50;
BatDev.Feature.arg[0] = 1;
BatDev.Feature.arg[1] = 2;
BatDev.Feature.datalen[0] = 2;
BatDev.Feature.datalen[1] = 2;
BatDev.Feature.dataNum = 2;
/* Input */
BatDev.Input.data1.minimum = 0; //Battery value
BatDev.Input.data1.maximum = 100;
BatDev.Input.data1.value = 100;
BatDev.Input.data2.minimum = 0; //Over flag
BatDev.Input.data2.maximum = 1;
BatDev.Input.data2.value = 0;
BatDev.Input.arg[0] = 1;
BatDev.Input.arg[1] = 2;
BatDev.Input.datalen[0] = 2;
BatDev.Input.datalen[1] = 1;
BatDev.Input.dataNum = 2;
/* Output */
BatDev.Output.dataNum = 0;
}
