//========================================================================= __myevic__ void LightSleep() { // Switch Core Clock to HXT/3 (4MHz) CLK_SetHCLK( CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK( 3 ) ); // Update clock data SystemCoreClockUpdate(); // Switch off the PLL Clock & the HIRC CLK_DisablePLL(); CLK_DisableXtalRC( CLK_PWRCTL_HIRCEN_Msk ); // Disable Clocks of Modules using HCLK/HXT or LIRC CLK_DisableModuleClock( PWM0_MODULE ); CLK_DisableModuleClock( SPI0_MODULE ); CLK_DisableModuleClock( CRC_MODULE ); #if (ENABLE_UART) CLK_DisableModuleClock( UART0_MODULE ); #endif gFlags.wake_up = 0; do { CLK_Idle(); } while ( !gFlags.wake_up ); // Wake up the HIRC CLK_EnableXtalRC( CLK_PWRCTL_HIRCEN_Msk ); CLK_WaitClockReady( CLK_STATUS_HIRCSTB_Msk ); // Wake up the PLL CLK_SetCoreClock( CPU_FREQ ); // Update clock data SystemCoreClockUpdate(); // Wake up Modules #if (ENABLE_UART) CLK_EnableModuleClock( UART0_MODULE ); #endif CLK_EnableModuleClock( PWM0_MODULE ); CLK_EnableModuleClock( SPI0_MODULE ); CLK_EnableModuleClock( CRC_MODULE ); }
void I2C0_Close(void) { /* Disable I2C0 interrupt and clear corresponding NVIC bit */ I2C_DisableInt(I2C0); NVIC_DisableIRQ(I2C0_IRQn); /* Disable I2C0 and close I2C0 clock */ I2C_Close(I2C0); CLK_DisableModuleClock(I2C0_MODULE); }
void us_ticker_free(void) { /* Disable interrupt */ NVIC_DisableIRQ(TIMER_MODINIT.irq_n); /* Disable IP clock */ CLK_DisableModuleClock(TIMER_MODINIT.clkidx); ticker_inited = 0; }
/*---------------------------------------------------------------------------------------------------------*/ int main(void) { const uint8_t acCRCSrcPattern[] = {0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38}; uint32_t i, u32TargetChecksum = 0xA12B, u32CalChecksum = 0; uint16_t *p16SrcAddr; /* Unlock protected registers */ SYS_UnlockReg(); /* Init System, peripheral clock and multi-function I/O */ SYS_Init(); /* Lock protected registers */ SYS_LockReg(); /* Init UART0 for printf */ UART0_Init(); printf("\n\nCPU @ %d Hz\n", SystemCoreClock); printf("+---------------------------------------------+\n"); printf("| CRC-CCITT Polynomial Mode Sample Code |\n"); printf("+---------------------------------------------+\n\n"); printf("# Calculate [0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38] CRC-CCITT checksum value.\n"); printf(" - Seed value is 0xFFFF \n"); printf(" - CPU write data length is 16-bit \n"); printf(" - Checksum complement disable \n"); printf(" - Checksum reverse disable \n"); printf(" - Write data complement disable \n"); printf(" - Write data reverse disable \n"); printf(" - Checksum should be 0x%X \n\n", u32TargetChecksum); /* Configure CRC controller for CRC-CCITT CPU mode */ CRC_Open(CRC_CCITT, 0, 0xFFFF, CRC_CPU_WDATA_16); /* Convert 16-bit source data */ p16SrcAddr = (uint16_t *)acCRCSrcPattern; /* Start to execute CRC-CCITT operation */ for(i = 0; i < sizeof(acCRCSrcPattern) / 2; i++) { CRC_WRITE_DATA((p16SrcAddr[i] & 0xFFFF)); } /* Get CRC-CCITT checksum value */ u32CalChecksum = CRC_GetChecksum(); printf("CRC checksum is 0x%X ... %s.\n", u32CalChecksum, (u32CalChecksum == u32TargetChecksum) ? "PASS" : "FAIL"); /* Disable CRC function */ CLK_DisableModuleClock(CRC_MODULE); while(1); }
void can_free(can_t *obj) { const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == obj->can); // Reset this module SYS_ResetModule(modinit->rsetidx); CLK_DisableModuleClock(modinit->clkidx); }
/* As crypto init counter changes from 1 to 0: * * 1. Disable crypto interrupt * 2. Disable crypto clock */ void crypto_uninit(void) { core_util_critical_section_enter(); if (crypto_init_counter == 0) { core_util_critical_section_exit(); error("Crypto clock enable counter would underflow (< 0)"); } core_util_atomic_decr_u16(&crypto_init_counter, 1); if (crypto_init_counter == 0) { NVIC_DisableIRQ(CRPT_IRQn); SYS_UnlockReg(); // Unlock protected register CLK_DisableModuleClock(CRPT_MODULE); SYS_LockReg(); // Lock protected register } core_util_critical_section_exit(); }
/*---------------------------------------------------------------------------------------------------------*/ int32_t main(void) { /* Unlock protected registers */ SYS_UnlockReg(); /* Init System, IP clock and multi-function I/O */ SYS_Init(); /* Lock protected registers */ SYS_LockReg(); /* Init UART0 for printf */ UART0_Init(); /*---------------------------------------------------------------------------------------------------------*/ /* SAMPLE CODE */ /*---------------------------------------------------------------------------------------------------------*/ printf("\nSystem clock rate: %d Hz", SystemCoreClock); /* EADC function test */ EADC_FunctionTest(); /* Reset EADC module */ SYS_ResetModule(EADC_RST); /* Disable EADC IP clock */ CLK_DisableModuleClock(EADC_MODULE); /* Disable External Interrupt */ NVIC_DisableIRQ(ADC00_IRQn); printf("Exit EADC sample code\n"); while(1); }
/** * @brief Disable frequency output function * @param None * @return None * @details This function disable frequency output function. */ void CLK_DisableCKO(void) { /* Disable CKO clock source */ CLK_DisableModuleClock(FDIV_MODULE); }