Ejemplo n.º 1
0
int serial_init (void)
{
	serial_setgpio();

	OUTREG8( (DEBUG_UART_BASE + UART_UIER_OFFSET), 0 );
	CLRREG8( (DEBUG_UART_BASE + UART_UFCR_OFFSET), UFCR_UME );	
	CLRREG8( (DEBUG_UART_BASE + UART_UISR_OFFSET), (UISR_RCVEIR|UISR_XMITIR) );
	SETREG8( (DEBUG_UART_BASE + UART_ULCR_OFFSET), (ULCR_WLS_8BITS|ULCR_SBLS_1BIT) );
	serial_setbrg();
	SETREG8( (DEBUG_UART_BASE + UART_UFCR_OFFSET), (UFCR_FME | UFCR_RFRT | UFCR_TFRT | UFCR_UME | UFCR_RDTR_15) );

	return 0;
}
Ejemplo n.º 2
0
void serial_setbrg (void)
{	
	unsigned short UART_DIVISOR_LATCH = DEVICE_CLOCK / 16 / DEBUG_UART_BAUDRATE;
	SETREG8( (DEBUG_UART_BASE + UART_ULCR_OFFSET), ULCR_DLAB );	
	OUTREG8( (DEBUG_UART_BASE + UART_UDLLR_OFFSET), UART_DIVISOR_LATCH & 0xFF );
	OUTREG8( (DEBUG_UART_BASE + UART_UDLHR_OFFSET), (UART_DIVISOR_LATCH >> 8) & 0xFF );
	CLRREG8( (DEBUG_UART_BASE + UART_ULCR_OFFSET), ULCR_DLAB );
}
Ejemplo n.º 3
0
//------------------------------------------------------------------------------
//
//  Function:  BSPIntrDoneIrq
//
//  This function is called from OALIntrDoneIrq to finish interrupt on
//  secondary interrupt controller.
//
UINT32 BSPIntrDoneIrq(UINT32 irq)
{
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDoneIrq(%d)\r\n", irq));

    // Secondary IRQ are using IRQ_GPIO16 and above
    if (irq < IRQ_PIC_0) goto cleanUp;

    // Enable interrupt on appropriate PIC
    if (irq < IRQ_PIC_8) {
        CLRREG8(&g_pPIC1Regs->mask, 1 << (irq - IRQ_PIC_0));
    } else {
        CLRREG8(&g_pPIC2Regs->mask, 1 << (irq - IRQ_PIC_8));
    }
    
    // IRQ_GPIO5 is used for cascade
    irq = IRQ_INTC;
    
cleanUp:
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrDoneIrq(irq = %d)\r\n", irq));
    return irq;
}
Ejemplo n.º 4
0
//------------------------------------------------------------------------------
//
//  Function:  BSPIntrInit
//
//  This function is called from OALIntrInit to initialize secondary interrupt
//  controller.
//
BOOL BSPIntrInit()
{
    UINT8 *pPIC1Edge, *pPIC2Edge;
    UINT32 irq;
    
    OALMSG(OAL_INTR&&OAL_FUNC, (L"+BSPIntrInit\r\n"));

    // Add static mapping for on chip devices...
    OALIntrStaticTranslate(SYSINTR_FIRMWARE + 0, IRQ_UART1);   // UART1

    // Add GPIO static mapping for RTC alarm
    OALIntrStaticTranslate(SYSINTR_RTC_ALARM, IRQ_GPIO);
    // And enable it (it will not occur until it is set in OEMSetAlarmTime)
    irq = IRQ_GPIO; OALIntrEnableIrqs(1, &irq);


    // Get and save uncached virtual addresses for VRC5477 and PIC1/PIC2
    g_pVRC5477Regs = OALPAtoUA(VRC5477_REG_PA);
    g_pPIC1Regs = OALPAtoUA(BSP_REG_PA_M1535_PIC1);
    g_pPIC2Regs = OALPAtoUA(BSP_REG_PA_M1535_PIC2);

    // M1535+ INTR uses positive logic (active on high), set VRC5477
    CLRPORT32(&g_pVRC5477Regs->INTPPES0, 1 << 4);

    // We have to enable PCI interrupts
    irq = IRQ_INTA; OALIntrEnableIrqs(1, &irq);
    irq = IRQ_INTB; OALIntrEnableIrqs(1, &irq);
    irq = IRQ_INTC; OALIntrEnableIrqs(1, &irq);
    irq = IRQ_INTD; OALIntrEnableIrqs(1, &irq);

    // PIC1/PIC2 edge registers are needed only for initialization
    pPIC1Edge = OALPAtoUA(BSP_REG_PA_M1535_EDGE1);
    pPIC2Edge = OALPAtoUA(BSP_REG_PA_M1535_EDGE2);
    
    // Initialize the 8259 PIC1
    OUTREG8(&g_pPIC1Regs->ctrl, 0x11);          // ICW1, cascade & ICW4
    OUTREG8(&g_pPIC1Regs->mask, IRQ_PIC_0);     // ICW2, vector to 32
    OUTREG8(&g_pPIC1Regs->mask, 0x04);          // ICW3, slave on IRQ 2
    OUTREG8(&g_pPIC1Regs->mask, 0x01);          // ICW4, normal EOI
    OUTREG8(&g_pPIC1Regs->ctrl, 0x0B);          // OCW2, read IS register
    OUTREG8(&g_pPIC1Regs->mask, 0xFF);          // OCW1, all disabled
    
    // Now initialize the 8259 PIC2
    OUTREG8(&g_pPIC2Regs->ctrl, 0x11);          // ICW1, cascade & ICW4
    OUTREG8(&g_pPIC2Regs->mask, IRQ_PIC_8);     // ICW2, vector to 40
    OUTREG8(&g_pPIC2Regs->mask, 0x02);          // ICW3, we are IRQ 2
    OUTREG8(&g_pPIC2Regs->mask, 0x01);          // ICW4, normal EOI
    OUTREG8(&g_pPIC2Regs->ctrl, 0x0B);          // OCW2, read IS register
    OUTREG8(&g_pPIC2Regs->mask, 0xFF);          // OCW1, all disabled

    // IRQ0-IRQ7 Edge sensitive(IRQ2 cannot be set to level sensitive)
    OUTREG8(pPIC1Edge, 0x00);

    // IRQ9&IRQ11 level (USB host, PCI INTC), other edge sensitive
    OUTREG8(pPIC2Edge, 0x0A);

    // Enable interrupt from PIC2 on PIC1
    CLRREG8(&g_pPIC1Regs->mask, 1 << 2);

    // Set static interrupt mappings for legacy devices
    
    OALIntrStaticTranslate(SYSINTR_FIRMWARE + 8, IRQ_PIC_1);    // keyboard
    OALIntrStaticTranslate(SYSINTR_FIRMWARE + 9, IRQ_PIC_12);   // mouse

    // We are done    
    OALMSG(OAL_INTR&&OAL_FUNC, (L"-BSPIntrInit(rc = 1)\r\n"));
    return TRUE;
}