/*
* Update an RCG with a new configuration. This may include a new M, N, or D
* value, source selection or pre-divider value.
*
*/
static void rcg_update_config(struct rcg_clk *rcg)
{
u32 cmd_rcgr_regval, count;
cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg));
cmd_rcgr_regval |= CMD_RCGR_CONFIG_UPDATE_BIT;
writel_relaxed(cmd_rcgr_regval, CMD_RCGR_REG(rcg));
/* Wait for update to take effect */
for (count = UPDATE_CHECK_MAX_LOOPS; count > 0; count--) {
if (!(readl_relaxed(CMD_RCGR_REG(rcg)) &
CMD_RCGR_CONFIG_UPDATE_BIT))
return;
udelay(1);
}
WARN(count == 0, "%s: rcg didn't update its configuration.",
rcg->c.dbg_name);
}
static struct clk *_rcg_clk_get_parent(struct rcg_clk *rcg, int has_mnd)
{
u32 n_regval = 0, m_regval = 0, d_regval = 0;
u32 cfg_regval;
struct clk_freq_tbl *freq;
u32 cmd_rcgr_regval;
cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg));
if (cmd_rcgr_regval & CMD_RCGR_CONFIG_DIRTY_MASK)
return NULL;
if (has_mnd) {
m_regval = readl_relaxed(M_REG(rcg));
n_regval = readl_relaxed(N_REG(rcg));
d_regval = readl_relaxed(D_REG(rcg));
n_regval |= (n_regval >> 8) ? BM(31, 16) : BM(31, 8);
d_regval |= (d_regval >> 8) ? BM(31, 16) : BM(31, 8);
}
cfg_regval = readl_relaxed(CFG_RCGR_REG(rcg));
cfg_regval &= CFG_RCGR_SRC_SEL_MASK | CFG_RCGR_DIV_MASK
| MND_MODE_MASK;
has_mnd = (has_mnd) &&
((cfg_regval & MND_MODE_MASK) == MND_DUAL_EDGE_MODE_BVAL);
cfg_regval &= ~MND_MODE_MASK;
for (freq = rcg->freq_tbl; freq->freq_hz != FREQ_END; freq++) {
if (freq->div_src_val != cfg_regval)
continue;
if (has_mnd) {
if (freq->m_val != m_regval)
continue;
if (freq->n_val != n_regval)
continue;
if (freq->d_val != d_regval)
continue;
}
break;
}
if (freq->freq_hz == FREQ_END)
return NULL;
rcg->current_freq = freq;
return freq->src_clk;
}
static enum handoff _rcg_clk_handoff(struct rcg_clk *rcg)
{
u32 cmd_rcgr_regval;
if (rcg->current_freq && rcg->current_freq->freq_hz != FREQ_END)
rcg->c.rate = rcg->current_freq->freq_hz;
/* Is the root enabled? */
cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg));
if ((cmd_rcgr_regval & CMD_RCGR_ROOT_STATUS_BIT))
return HANDOFF_DISABLED_CLK;
return HANDOFF_ENABLED_CLK;
}
static struct clk *_rcg_clk_get_parent(struct rcg_clk *rcg, int has_mnd)
{
u32 n_regval = 0, m_regval = 0, d_regval = 0;
u32 cfg_regval;
struct clk_freq_tbl *freq;
u32 cmd_rcgr_regval;
/* Is there a pending configuration? */
cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg));
if (cmd_rcgr_regval & CMD_RCGR_CONFIG_DIRTY_MASK)
return NULL;
/* Get values of m, n, d, div and src_sel registers. */
if (has_mnd) {
m_regval = readl_relaxed(M_REG(rcg));
n_regval = readl_relaxed(N_REG(rcg));
d_regval = readl_relaxed(D_REG(rcg));
/*
* The n and d values stored in the frequency tables are sign
* extended to 32 bits. The n and d values in the registers are
* sign extended to 8 or 16 bits. Sign extend the values read
* from the registers so that they can be compared to the
* values in the frequency tables.
*/
n_regval |= (n_regval >> 8) ? BM(31, 16) : BM(31, 8);
d_regval |= (d_regval >> 8) ? BM(31, 16) : BM(31, 8);
}
cfg_regval = readl_relaxed(CFG_RCGR_REG(rcg));
cfg_regval &= CFG_RCGR_SRC_SEL_MASK | CFG_RCGR_DIV_MASK
| MND_MODE_MASK;
/* If mnd counter is present, check if it's in use. */
has_mnd = (has_mnd) &&
((cfg_regval & MND_MODE_MASK) == MND_DUAL_EDGE_MODE_BVAL);
/*
* Clear out the mn counter mode bits since we now want to compare only
* the source mux selection and pre-divider values in the registers.
*/
cfg_regval &= ~MND_MODE_MASK;
/* Figure out what rate the rcg is running at */
for (freq = rcg->freq_tbl; freq->freq_hz != FREQ_END; freq++) {
if (freq->div_src_val != cfg_regval)
continue;
if (has_mnd) {
if (freq->m_val != m_regval)
continue;
if (freq->n_val != n_regval)
continue;
if (freq->d_val != d_regval)
continue;
}
break;
}
/* No known frequency found */
if (freq->freq_hz == FREQ_END)
return NULL;
rcg->current_freq = freq;
return freq->src_clk;
}
