/* ===================================================================*/
LDD_TDeviceData* ACompLdd1_Init(LDD_TUserData *UserDataPtr)
{
ACompLdd1_TDeviceData *DeviceDataPtr; /* LDD device structure */
/* Allocate HAL device structure */
/* {FreeRTOS RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPtr = &DeviceDataPtr__DEFAULT_RTOS_ALLOC;
DeviceDataPtr->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPtr->EventMask = 0x00U; /* Store mask of enabled event */
/* SIM_SCGC4: CMP=1 */
SIM_SCGC4 |= SIM_SCGC4_CMP_MASK;
/* PORTC_PCR2: ISF=0,MUX=0 */
PORTC_PCR2 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* CMP1_CR1: SE=0,WE=0,??=0,PMODE=0,INV=0,COS=0,OPE=0,EN=0 */
CMP1_CR1 = 0x00U; /* Disable comparator and sampling */
/* CMP1_MUXCR: ??=0,??=0,PSEL=2,MSEL=0 */
CMP1_MUXCR = (CMP_MUXCR_PSEL(0x02) | CMP_MUXCR_MSEL(0x00)); /* Initialize inputs */
/* CMP1_FPR: FILT_PER=0 */
CMP1_FPR = CMP_FPR_FILT_PER(0x00); /* Disable filter */
/* CMP1_CR0: ??=0,FILTER_CNT=0,??=0,??=0,HYSTCTR=0 */
CMP1_CR0 = (CMP_CR0_FILTER_CNT(0x00) | CMP_CR0_HYSTCTR(0x00)); /* Reset filter */
/* CMP1_FPR: FILT_PER=0 */
CMP1_FPR = CMP_FPR_FILT_PER(0x00); /* Set filter period */
/* CMP1_SCR: ??=0,DMAEN=0,??=0,IER=0,IEF=0,CFR=1,CFF=1,COUT=0 */
CMP1_SCR = (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* Set SC register and clear flags */
/* CMP1_CR1: SE=0,WE=0,??=0,PMODE=0,INV=0,COS=0,OPE=0,EN=1 */
CMP1_CR1 = CMP_CR1_EN_MASK;
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ACompLdd1_ID,DeviceDataPtr);
return ((LDD_TDeviceData*)DeviceDataPtr); /* Return pointer to the data data structure */
}
void CCD_Init(){
int i=0;
DAC_Init();
SIM->SCGC4 |= SIM_SCGC4_CMP_MASK;
PORTC->PCR[7] = PORT_PCR_MUX(0); //COMPARATOR MUX
PTC->PDDR &= ~0X07;
CMP0->CR1 = 0X10; // 先关闭模块及其使能
CMP0->CR0 |= CMP_CR0_FILTER_CNT(4); // 先将滤波器count置零
CMP0->FPR = 0X02; // 滤波周期（待定）= TPD + (CR0[FILTER_CNT] *TSAMPLE) + Tper
CMP0->SCR = CMP_SCR_IER_MASK|CMP_SCR_IEF_MASK|CMP_SCR_CFR_MASK|CMP_SCR_CFF_MASK; // 开启上升下降沿中断，禁止DMA方式
CMP0->MUXCR = 0XCD; // 正反向复用使能，正向输入IN1(VEDIO)，反向输入IN5（DAC)
CMP0->CR0 |= 0X40; // 四次连续采样相同则输出
CMP0->CR1 = 0X11; // ,SE WE禁止模块使能，高速比较模式，结果不翻转，输出为COUT，输出引脚禁止
CMOS_Temp_Index=0;
CMOS_Data_Index=0;
CMOS_Invalid_Line_Count=0;
CMOS_Last_MidLine = CMOS_POINT_PER_LINE/2;
CMOS_Data[0][1]=3200/2; // intialize the first midline
CMOS_Sample_Flag = 0;
enable_irq(59);
for(i;i<LINES_PER_FIELD;i++){
CMOS_Data[i][0]=0;
CMOS_Data[i][1]=0;
CMOS_Data[i][2]=0;
}
}
void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
{
assert(NULL != config);
uint8_t tmp8;
#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
/* Choose the clock source for sampling. */
if (config->enableSample)
{
base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */
}
else
{
base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */
}
#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
/* Set the filter count. */
tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK;
tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount);
base->CR0 = tmp8;
/* Set the filter period. It is used as the divider to bus clock. */
base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
}
/*******************************************************************************
* Enable Driver
*******************************************************************************/
void SnoozeCompare::enableDriver( void ) {
if ( mode == RUN_LP ) { return; }
if ( mode == VLPW || mode == VLPS ) {
IRQ_NUMBER_t IRQ_CMP;
switch (pin) {
case 11:
IRQ_CMP = IRQ_CMP0;
break;
#if defined(KINETISK)
case 9:
IRQ_CMP = IRQ_CMP1;
break;
case 4:
IRQ_CMP = IRQ_CMP2;
break;
#endif
default:
IRQ_CMP = IRQ_CMP;
return;
}
return_priority = NVIC_GET_PRIORITY( IRQ_CMP );//get current priority
int priority = nvic_execution_priority( );// get current priority
// if running from handler mode set priority higher than current handler
priority = ( priority < 256 ) && ( ( priority - 16 ) > 0 ) ? priority - 16 : 128;
NVIC_SET_PRIORITY( IRQ_CMP, priority );//set priority to new level
__disable_irq( );
return_cmp_irq = _VectorsRam[IRQ_CMP+16];// save prev isr
attachInterruptVector( IRQ_CMP, wakeupIsr );
__enable_irq( );
}
if ( SIM_SCGC4 & SIM_SCGC4_CMP ) SIM_SCGC4_clock_active = true;
else SIM_SCGC4 |= SIM_SCGC4_CMP;
CR0 = *cmpx_cr0;
CR1 = *cmpx_cr1;
SCR = *cmpx_scr;
FPR = *cmpx_fpr;
MUXCR = *cmpx_muxcr;
DACCR = *cmpx_daccr;
uint8_t _pin = 0;
*cmpx_cr0 = 0;
*cmpx_cr1 = 0;
*cmpx_scr = 0;
#if defined(__MKL26Z64__) || defined(__MK66FX1M0__)
if ( SIM_SCGC5 & SIM_SCGC5_LPTIMER ) SIM_SCGC5_clock_active = true;
else SIM_SCGC5 |= SIM_SCGC5_LPTIMER;
PSR = LPTMR0_PSR;
CMR = LPTMR0_CMR;
CSR = LPTMR0_CSR;
#endif
if ( pin == 11 ) {
if ( mode >= LLS ) llwu_configure_modules_mask( LLWU_CMP0_MOD );
return_core_pin_config[0] = CORE_PIN11_CONFIG;
CORE_PIN11_CONFIG = PORT_PCR_MUX( 0 );
_pin = 0x00;
}
else if ( pin == 4 ) {
#if defined(KINETISK)
if ( mode >= LLS ) llwu_configure_modules_mask( LLWU_CMP2_MOD );
return_core_pin_config[1] = CORE_PIN4_CONFIG;
CORE_PIN4_CONFIG = PORT_PCR_MUX( 0 );
_pin = 0x01;
#else
return;
#endif
}
else if ( pin == 9 ) {
#if defined(KINETISK)
if ( mode >= LLS ) llwu_configure_modules_mask( LLWU_CMP1_MOD );
return_core_pin_config[2] = CORE_PIN9_CONFIG;
CORE_PIN9_CONFIG = PORT_PCR_MUX( 0 );
_pin = 0x01;
#else
return;
#endif
}
// save if isr is already enabled and enable isr if not
if ( mode == VLPW || mode == VLPS ) {
IRQ_NUMBER_t IRQ_CMP;
switch (pin) {
case 11:
IRQ_CMP = IRQ_CMP0;
break;
#if defined(KINETISK)
case 9:
IRQ_CMP = IRQ_CMP1;
break;
case 4:
IRQ_CMP = IRQ_CMP2;
break;
#endif
default:
IRQ_CMP = IRQ_CMP;
return;
}
return_isr_enabled = NVIC_IS_ENABLED( IRQ_CMP );
if ( return_isr_enabled == 0 ) NVIC_ENABLE_IRQ( IRQ_CMP );
}
// setup compare
*cmpx_cr0 = CMP_CR0_FILTER_CNT( 0x07 );
if ( type == CHANGE ) *cmpx_scr = CMP_SCR_CFF | CMP_SCR_CFR | CMP_SCR_IEF | CMP_SCR_IER;
else if ( type == RISING || type == HIGH ) *cmpx_scr = CMP_SCR_CFF | CMP_SCR_CFR | CMP_SCR_IER;
else if ( type == FALLING || type == LOW ) *cmpx_scr = CMP_SCR_CFF | CMP_SCR_CFR | CMP_SCR_IEF;
else return;
uint8_t tap = ( threshold_crossing/0.0515625 ) - 1;
*cmpx_fpr = 0x00;
*cmpx_muxcr = CMP_MUXCR_MSEL( 0x07 ) | CMP_MUXCR_PSEL( _pin );
*cmpx_daccr = CMP_DACCR_DACEN | CMP_DACCR_VRSEL | CMP_DACCR_VOSEL( tap );
#if defined(__MKL26Z64__) || defined(__MK66FX1M0__)
// compare needs lptmr to operate in low power with LC, 3.6
*cmpx_cr1 = CMP_CR1_EN | CMP_CR1_TRIGM;
SIM_SCGC5 |= SIM_SCGC5_LPTIMER;
LPTMR0_CSR = 0;
LPTMR0_PSR = LPTMR_PSR_PBYP | LPTMR_PSR_PCS( LPTMR_LPO );//LPO Clock
LPTMR0_CMR = 1;
LPTMR0_CSR = LPTMR_CSR_TEN | LPTMR_CSR_TCF;
#else
*cmpx_cr1 = CMP_CR1_EN;
#endif
}
