void modulo1(int nGpio){
int num;
switch(nGpio){
case GPIO_0 ... GPIO_7:
GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(nGpio), CONTROL_CONF_MUXMODE(7));
break;
case GPIO_12 ... GPIO_15:
GPIOPinMuxSetup(CONTROL_CONF_GPMC_A(7), CONTROL_CONF_MUXMODE(7));
break;
case GPIO_8 ... GPIO_11:
selectUART(nGpio);
break;
case GPIO_16 ... GPIO_27:
num = nGpio - 16;
GPIOPinMuxSetup(CONTROL_CONF_GPMC_A(num), CONTROL_CONF_MUXMODE(7));
break;
case GPIO_28:
GPIOPinMuxSetup(CONTROL_CONF_GPMC_BE1N, CONTROL_CONF_MUXMODE(7));
break;
case GPIO_29 ... GPIO_31:
selectCSN(nGpio);
break;
}
}
unsigned int GPIO1Pin20PinMuxSetup(void)
{
unsigned int profile = 0;
unsigned int status = FALSE;
profile = EVMProfileGet();
switch(profile)
{
/* Fall through for cases 0, 1, 2, 4, 5 and 6. */
case 0:
case 1:
case 2:
case 4:
case 5:
case 6:
case 7:
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4)) =
CONTROL_CONF_MUXMODE(7);
status = TRUE;
break;
case 3:
default:
break;
}
return status;
}
unsigned int GPIO1Pin16PinMuxSetup(void)
{
unsigned int profile = 0;
unsigned int status = FALSE;
profile = EVMProfileGet();
switch(profile)
{
/* Fall through for cases 0 and 3. */
case 0:
case 3:
case 5:
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) =
(CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RXACTIVE |
CONTROL_CONF_MUXMODE(7));
status = TRUE;
break;
/* Fall through for cases 1, 2, 4, 6 and 7. */
case 1:
case 2:
case 4:
case 6:
case 7:
default:
break;
}
return status;
}
static void GetGPIOPinName(){
if (GPIO_INSTANCE_PIN_NUMBER >= 0 || GPIO_INSTANCE_PIN_NUMBER <= 7){
GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER));
}else if (GPIO_INSTANCE_PIN_NUMBER >= 8 || GPIO_INSTANCE_PIN_NUMBER <= 11){
switch(GPIO_INSTANCE_PIN_NUMBER){
case 8:
GPIOPinMuxSetup(CONTROL_CONF_UART_RTSN(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER));
break;
case 9:
GPIOPinMuxSetup(CONTROL_CONF_UART_CTSN(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER));
break;
case 10:
GPIOPinMuxSetup(CONTROL_CONF_UART_RXD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER));
break;
case 11:
GPIOPinMuxSetup(CONTROL_CONF_UART_TXD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER));
break;
}
}else if (GPIO_INSTANCE_PIN_NUMBER >= 12 || GPIO_INSTANCE_PIN_NUMBER <= 14){
GPIOPinMuxSetup(CONTROL_CONF_GPMC_AD(GPIO_INSTANCE_PIN_NUMBER), CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER));
}else if (GPIO_INSTANCE_PIN_NUMBER >= 16 || GPIO_INSTANCE_PIN_NUMBER <= 27){
int PIN_REFERENCE = GPIO_INSTANCE_PIN_NUMBER - 16;
GPIOPinMuxSetup(CONTROL_CONF_GPMC_A(PIN_REFERENCE), CONTROL_CONF_MUXMODE(PIN_REFERENCE));
}else if (GPIO_INSTANCE_PIN_NUMBER == 28) {
GPIOPinMuxSetup(CONTROL_CONF_GPMC_BE1N , CONTROL_CONF_MUXMODE(GPIO_INSTANCE_PIN_NUMBER));
}else if (GPIO_INSTANCE_PIN_NUMBER >= 29 || GPIO_INSTANCE_PIN_NUMBER <= 31){
}
}
// TODO: need to init more pins here
void gpioPinMux(void)
{
// gpio1 pin 23
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(7)) = CONTROL_CONF_MUXMODE(7);
//
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) = CONTROL_CONF_MUXMODE(7);
//
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) = CONTROL_CONF_MUXMODE(7);
}
unsigned int CPSWPinMuxSetup(unsigned int MiiNr)
{
#if (defined beaglebone) || (defined evmAM335x)
switch(MiiNr)
{
case 1:
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE | CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN) = CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV) =
CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE | CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3) = CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2) = CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1) = CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0) = CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK) =
CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RXACTIVE | CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK) =
CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE | CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3) =
CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE | CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2) =
CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE | CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1) =
CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE | CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0) =
CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE | CPSW_MII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA) =
CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE
| CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL
| CPSW_MDIO_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK) =
CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL | CPSW_MDIO_SEL_MODE;
break;
default:
return 0;
}
#elif (defined evmskAM335x)
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(1)) =
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(2)) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(3)) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4)) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(5)) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(6)) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(7)) =
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(8)) =
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(9)) =
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(10)) =
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(11)) =
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) =
CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) =
CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV) =
CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK) =
CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3) =
CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2) =
CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1) =
CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0) =
CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) =
CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA) =
CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE
| CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL
| CPSW_MDIO_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK) =
CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL
| CPSW_MDIO_SEL_MODE;
#endif
return 1;
}
void GPIO1Pin23PinMuxSetup(void)
{
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(7)) = CONTROL_CONF_MUXMODE(7);
}
