/*
* ack GPIO irq's
* Ack only for edge triggered int's valid
*/
static void inline ack_gpio_irq(u32 irq)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
u32 bit = IRQ_TO_BIT(irq);
if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
CPU_REG (reg_base, GPIO_CLR) = bit;
}
/*
* ack GPIO irq's
* Ack only for edge triggered int's valid
*/
static void inline ack_gpio_irq(struct irq_data *d)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
u32 bit = IRQ_TO_BIT(d->irq);
if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
CPU_REG (reg_base, GPIO_CLR) = bit;
}
/*
* Hardware init. This is called early in initcalls
* Place pin inits here. So you avoid adding ugly
* #ifdef stuff to common drivers.
* Use this only, if your bootloader is not able
* to initialize the pins proper.
*/
static void __init init_eval_h7202(void)
{
init_hw_h7202();
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
/* Enable interrupt on portb bit 8 (ethernet) */
CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8);
CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8);
}
static void __init init_eval_h7202(void)
{
init_hw_h7202();
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
/* */
CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8);
CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8);
}
static void h720x__idle(void)
{
CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
nop();
nop();
CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
nop();
nop();
}
/*
* Setup TIMER0 as system timer
*/
void __init h7202_init_time(void)
{
CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
setup_irq(IRQ_TIMER0, &h7202_timer_irq);
}
void __init init_hw_h7202(void)
{
/* Enable clocks */
CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
#ifdef CONFIG_H7202_SERIAL23
CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 | AMULSEL_USOUT2 |
AMULSEL_USIN3 | AMULSEL_USOUT3;
#endif
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
}
/* Although we have two interrupt lines for the timers, we only have one
* status register which clears all pending timer interrupts on reading. So
* we have to handle all timer interrupts in one place.
*/
static void
h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
struct pt_regs *regs)
{
unsigned int mask, irq;
mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
if ( mask & TSTAT_T0INT ) {
timer_tick(regs);
if( mask == TSTAT_T0INT )
return;
}
mask >>= 1;
irq = IRQ_TIMER1;
desc = irq_desc + irq;
while (mask) {
if (mask & 1)
desc->handle(irq, desc, regs);
irq++;
desc++;
mask >>= 1;
}
}
/*
* Timer interrupt handler
*/
static irqreturn_t
h7201_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
timer_tick(regs);
return IRQ_HANDLED;
}
void __init init_hw_h7202(void)
{
/* Enable clocks */
CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void
h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOB(0);
IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
h720x_gpio_handler(mask, irq, desc);
}
/*
* Timer interrupt handler
*/
static irqreturn_t
h7201_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
write_seqlock(&xtime_lock);
CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
timer_tick(regs);
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
void __init h7202_init_irq (void)
{
int irq;
CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
for (irq = IRQ_TIMER1;
irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
mask_timerx_irq(irq);
set_irq_chip(irq, &h7202_timerx_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_flags(irq, IRQF_VALID );
}
set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
h720x_init_irq();
}
/* Although we have two interrupt lines for the timers, we only have one
* status register which clears all pending timer interrupts on reading. So
* we have to handle all timer interrupts in one place.
*/
static void
h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
if ( mask & TSTAT_T0INT ) {
timer_tick();
if( mask == TSTAT_T0INT )
return;
}
mask >>= 1;
irq = IRQ_TIMER1;
while (mask) {
if (mask & 1)
generic_handle_irq(irq);
irq++;
mask >>= 1;
}
}
void __init h720x_init_irq (void)
{
int irq;
CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
irq_set_chip_and_handler(irq, &h720x_global_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
#ifdef CONFIG_CPU_H7202
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
#endif
CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
}
/*
* Initialize IRQ's, mask all, enable multiplexed irq's
*/
void __init h720x_init_irq (void)
{
int irq;
/* Mask global irq's */
CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
/* Mask all multiplexed irq's */
CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
/* Initialize global IRQ's, fast path */
for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
irq_set_chip_and_handler(irq, &h720x_global_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/* Initialize multiplexed IRQ's, slow path */
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
#ifdef CONFIG_CPU_H7202
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
irq_set_chip_and_handler(irq, &h720x_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID );
}
irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
#endif
/* Enable multiplexed irq's */
CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
}
/*
* unmask GPIO irq's
*/
static void inline unmask_gpio_irq(u32 irq)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
u32 bit = IRQ_TO_BIT(irq);
CPU_REG (reg_base, GPIO_MASK) |= bit;
}
/*
* unmask multiplexed timer IRQs
*/
static void inline unmask_timerx_irq(struct irq_data *d)
{
unsigned int bit;
bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
}
/*
* mask multiplexed timer irq's
*/
static void inline mask_timerx_irq (u32 irq)
{
unsigned int bit;
bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
}
/*
* unmask Global irq's
*/
static void unmask_global_irq(struct irq_data *d)
{
CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << d->irq);
}
/*
* Return usecs since last timer reload
* (timercount * (usecs perjiffie)) / (ticks per jiffie)
*/
unsigned long h720x_gettimeoffset(void)
{
return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
}
void h720x_restart(char mode, const char *cmd)
{
CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
}
/*
* unmask GPIO irq's
*/
static void inline unmask_gpio_irq(struct irq_data *d)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
u32 bit = IRQ_TO_BIT(d->irq);
CPU_REG (reg_base, GPIO_MASK) |= bit;
}
/*
* unmask Global irq's
*/
static void unmask_global_irq (unsigned int irq )
{
CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq);
}
