BOOL CPU_SPI_Xaction_Start(const SPI_CONFIGURATION& Configuration)
{
if (Configuration.SPI_mod >= TOTAL_SPI_PORT) return FALSE;
LPC_SSP_T *spi = SPI_REG(Configuration.SPI_mod);
int Bits, Mode;
// Configure options and clock
Bits = (Configuration.MD_16bits) ? 16 : 8;
Mode = (Configuration.MSK_IDLE) ? 2 : 0; // ToDo: Check
Mode |= (!Configuration.MSK_SampleEdge) ? 1 : 0;
SPI_Config(spi, Bits, Mode, 0);
SPI_Frequency(spi, (1000 * Configuration.Clock_RateKHz));
// I/O setup
GPIO_PIN msk, miso, mosi;
CPU_SPI_GetPins(Configuration.SPI_mod, msk, miso, mosi);
UINT32 alternate = 0x252; // AF5 = SPI1/SPI2
if (Configuration.SPI_mod == 2) alternate = 0x262; // AF6 = SPI3, speed = 2 (50MHz)
CPU_GPIO_DisablePin(msk, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(miso, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin(mosi, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
// CS setup
CPU_GPIO_EnableOutputPin(Configuration.DeviceCS, Configuration.CS_Active);
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled(Configuration.CS_Setup_uSecs);
}
return TRUE;
}
BOOL CPU_SPI_Xaction_Start( const SPI_CONFIGURATION& Configuration )
{
NATIVE_PROFILE_HAL_PROCESSOR_SPI();
if (Configuration.SPI_mod >= STM32F4_SPI_MODS) return FALSE;
// CS setup
CPU_GPIO_EnableOutputPin( Configuration.DeviceCS, Configuration.CS_Active );
if(Configuration.CS_Setup_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled( Configuration.CS_Setup_uSecs );
}
// I/O setup
GPIO_PIN msk, miso, mosi;
CPU_SPI_GetPins(Configuration.SPI_mod, msk, miso, mosi);
UINT32 alternate = 0x252; // AF5 = SPI1/SPI2
if (Configuration.SPI_mod == 2) alternate = 0x262; // AF6 = SPI3, speed = 2 (50MHz)
CPU_GPIO_DisablePin( msk, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin( miso, RESISTOR_DISABLED, 0, (GPIO_ALT_MODE)alternate);
CPU_GPIO_DisablePin( mosi, RESISTOR_DISABLED, 1, (GPIO_ALT_MODE)alternate);
switch (Configuration.SPI_mod) {
case 0: RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; break; // enable SPI1 clock
case 1: RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; break; // enable SPI2 clock
case 2: RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; break; // enable SPI3 clock
}
ptr_SPI_TypeDef spi = g_STM32_Spi_Port[Configuration.SPI_mod];
// set mode bits
UINT32 cr1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR | SPI_CR1_SPE;
if (Configuration.MD_16bits) cr1 |= SPI_CR1_DFF;
if (Configuration.MSK_IDLE) cr1 |= SPI_CR1_CPOL | SPI_CR1_CPHA;
if (!Configuration.MSK_SampleEdge) cr1 ^= SPI_CR1_CPHA; // toggle phase
// set clock prescaler
UINT32 clock = SYSTEM_APB2_CLOCK_HZ / 2000; // SPI1 on APB2
if (Configuration.SPI_mod != 0) clock = SYSTEM_APB1_CLOCK_HZ / 2000; // SPI2/3 on APB1
if (clock > Configuration.Clock_RateKHz << 3) {
clock >>= 4;
cr1 |= SPI_CR1_BR_2;
}
BOOL CPU_SPI_Xaction_Stop(const SPI_CONFIGURATION& Configuration)
{
LPC_SSP_T *spi = SPI_REG(Configuration.SPI_mod);
while (SPI_Busy(spi)); // wait for completion
if(Configuration.CS_Hold_uSecs)
{
HAL_Time_Sleep_MicroSeconds_InterruptEnabled(Configuration.CS_Hold_uSecs);
}
CPU_GPIO_SetPinState(Configuration.DeviceCS, !Configuration.CS_Active);
GPIO_RESISTOR res = RESISTOR_PULLDOWN;
if (Configuration.MSK_IDLE) res = RESISTOR_PULLUP;
GPIO_PIN msk, miso, mosi;
CPU_SPI_GetPins(Configuration.SPI_mod, msk, miso, mosi);
CPU_GPIO_EnableInputPin(msk, FALSE, NULL, GPIO_INT_NONE, res);
CPU_GPIO_EnableInputPin(miso, FALSE, NULL, GPIO_INT_NONE, RESISTOR_PULLDOWN);
CPU_GPIO_EnableInputPin(mosi, FALSE, NULL, GPIO_INT_NONE, RESISTOR_PULLDOWN);
SPI_Disable(spi); // Disable SPI
return TRUE;
}
