void CPU_ProtectCommunicationGPIOs( BOOL On ) { NATIVE_PROFILE_PAL_COM(); switch(ExtractTransport(HalSystemConfig.DebugTextPort)) { case USART_TRANSPORT: CPU_USART_ProtectPins( ConvertCOM_ComPort(HalSystemConfig.DebugTextPort), On ); return ; case USB_TRANSPORT: CPU_USB_ProtectPins ( ConvertCOM_UsbController(HalSystemConfig.DebugTextPort), On ); return; default: return; } }
// --------------------------------------------------------------------------- HRESULT CPU_USB_Initialize(int core) { if (core >= MAX_USB_CORE || USB_ENABLED(core)) return S_FALSE; USB_CONTROLLER_STATE *State = CPU_USB_GetState(core); const USB_ENDPOINT_DESCRIPTOR *pEpDesc; const USB_INTERFACE_DESCRIPTOR *pIfDesc; int epNum, ret; UINT32 queueId = 0; GLOBAL_LOCK(irq); // Initialize physical layer if (!USB_ENABLED(1 - core)) // No other USB controllers enabled? { LPC_CGU->PLL[CGU_USB_PLL].PLL_CTRL &= ~1; // Enable USB PLL while (!(LPC_CGU->PLL[CGU_USB_PLL].PLL_STAT & 1)); // Wait for USB PLL to lock } LPC_CGU->BASE_CLK[USB_CLK[core]] &= ~1; // Enable USBx base clock LPC_CREG->CREG0 &= ~(1 << 5); // Enable USB0 PHY if (core == 1) // Special init for USB1 { // Enable USB1_DP and USB1_DN on chip FS phy LPC_SCU->SFSUSB = 0x12; // USB device mode (0x16 for host mode) LPC_USB1->PORTSC1_D |= (1 << 24); } // Set USB state USB_STATE(core) = State; USB_FLAGS(core) = 0; ep_out_count[core] = 0; ep_in_count[core] = 0; State->EndpointStatus = USB_EPSTATUS(core); State->EndpointCount = USB_MAX_EP_NUM; State->PacketSize = MAX_EP0_SIZE; // Initialize USB stack ret = USB_InitStack(core); if (ret != RET_OK) return S_FALSE; // Exit if not succesful // Set defaults for unused endpoints for (epNum = 1; epNum < State->EndpointCount; epNum++) { State->IsTxQueue[epNum] = FALSE; State->MaxPacketSize[epNum] = MAX_EP_SIZE; } // Get endpoint configuration while (USB_NextEndpoint(State, pEpDesc, pIfDesc)) { // Figure out which endpoint we are initializing epNum = pEpDesc->bEndpointAddress & 0x7F; // Check interface and endpoint numbers against hardware capability if (epNum >= State->EndpointCount || pIfDesc->bInterfaceNumber > 3) return S_FALSE; if (pEpDesc->bEndpointAddress & 0x80) State->IsTxQueue[epNum] = TRUE; // Set the maximum size of the endpoint hardware FIFO int endpointSize = pEpDesc->wMaxPacketSize; // Exit if the endpoint maximum size in the configuration list is bogus // or greater than USB_MAX_DATA_PACKET_SIZE (default=64) if ((endpointSize != 8 && endpointSize != 16 && endpointSize != 32 && endpointSize != 64 && endpointSize != 128 && endpointSize != 256 && endpointSize != 512) || endpointSize > USB_MAX_DATA_PACKET_SIZE) return S_FALSE; State->MaxPacketSize[epNum] = endpointSize; // Assign queues QueueBuffers[queueId].Initialize(); // Clear queue before use State->Queues[epNum] = &QueueBuffers[queueId]; // Attach queue to endpoint queueId++; // Isochronous endpoints are currently not supported if ((pEpDesc->bmAttributes & 3) == USB_ENDPOINT_ATTRIBUTE_ISOCHRONOUS) return FALSE; } // Configure CDC driver ret = CDC_Init(core); if (ret != RET_OK) return S_FALSE; // Exit if not succesful // Connect and enable interrupts CPU_USB_ProtectPins(core, FALSE); CPU_INTC_ActivateInterrupt(USB_IRQ[core], USB_ISR[core], 0); USB_ENABLED(core) = TRUE; State->DeviceState = USB_DEVICE_STATE_CONFIGURED; // Config done by ROM stack USB_StateCallback(State); return S_OK; }