/** ===========================================================================
* @n@b DAT_wait
*
* @b Description
* @n This function wait till the completion of Data Transfer.
*
* @b Arguments
* @verbatim
hDAT Handle to the DAT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n DAT_open() API must be called before this.
*
* <b> Post Condition </b>
* @n None
*
* @b Example
* @verbatim
#define CSL_DAT_BUFFER_LENGTH 100
CSL_DAT_ChannelObj pDatChanObj
CSL_DAT_Handle hDAT;
CSL_DAT_TxType type;
CSL_DATChanNum chanNum;
Uint16 chanPriority;
Uint32 srcAddr;
Uint32 destAddr;
Uint16 dataLength;
CSL_status status;
Uint32 pdataValue;
Uint16 destBuffer[CSL_DAT_BUFFER_LENGTH]
...
chanNum = CSL_DAT_CHAN0;
chanNum = CSL_DAT_CHAN_PRIORITY_HIGH;
hDAT = DAT_open(chanNum, chanPriority, &pDatChanObj, &status);
...
destAddr = destBuffer;
dataLength = CSL_DAT_BUFFER_LENGTH;
pdataValue = 0xABCD;
status = DAT_fill(hDAT, destAddr, dataLength, &pdataValue);
status = DAT_wait(hDAT);
@endverbatim
* ===========================================================================
*/
CSL_Status DAT_wait (
CSL_DAT_Handle hDAT
)
{
Bool status;
Uint16 chanNum;
Uint16 timeOut;
status = TRUE;
if(hDAT == NULL)
{
return CSL_ESYS_BADHANDLE;
}
chanNum = hDAT->chanNum;
while(chanNum >= CSL_DMA_PER_CNT)
{
chanNum = chanNum - CSL_DMA_PER_CNT;
}
switch((CSL_DATChanNum)chanNum)
{
case CSL_DAT_CHAN0:
timeOut = CSL_DAT_TIME_OUT;
while( status && timeOut-- )
{
status = CSL_FEXT(hDAT->dmaRegs->DMACH0TCR2, DMA_DMACH0TCR2_EN);
}
break;
case CSL_DAT_CHAN1:
timeOut = CSL_DAT_TIME_OUT;
while( status && timeOut-- )
{
status = CSL_FEXT(hDAT->dmaRegs->DMACH1TCR2, DMA_DMACH1TCR2_EN);
}
break;
case CSL_DAT_CHAN2:
timeOut = CSL_DAT_TIME_OUT;
while( status && timeOut-- )
{
status = CSL_FEXT(hDAT->dmaRegs->DMACH2TCR2, DMA_DMACH2TCR2_EN);
}
break;
case CSL_DAT_CHAN3:
timeOut = CSL_DAT_TIME_OUT;
while( status && timeOut-- )
{
status = CSL_FEXT(hDAT->dmaRegs->DMACH3TCR2, DMA_DMACH3TCR2_EN);
}
break;
}
return CSL_SOK;
}
static Bool LOCAL_examplePassed ( Uint8 pruNum )
{
Bool retVal = TRUE;
CSL_PscRegsOvly PSC0 = (CSL_PscRegsOvly) CSL_PSC_0_REGS;
CSL_PscRegsOvly PSC1 = (CSL_PscRegsOvly) CSL_PSC_1_REGS;
// Make sure the PRU did the PSC transitions
retVal = retVal && ( CSL_FEXT(PSC0->MDSTAT[CSL_PSC_UART0], PSC_MDSTAT_STATE) == CSL_PSC_MDSTAT_STATE_ENABLE );
retVal = retVal && ( CSL_FEXT(PSC0->MDSTAT[CSL_PSC_SPI0] , PSC_MDSTAT_STATE) == CSL_PSC_MDCTL_NEXT_SYNCRST );
retVal = retVal && ( CSL_FEXT(PSC1->MDSTAT[CSL_PSC_I2C1] , PSC_MDSTAT_STATE) == CSL_PSC_MDSTAT_STATE_ENABLE );
retVal = retVal && ( CSL_FEXT(PSC1->MDSTAT[CSL_PSC_SPI1] , PSC_MDSTAT_STATE) == CSL_PSC_MDCTL_NEXT_SYNCRST );
return retVal;
}
/*..........................................................................*/
void QK_onIdle(void) {
QF_INT_DISABLE();
SLED_ON(); /* switch the System LED on and off */
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
SLED_OFF();
QF_INT_ENABLE();
#ifdef Q_SPY
if (CSL_FEXT(l_uartObj.uartRegs->LSR, UART_LSR_THRE)) {
uint16_t b;
QF_INT_DISABLE();
b = QS_getByte();
QF_INT_ENABLE();
if (b != QS_EOD) { /* not End-Of-Data? */
CSL_FSET(l_uartObj.uartRegs->THR, 7U, 0U, b);
}
}
#elif defined NDEBUG
/* Put the CPU and peripherals to the low-power mode.
* you might need to customize the clock management for your application,
* see the datasheet for your particular TMS320C5500 device.
*/
asm(" IDLE");
#endif
}
CSL_Status SAR_chanClose (
SAR_Handle hSar
)
{
hSar->chanNo = CSL_SAR_NO_CHAN;
if(NULL == hSar)
{
return CSL_ESYS_BADHANDLE;
}
// stop conversion
if(CSL_SAR_ADC_START ==
CSL_FEXT (hSar->baseAddr->SARCTRL,ANACTRL_SARCTRL_ADCSTRT) )
{
/* Stop SAR A/D conversion */
CSL_FINST (hSar->baseAddr->SARCTRL,ANACTRL_SARCTRL_ADCSTRT,
CLEAR);
}
/* Power Down the Analog */
CSL_FINST (hSar->baseAddr->SARPINCTRL,ANACTRL_SARPINCTRL_SARPWRUP,
CLEAR);
/* Power down the current bias circuit */
CSL_FINST (hSar->baseAddr->SARPINCTRL,ANACTRL_SARPINCTRL_PWRUPBIAS,
CLEAR);
hSar->baseAddr = NULL ;
hSar->status = CSL_SAR_CLOSE;
return CSL_SOK;
}
/**
* @b Description
* @n
* The function returns size of the descriptors in the specified memory region.
*
* This is for *internal* LLD usage.
*
* @param[in] memRegion
* Memory region number.
*
* @retval
* Descriptor size
*/
uint32_t Qmss_getMemRegDescSize (uint32_t memRegion)
{
uint32_t descVal;
descVal = CSL_FEXT (qmssLObj.qmDescReg->MEMORY_REGION_BASE_ADDRESS_GROUP[memRegion].MEMORY_REGION_DESCRIPTOR_SETUP_REG,
QM_DESCRIPTOR_REGION_CONFIG_MEMORY_REGION_DESCRIPTOR_SETUP_REG_DESC_SIZE);
return ((descVal + 1) * 16);
}
/** ===========================================================================
* @n@b SPI_write
*
* @b Description
* @n This function Write data to specified device.
*
* @b Arguments
* @verbatim
hSpi Pointer to handler
writeBuff Pointer to the write buffer.
buffLen Maximum read buffer size.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Write successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* This function can call by SPI_dataTransaction function.
*
* <b> Post Condition </b>
* @n SPI_deInit can be call after this function call.
*
* @b Modifies
* @n
*
* @b Example
* @verbatim
CSL_SpiHandle hSpi
Uint16 writeBuff[size];
Uint16 buffLen;
CSL_status status;
status = SPI_write(hSpi,&writeBuff, buffLen);
@endverbatim
* ===========================================================================
*/
CSL_Status SPI_write (CSL_SpiHandle hSpi,
Uint16 *writeBuffer,
Uint16 bufLen)
{
Uint16 getWLen;
volatile Uint16 bufIndex;
Uint16 spiStatusReg;
volatile Uint16 spiBusyStatus;
volatile Uint16 spiWcStaus;
volatile Uint16 delay;
bufIndex = 0;
if((NULL == writeBuffer) || (0 == bufLen))
{
return (CSL_ESYS_INVPARAMS);
}
/* Read the word length form the register */
getWLen = CSL_FEXT(CSL_SPI_REGS->SPICMD2, SPI_SPICMD2_CLEN) + 1;
if(getWLen >= SPI_MAX_WORD_LEN)
{
return (CSL_ESYS_INVPARAMS);
}
/* Write Word length set by the user */
while(bufIndex < bufLen)
{
/* Write to registers more then 16 bit word length */
if(getWLen == 16)
{
CSL_SPI_REGS->SPIDR2 = writeBuffer[bufIndex];
CSL_SPI_REGS->SPIDR1 = 0x0000;
bufIndex ++;
}
/* Write to register less then or equal to 16 bit word length */
else if(getWLen == 8)
{
CSL_SPI_REGS->SPIDR2 = (Uint16)(writeBuffer[bufIndex] << 0x08);
CSL_SPI_REGS->SPIDR1 = 0x0000;
bufIndex++;
}
/* Set command for Writting to registers */
CSL_FINS(CSL_SPI_REGS->SPICMD2, SPI_SPICMD2_CMD, SPI_WRITE_CMD);
for(delay = 0; delay < 100; delay++);
do
{
spiStatusReg = CSL_SPI_REGS->SPISTAT1;
spiBusyStatus = (spiStatusReg & CSL_SPI_SPISTAT1_BSY_MASK);
spiWcStaus = (spiStatusReg & CSL_SPI_SPISTAT1_CC_MASK);
}while((spiBusyStatus == CSL_SPI_SPISTAT1_BSY_BUSY) &&
(spiWcStaus != CSL_SPI_SPISTAT1_CC_MASK));
}
return (CSL_SOK);
}
int upp_start_transmit(
unsigned char *trans_buffer,
int receive_length,
int byte_receive_perline,
int send_length,
int byte_send_perline,unsigned char tranflag)
{
int status = 0;
int receive_line_cnt,send_line_cnt;
// unsigned short *xmtBuffer_pt;
#ifdef LoopBack
upp_fill_buffer(trans_buffer, dataWidth, UPP_DP_RJUST_0FILL, sendSize); // fill transmit buffer with test pattern
//
upp_fill_buffer(recv_buffer, 0, UPP_DP_RJUST_0FILL, receiveSize); // clear receive buffer
#else
receive_line_cnt=receive_length/byte_receive_perline;
send_line_cnt=send_length/byte_send_perline;
#endif
// Ensure uPP not enabled yet.
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_EN, DISABLE);
// init DMA channels
if(tranflag == 0)
{
while(CSL_FEXT(uppRegs->UPQS2, UPP_UPQS2_PEND) == 1);
upp_dma_prog(UPP_DMA_CHAN_Q, (void *)trans_buffer, receive_line_cnt, byte_receive_perline, byte_receive_perline);
}
if(tranflag == 1)
{
while(CSL_FEXT(uppRegs->UPIS2, UPP_UPIS2_PEND) == 1);
upp_dma_prog(UPP_DMA_CHAN_I, (void *)trans_buffer, send_line_cnt, byte_send_perline, byte_send_perline);
}
// Enable uPP here. PCR.EN bit
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_EN, ENABLE);
status = 0;
upp_test_exit:
return status;
}
int DRV_imageTuneGetRawDataStartPhase()
{
int phase, startX, startY;
int regValue = CSL_FEXT(gCSL_vpssHndl.ipipeRegs->SRC_COL, IPIPE_SRC_COL_EE);
regValue = regValue % 4;
startX = gCSL_vpssHndl.ipipeRegs->SRC_HPS % 2;
startY = gCSL_vpssHndl.ipipeRegs->SRC_VPS % 2;
phase = regValue;
if (startX)
{
switch (phase)
{
case CSL_IPIPE_SOURCE_COLOUR_R:
phase = CSL_IPIPE_SOURCE_COLOUR_GR;
break;
case CSL_IPIPE_SOURCE_COLOUR_GR:
phase = CSL_IPIPE_SOURCE_COLOUR_R;
break;
case CSL_IPIPE_SOURCE_COLOUR_GB:
phase = CSL_IPIPE_SOURCE_COLOUR_B;
break;
case CSL_IPIPE_SOURCE_COLOUR_B:
phase = CSL_IPIPE_SOURCE_COLOUR_GB;
break;
}
}
if (startY)
{
switch (phase)
{
case CSL_IPIPE_SOURCE_COLOUR_R:
phase = CSL_IPIPE_SOURCE_COLOUR_GB;
break;
case CSL_IPIPE_SOURCE_COLOUR_GR:
phase = CSL_IPIPE_SOURCE_COLOUR_B;
break;
case CSL_IPIPE_SOURCE_COLOUR_GB:
phase = CSL_IPIPE_SOURCE_COLOUR_R;
break;
case CSL_IPIPE_SOURCE_COLOUR_B:
phase = CSL_IPIPE_SOURCE_COLOUR_GR;
break;
}
}
#if 0
OSA_printf(" IMAGE TUNE: Phase Reg = %s : Start x,y = %d,%d : Phase = %s \n",
phaseName[regValue], startX, startY, phaseName[phase]
);
#endif
return phase;
}
CSL_Status CSL_intcQueryDropStatus (
CSL_IntcDropStatus *drop
)
{
Uint32 dropVal;
CSL_Status status = CSL_ESYS_INVPARAMS ;
if (drop) {
dropVal = ((CSL_IntcRegsOvly)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS)->INTXSTAT;
drop->drop = (Bool)(CSL_FEXT(dropVal,INTC_INTXSTAT_DROP));
drop->eventId = (CSL_IntcEventId)(CSL_FEXT(dropVal,INTC_INTXSTAT_SYSINT));
drop->vectId = (CSL_IntcVectId)(CSL_FEXT(dropVal,INTC_INTXSTAT_CPUINT));
/* Clear the drop condition */
((CSL_IntcRegsOvly)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS)->INTXCLR = 1;
status = CSL_SOK;
}
return status;
}
/** ============================================================================
* @n@b I2C_getEventId
*
* @b Description
* @n Returns the I2C event ID. This event represent the I2C interrupt
* in the I2C interrupt vector register
*
* @b Arguments
* @verbatim
None
@endverbatim
*
* <b> Return Value </b>
* @n I2C Event Id
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Returns I2C event Id
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Int16 i2cEvent;
i2cEvent = I2C_getEventId();
@endverbatim
* ============================================================================
*/
Int16 I2C_getEventId(void)
{
Int16 eventId;
/* Read the event generated the interrupt from interrupt vector register */
eventId = (Int16)CSL_FEXT(i2cHandle->i2cRegs->ICIVR, I2C_ICIVR_INTCODE);
return(eventId);
}
Uint32 getSysClk(void)
{
Bool pllRDBypass;
Bool pllOutDiv;
Bool pllOutDiv2;
Uint32 sysClk;
Uint16 pllVP;
Uint16 pllVS;
Uint16 pllRD;
Uint16 pllVO;
Uint16 pllDivider;
Uint32 pllMultiplier;
pllVP = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR1, SYS_CGCR1_MH);
pllVS = CSL_FEXT(CSL_SYSCTRL_REGS->CGICR, SYS_CGICR_ML);
pllRD = CSL_FEXT(CSL_SYSCTRL_REGS->CGICR, SYS_CGICR_RDRATIO);
pllVO = CSL_FEXT(CSL_SYSCTRL_REGS->CGOCR, SYS_CGOCR_ODRATIO);
pllRDBypass = CSL_FEXT(CSL_SYSCTRL_REGS->CGICR, SYS_CGICR_RDBYPASS);
pllOutDiv = CSL_FEXT(CSL_SYSCTRL_REGS->CGOCR, SYS_CGOCR_OUTDIVEN);
pllOutDiv2 = CSL_FEXT(CSL_SYSCTRL_REGS->CGOCR, SYS_CGOCR_OUTDIV2BYPASS);
pllDivider = ((pllOutDiv2) | (pllOutDiv << 1) | (pllRDBypass << 2));
pllMultiplier = ((Uint32)CSL_PLL_CLOCKIN * ((pllVP << 2) + pllVS + 4));
switch(pllDivider)
{
case CSL_PLL_DIV_000:
case CSL_PLL_DIV_001:
sysClk = pllMultiplier / (pllRD + 4);
break;
case CSL_PLL_DIV_002:
sysClk = pllMultiplier / ((pllRD + 4) * (pllVO + 4) * 2);
break;
case CSL_PLL_DIV_003:
sysClk = pllMultiplier / ((pllRD + 4) * 2);
break;
case CSL_PLL_DIV_004:
case CSL_PLL_DIV_005:
sysClk = pllMultiplier;
break;
case CSL_PLL_DIV_006:
sysClk = pllMultiplier / ((pllVO + 4) * 2);
break;
case CSL_PLL_DIV_007:
sysClk = pllMultiplier / 2;
break;
}
/* Return the value of system clock in KHz */
return(sysClk/1000);
}
/** ===========================================================================
* @n@b SPI_read
*
* @b Description
* @n This function Read data form specified device.
*
* @b Arguments
* @verbatim
hSpi Pointer to handler
readBuff Pointer to the read buffer.
buffLen Maximum read buffer size.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Read successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n This function can call by SPI_dataTransaction function.
*
* <b> Post Condition </b>
* @n SPI_deInit can be call after this function call.
*
* @b Modifies
* @n
*
* @b Example
* @verbatim
CSL_SpiHandle hSpi
Uint16 readBuff[size];
Uint16 buffLen;
CSL_status status;
status = SPI_read(hSpi,&readBuff, buffLen);
@endverbatim
* ===========================================================================
*/
CSL_Status SPI_read (CSL_SpiHandle hSpi,
Uint16 *readBuffer,
Uint16 bufLen)
{
Int16 getWLen;
volatile Uint16 bufIndex;
Int16 spiStatusReg;
volatile Int16 spiBusyStatus;
volatile Int16 spiWcStaus;
volatile Uint16 delay;
bufIndex = 0;
if((NULL == readBuffer) || (0 == bufLen))
{
return (CSL_ESYS_INVPARAMS);
}
/* Read the word length form the register */
getWLen = CSL_FEXT(CSL_SPI_REGS->SPICR2, SPI_SPICR2_WLEN) + 1;
if(getWLen >= SPI_MAX_WORD_LEN)
{
return (CSL_ESYS_INVPARAMS);
}
/* Read Word length set by the user */
while(bufIndex < bufLen)
{
/* Set command for reading buffer */
CSL_FINS(CSL_SPI_REGS->SPICR2, SPI_SPICR2_CMD,
CSL_SPI_SPICR2_CMD_READ);
for(delay = 0; delay < 100; delay++);
do
{
spiStatusReg = CSL_SPI_REGS->SPISR1;
spiBusyStatus = (spiStatusReg & CSL_SPI_SPISR1_BSY_MASK);
spiWcStaus = (spiStatusReg & CSL_SPI_SPISR1_WC_MASK);
}while((spiBusyStatus == CSL_SPI_SPISR1_BSY_MASK) &&
(spiWcStaus != CSL_SPI_SPISR1_WC_MASK));
if(getWLen == 16)
{
//printf("value in reg before read = %d, in reg 2 = %d\n",(Int16) CSL_SPI_REGS->SPIDR1, (Int16) CSL_SPI_REGS->SPIDR2);
readBuffer[bufIndex] = CSL_SPI_REGS->SPIDR1;
bufIndex++;
}
else if(getWLen == 8)
{
readBuffer[bufIndex] = (CSL_SPI_REGS->SPIDR1 & 0xFF);
bufIndex++;
}
}
return (CSL_SOK);
}
// Clock gating for unused peripherals
void ClockGating(void)
{
Uint16 pcgcr_value, clkstop_value;
// set PCGCR1
pcgcr_value = 0;
// clock gating SPI
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_SPICG, DISABLED);
// clock gating SD/MMC
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_MMCSD0CG, DISABLED);
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_MMCSD0CG, DISABLED);
// clock stop request for UART
clkstop_value = CSL_FMKT(SYS_CLKSTOP_URTCLKSTPREQ, REQ);
// write to CLKSTOP
CSL_FSET(CSL_SYSCTRL_REGS->CLKSTOP, 15, 0, clkstop_value);
// wait for acknowledge
while (CSL_FEXT(CSL_SYSCTRL_REGS->CLKSTOP, SYS_CLKSTOP_URTCLKSTPACK)==0);
// clock gating UART
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_UARTCG, DISABLED);
// clock stop request for EMIF
//clkstop_value = CSL_FMKT(SYS_CLKSTOP_EMFCLKSTPREQ, REQ);
// write to CLKSTOP
//CSL_FSET(CSL_SYSCTRL_REGS->CLKSTOP, 15, 0, clkstop_value);
// wait for acknowledge
//while (CSL_FEXT(CSL_SYSCTRL_REGS->CLKSTOP, SYS_CLKSTOP_EMFCLKSTPACK)==0);
// clock gating EMIF
//pcgcr_value |= CSL_FMKT(SYS_PCGCR1_EMIFCG, DISABLED);
// clock gating unused I2S (I2S 0, 1, 3)
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_I2S0CG, DISABLED);
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_I2S1CG, DISABLED);
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_I2S3CG, DISABLED);
// clcok gating DMA0
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_DMA0CG, DISABLED);
// clcok gating Timer 1
//pcgcr_value |= CSL_FMKT(SYS_PCGCR1_TMR1CG, DISABLED);
// clcok gating Timer 2
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_TMR2CG, DISABLED);
// write to PCGCR1
CSL_FSET(CSL_SYSCTRL_REGS->PCGCR1, 15, 0, pcgcr_value);
// set PCGCR2
pcgcr_value = 0;
// clock gating LCD
pcgcr_value |= CSL_FMKT(SYS_PCGCR2_LCDCG, DISABLED);
// clcok gating DMA2
pcgcr_value |= CSL_FMKT(SYS_PCGCR2_DMA2CG, DISABLED);
// clcok gating DMA3
pcgcr_value |= CSL_FMKT(SYS_PCGCR2_DMA3CG, DISABLED);
// write to PCGCR2
CSL_FSET(CSL_SYSCTRL_REGS->PCGCR2, 15, 0, pcgcr_value);
return;
}
Bool SAR_getStatus(
CSL_SarHandleObj *hSar,
CSL_Status *status
)
{
volatile Bool busyBit = CSL_SAR_ADC_BUSY ;
if(NULL == hSar)
{
*status = CSL_ESYS_BADHANDLE;
}
busyBit = CSL_FEXT (hSar->baseAddr->SARDATA, ANACTRL_SARDATA_ADCBSY) ;
*status = CSL_SOK;
return busyBit;
}
CSL_Status UART_setup(CSL_UartHandle hUart, CSL_UartSetup *uartSetup)
{
CSL_Status status =CSL_SOK;
Uint32 value;
Uint32 clk_div;
if( NULL == hUart )
{
return CSL_ESYS_BADHANDLE;
}
if( NULL == uartSetup)
{
return CSL_ESYS_INVPARAMS;
}
/**Putting UART recvor and xmittor in reset state*/
hUart->uartRegs->PWREMU_MGMT = CSL_UART_PWREMU_MGMT_RESETVAL;
/* Write 0 to DLAB to access IER*/
CSL_FINST(hUart->uartRegs->LCR, UART_LCR_DLAB, DLABON);
/*Disable all interrupts*/
hUart->uartRegs->IER = CSL_UART_IER_RESETVAL;
/* Flushing buffer */
value = (Uint32)(hUart->uartRegs->RBR);
/* reset and possibly enable FIFOs */
CSL_FINST(hUart->uartRegs->FCR, UART_FCR_FIFOEN, ENABLE);
CSL_FINST(hUart->uartRegs->FCR, UART_FCR_RXCLR, CLR);
CSL_FINST(hUart->uartRegs->FCR, UART_FCR_TXCLR, CLR);
hUart->uartRegs->FCR = uartSetup->fifoControl;
hUart->trigLevel = CSL_FEXT(uartSetup->fifoControl,UART_FCR_RXFIFTL);
clk_div = CSL_UART_CLK_DIVIDER(uartSetup->baud);
/* Set DLL and DLM to values appropriate for the required baudrate */
value = ( (Uint32) (uartSetup->clkInput) / (clk_div ) );
/* Write 1 to DLAB to access DLL and DLH*/
CSL_FINST(hUart->uartRegs->LCR, UART_LCR_DLAB, DLABOFF);
if ( ( (Uint32)(uartSetup->clkInput) % ( clk_div ) )
>= ( clk_div / 2 ) )
{
if ((value & 0xFF) != 0xFF)
{
hUart->uartRegs->DLL = (Uint8)(value & 0xFF) + 1;
hUart->uartRegs->DLH = (Uint8)((value & 0xFF00) >> 8);
}
else
{
CSL_Status SAR_readData (
SAR_Handle hSar,
Uint16 *readData
)
{
if(NULL == hSar)
{
return CSL_ESYS_BADHANDLE;
}
if(NULL == readData)
{
return CSL_ESYS_INVPARAMS;
}
*readData = CSL_FEXT (hSar->baseAddr->SARDATA, ANACTRL_SARDATA_ADCDAT);
return CSL_SOK;
}
CSL_Status SAR_stopConversion (
SAR_Handle hSar
)
{
if(NULL == hSar)
{
return CSL_ESYS_BADHANDLE;
}
/* Check whether conversion start bit is set or not */
if(CSL_SAR_ADC_START ==
CSL_FEXT (hSar->baseAddr->SARCTRL, ANACTRL_SARCTRL_ADCSTRT) )
{
/* Stop SAR A/D conversion */
CSL_FINST (hSar->baseAddr->SARCTRL, ANACTRL_SARCTRL_ADCSTRT, CLEAR);
}
return CSL_SOK;
}
/** ============================================================================
* @n@b I2C_getConfig
*
* @b Description
* @n Gets the I2C configuration parameters
*
* @b Arguments
* @verbatim
i2cgetConfig I2C Configuration structure pointer
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n I2C_config should be called successfully
*
* <b> Post Condition </b>
* @n Populates the I2C config structure
*
* @b Modifies
* @n Structure pointed by getI2cConfig
*
* @b Example
* @verbatim
CSL_Status status;
CSL_I2cConfig i2cConfig;
CSL_I2cConfig i2cgetConfig
i2cConfig.icoar = CSL_I2C_ICOAR_DEFVAL;
i2cConfig.icimr = CSL_I2C_ICIMR_DEFVAL;
i2cConfig.icclkl = CSL_I2C_ICCLK_DEFVAL;
i2cConfig.icclkh = CSL_I2C_ICCLK_DEFVAL;
i2cConfig.iccnt = CSL_I2C_DATA_SIZE;
i2cConfig.icsar = CSL_I2C_ICSAR_DEFVAL;
i2cConfig.icmdr = CSL_I2C_ICMDR_WRITE_DEFVAL;
i2cConfig.icemdr = CSL_I2C_ICEMDR_DEFVAL;
i2cConfig.icpsc = CSL_I2C_ICPSC_DEFVAL;
status = I2C_init(CSL_I2C0);
....
status = I2C_config(&i2cConfig);
....
....
status = I2C_getConfig(&i2cgetConfig);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_getConfig(CSL_I2cConfig *i2cgetConfig)
{
if(i2cgetConfig != NULL)
{
/* Read I2C Own Address register */
i2cgetConfig->icoar = CSL_FEXT(i2cHandle->i2cRegs->ICOAR,
I2C_ICOAR_OADDR);
/* Read I2C interrupt mask register */
i2cgetConfig->icimr = CSL_FEXTR(i2cHandle->i2cRegs->ICIMR,
CSL_I2C_ICIMR_AAS_SHIFT,
CSL_I2C_ICIMR_AL_SHIFT);
/* Read I2C clock low register */
i2cgetConfig->icclkl = CSL_FEXT(i2cHandle->i2cRegs->ICCLKL,
I2C_ICCLKL_ICCL);
/* Read I2C clock high register */
i2cgetConfig->icclkh = CSL_FEXT(i2cHandle->i2cRegs->ICCLKH,
I2C_ICCLKH_ICCH);
/* Read I2C count register */
i2cgetConfig->iccnt = CSL_FEXT(i2cHandle->i2cRegs->ICCNT,
I2C_ICCNT_ICDC);
/* Read I2C slave address register */
i2cgetConfig->icsar = CSL_FEXT(i2cHandle->i2cRegs->ICSAR,
I2C_ICSAR_SADDR);
/* Read I2C mode address register */
i2cgetConfig->icmdr = i2cHandle->i2cRegs->ICMDR;
/* Read I2C extended mode address register */
i2cgetConfig->icemdr = CSL_FEXTR(i2cHandle->i2cRegs->ICEMDR,
CSL_I2C_ICEMDR_IGNACK_SHIFT,
CSL_I2C_ICEMDR_BCM_SHIFT);
/* Read I2C prescaler register */
i2cgetConfig->icpsc = CSL_FEXT(i2cHandle->i2cRegs->ICPSC,
I2C_ICPSC_IPSC);
}
else
{
return(CSL_ESYS_INVPARAMS);
}
return(CSL_SOK);
}
static void Qmss_internaldownloadFirmware (Qmss_PdspId pdspId, void *image, uint32_t size)
{
uint32_t i, count;
volatile uint32_t enable;
uint32_t *data = (uint32_t *) image;
/* Reset the PDSP */
CSL_FINS (qmssLObj.qmPdspCtrlReg[pdspId]->PDSP_CONTROL_REG, PDSP_PDSP_CONTROL_REG_PDSP_ENABLE, 0);
/* Confirm PDSP has halted */
do
{
enable = CSL_FEXT (qmssLObj.qmPdspCtrlReg[pdspId]->PDSP_CONTROL_REG, PDSP_PDSP_CONTROL_REG_PDSP_STATE);
}while (enable);
count = size / 4;
/* Download the firmware */
for(i = 0; i < count; i++)
qmssLObj.qmPdspIRamReg[pdspId][i] = data[i];
/* Use the command register to sync the PDSP */
*qmssLObj.qmPdspCmdReg[pdspId] = 0xFFFFFFFF;
/* Wait to the memory write to land */
for(i = 0; i < 20000 && *qmssLObj.qmPdspCmdReg[pdspId] != 0xFFFFFFFF; i++);
/* Reset program counter to zero */
CSL_FINS (qmssLObj.qmPdspCtrlReg[pdspId]->PDSP_CONTROL_REG, PDSP_PDSP_CONTROL_REG_PCOUNTER_RST_VAL, 0);
/* Set soft reset to zero to load the program counter */
CSL_FINS (qmssLObj.qmPdspCtrlReg[pdspId]->PDSP_CONTROL_REG, PDSP_PDSP_CONTROL_REG_SOFT_RST_N, 0);
/* Enable the PDSP */
CSL_FINS (qmssLObj.qmPdspCtrlReg[pdspId]->PDSP_CONTROL_REG, PDSP_PDSP_CONTROL_REG_PDSP_ENABLE, 1);
/* Wait for the command register to clear */
while (*qmssLObj.qmPdspCmdReg[pdspId]);
return;
}
Uint32 getSysClk(void)
{
Bool pllRDBypass;
Bool pllOutDiv;
Uint32 sysClk;
Uint16 pllVP;
Uint16 pllVS;
Uint16 pllRD;
Uint16 pllVO;
pllVP = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR1, SYS_CGCR1_VP);
pllVS = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR1, SYS_CGCR1_VS);
pllRD = CSL_FEXT(CSL_SYSCTRL_REGS->CGICR, SYS_CGICR_RDRATIO);
pllVO = CSL_FEXT(CSL_SYSCTRL_REGS->CGOCR, SYS_CGOCR_OD);
pllRDBypass = CSL_FEXT(CSL_SYSCTRL_REGS->CGICR, SYS_CGICR_RDBYPASS);
pllOutDiv = CSL_FEXT(CSL_SYSCTRL_REGS->CGOCR, SYS_CGOCR_OUTDIVEN);
sysClk = CSL_PLL_CLOCKIN;
if (0 == pllRDBypass)
{
sysClk = sysClk/(pllRD + 4);
}
sysClk = (sysClk * ((pllVP << 2) + pllVS + 4));
if (1 == pllOutDiv)
{
sysClk = sysClk/(pllVO + 1);
}
/* Return the value of system clock in KHz */
return(sysClk/1000);
}
int upp_init()
{
int status = 0;
uppDevParams uPP;
upp_key_config(); // program the KICK0 and 1 registers.
upp_pinmux_enable(); // Though internal loopback, enable uPP in PIN_CONTROL_1
// EMIF16/UPP pinmux, "1" enable UPP
// read PID
int pid = CSL_FEXT(uppRegs->UPPID, UPP_UPPID_REVID);
if(pid != CSL_UPP_UPPID_RESETVAL)
{
printf("\n Error : Incorrect UPP ID read.");
goto upp_test_exit;
}
CSL_UPP_UPPCR_EN_TOKEN
// toggle SW reset in PCR
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_EN, DISABLE);
// toggle SW reset in PCR
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_SWRST, RESET);
LOCAL_delay(300);
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_SWRST, RUNNING);
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_SOFT, ENABLE);
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_FREE, DISABLE );
// init regs: CTL, ICR, IVR, TCR
uPP = uppDevParams_DEFAULT;
uPP.A.direction = UPP_DIR_XMT;//UPCTL中MODE位为1，发送模式
uPP.A.dataRate = UPP_DR_SDR;//UPCTL中DRA位为0，单倍速率模式
uPP.A.dataWidthVal = dataWidth;//UPCTL中IWA位为0,8bit宽度
uPP.A.idleValueVal = 0xAAAA;//空闲状态通道A中的idle值
uPP.A.clkDivVal = 0x2; // I/O时钟=发送时钟/(2*(UPICR.CLKDIVn+1))=发送时钟/(2*(2+1)=六分之一发送时钟
uPP.A.txThresh = UPP_TT_64B;//读阈值，一次最多读64B
uPP.B.direction = UPP_DIR_RCV;//UPCTL中MODE位为0，接收模式
uPP.B.dataRate = UPP_DR_SDR;
uPP.B.dataWidthVal = dataWidth;
uPP.B.idleValueVal = 0xBBBB;
uPP.B.clkDivVal = 0x2;//接收模式，分频无效，由外部时钟决定
uPP.B.rcvThresh = UPP_TT_64B;
uPP.loopback = UPP_LB_NONE; // UPP_LB_NONE UPP_LB_INTERNAL;
uPP.numChannelsVal = 2;
status = upp_config(&uPP);
if (status < 0)
goto upp_test_exit;
// init interrupt regs
upp_intc_setup_my(upp_isr); // setup intc (removed: use polled operation)
upp_int_enable( upp_int_EOLI |
upp_int_EOWI |
upp_int_ERRI | upp_int_UORI | upp_int_DPEI |
upp_int_EOLQ |
upp_int_EOWQ |
upp_int_ERRQ | upp_int_UORQ | upp_int_DPEQ |
0 );
CSL_FINST(uppRegs->UPPCR, UPP_UPPCR_EN, ENABLE);
status = 0;
upp_test_exit:
return status;
}
/**
* @b Description
* @n
* This function returns the threshold at which the queue threshold pin is asserted
*
* @param[in] hnd
* Queue handle.
*
* @pre
* Qmss_queueOpen function should be called before calling this function.
*
* @retval
* Queue threshold
*/
uint32_t Qmss_getQueueThreshold (Qmss_QueueHnd hnd)
{
return (uint32_t) CSL_FEXT (qmssLObj.qmQueStatReg->QUEUE_STATUS_CONFIG_GROUP[hnd].QUEUE_STATUS_CONFIG_REG_D,
QM_QUEUE_STATUS_CONFIG_QUEUE_STATUS_CONFIG_REG_D_THRESHOLD);
}
/** ===========================================================================
* @n@b SPI_write
*
* @b Description
* @n This function Write data to specified device.
*
* @b Arguments
* @verbatim
hSpi Pointer to handler
writeBuff Pointer to the write buffer.
buffLen Maximum read buffer size.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Write successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* This function can call by SPI_dataTransaction function.
*
* <b> Post Condition </b>
* @n SPI_deInit can be call after this function call.
*
* @b Modifies
* @n
*
* @b Example
* @verbatim
CSL_SpiHandle hSpi
Uint16 writeBuff[size];
Uint16 buffLen;
CSL_status status;
status = SPI_write(hSpi,&writeBuff, buffLen);
@endverbatim
* ===========================================================================
*/
CSL_Status SPI_write (CSL_SpiHandle hSpi,
Uint16 *writeBuffer,
Uint16 bufLen)
{
Uint16 getWLen;
volatile Uint16 bufIndex;
Uint16 spiStatusReg;
volatile Uint16 spiBusyStatus;
volatile Uint16 spiWcStaus;
volatile Uint16 delay;
bufIndex = 0;
if((NULL == writeBuffer) || (0 == bufLen))
{
return (CSL_ESYS_INVPARAMS);
}
/* Read the word length form the register */
getWLen = CSL_FEXT(CSL_SPI_REGS->SPICR2, SPI_SPICR2_WLEN) + 1;
if(getWLen >= SPI_MAX_WORD_LEN)
{
return (CSL_ESYS_INVPARAMS);
}
/* Write Word length set by the user */
while(bufIndex < bufLen)
{
/* Write to registers more then 16 bit word length */
if(getWLen == 16)
{
CSL_SPI_REGS->SPIDR2 = writeBuffer[bufIndex];
//printf("value in reg = %d, in buffer val = %d\n",(Int16) CSL_SPI_REGS->SPIDR2,(Int16) writeBuffer[bufIndex]);
CSL_SPI_REGS->SPIDR1 = 0x0000;
bufIndex ++;
}
/* Write to register less then or equal to 16 bit word length */
else if(getWLen == 8)
{
CSL_SPI_REGS->SPIDR2 = (Uint16)(writeBuffer[bufIndex] << 0x08);
CSL_SPI_REGS->SPIDR1 = 0x0000; //jb
bufIndex++;
}
//printf("before CSL_FINS, reg val 2= %d, reg val 1 = %d\n",(Int16) CSL_SPI_REGS->SPIDR2, (Int16)CSL_SPI_REGS->SPIDR1);
/* Set command for Writting to registers */
CSL_FINS(CSL_SPI_REGS->SPICR2, SPI_SPICR2_CMD, SPI_WRITE_CMD);
//printf("after CSL_FINS, reg val 2= %d, reg val 1 = %d\n",(Int16) CSL_SPI_REGS->SPIDR2, (Int16)CSL_SPI_REGS->SPIDR1);
for(delay = 0; delay < 100; delay++); //register resetting after delay
//printf("after delay, reg val 2= %d, reg val 1 = %d\n",(Int16) CSL_SPI_REGS->SPIDR2, (Int16)CSL_SPI_REGS->SPIDR1);
do
{
//printf("beginning of while, reg val 2= %d, reg val 1 = %d\n",(Int16) CSL_SPI_REGS->SPIDR2, (Int16)CSL_SPI_REGS->SPIDR1);
spiStatusReg = CSL_SPI_REGS->SPISR1;
spiBusyStatus = (spiStatusReg & CSL_SPI_SPISR1_BSY_MASK);
spiWcStaus = (spiStatusReg & CSL_SPI_SPISR1_WC_MASK);
//printf("end of while iteration, reg val 2= %d, reg val 1 = %d\n",(Int16) CSL_SPI_REGS->SPIDR2, (Int16)CSL_SPI_REGS->SPIDR1);
}while((spiBusyStatus == CSL_SPI_SPISR1_BSY_MASK) &&
(spiWcStaus != CSL_SPI_SPISR1_WC_MASK));
//printf("very end of while loop, reg val 2= %d, reg val 1 = %d\n",(Int16) CSL_SPI_REGS->SPIDR2, (Int16)CSL_SPI_REGS->SPIDR1);
}
//printf("after write while loop, reg val 2= %d, reg val 1 = %d\n",(Int16) CSL_SPI_REGS->SPIDR2, (Int16)CSL_SPI_REGS->SPIDR1);
return (CSL_SOK);
}
/** ============================================================================
* @n@b I2C_read
*
* @b Description
* @n Receives the I2C data from the I2C device.
*
* @b Arguments
* @verbatim
i2cRdBuf I2C Data buffer pointer
dataLength Number bytes to receive
slaveAddr Address of the slave device
masterMode Master mode flag
startStopFlag Flag for the start and stop bits
timeout Time out variable
checkBus Check Bus busy flag
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
* @li CSL_I2C_BUS_BUSY_ERR - Busy Bit Error
* @li CSL_I2C_TIMEOUT_ERROR - Time out Error has occured
* @li CSL_I2C_RECEIVE_OVERFLOW_ERR - Recieve Register over flow error
*
* <b> Pre Condition </b>
* @n I2C_init and I2C_config/I2C_setup should be called successfully
*
* <b> Post Condition </b>
* @n Receives the I2C data
*
* @b Modifies
* @n I2C data buffer
*
* @b Example
* @verbatim
#define CSL_I2C_SYS_CLK (12) // In MHz
#define CSL_I2C_BUS_FREQ (10) // In KHz
#define CSL_I2C_DATA_SIZE (16)
#define CSL_I2C_EEPROM_ADDR (0x50)
#define CSL_I2CEEPROM_ADDR_SIZE (2)
Uint16 i2cDataBuf[CSL_I2C_DATA_SIZE];
CSL_Status status;
CSL_I2cSetup i2cSetup;
i2cSetup.addrMode = CSL_I2C_ADDR_7BIT;
i2cSetup.bitCount = CSL_I2C_BC_8BITS;
i2cSetup.loopBack = CSL_I2C_LOOPBACK_DISABLE;
i2cSetup.freeMode = CSL_I2C_FREEMODE_DISABLE;
i2cSetup.repeatMode = CSL_I2C_REPEATMODE_DISABLE;
i2cSetup.ownAddr = CSL_I2C_OWN_ADDR;
i2cSetup.sysInputClk = CSL_I2C_SYS_CLK;
i2cSetup.i2cBusFreq = CSL_I2C_BUS_FREQ;
status = I2C_init(CSL_I2C0);
....
status = I2C_setup(&i2cSetup);
....
....
status = I2C_read(i2cDataBuf, CSL_I2C_DATA_SIZE, CSL_I2C_EEPROM_ADDR,
TRUE, 1, CSL_I2C_MAX_TIMEOUT, FALSE);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_read(Uint16 *i2cRdBuf,
Uint16 dataLength,
Uint16 slaveAddr,
Bool masterMode,
Uint16 startStopFlag,
Uint16 timeout,
Bool checkBus)
{
Uint16 looper;
Uint16 dataCount;
Uint16 statusByte;
if((i2cRdBuf != NULL) && (dataLength !=0))
{
/* Set the Rx mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_TRX, CLEAR);
/* Set the data length */
CSL_FINS(i2cHandle->i2cRegs->ICCNT, I2C_ICCNT_ICDC, dataLength);
if(masterMode == TRUE)
{
/* Set the slave address */
CSL_FINS(i2cHandle->i2cRegs->ICSAR, I2C_ICSAR_SADDR, slaveAddr);
/* Enable Master mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, SET);
/* Set the stop bit */
if((startStopFlag & CSL_I2C_STOP) == CSL_I2C_STOP)
{
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STP, SET);
}
/* Set the start bit */
if((startStopFlag & CSL_I2C_START) == CSL_I2C_START)
{
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STT, SET);
}
}
else
{
/* Disable Master mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, CLEAR);
}
if(checkBus == TRUE)
{
/* check for bus busy */
for(looper = 0; looper < timeout; looper++)
{
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR, I2C_ICSTR_BB);
if (statusByte == FALSE)
{
break;
}
}
if(looper >= timeout)
{
/* bus busy timeout error */
return(CSL_I2C_BUS_BUSY_ERR);
}
}
for(dataCount = 0; dataCount < dataLength; dataCount++)
{
/* Check for ICRRDY status */
for(looper = 0; looper < timeout; looper++)
{
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR,
I2C_ICSTR_ICRRDY);
if(statusByte == TRUE)
{
break;
}
}
if(looper >= timeout)
{
return(CSL_I2C_TIMEOUT_ERROR);
}
/* Read data from the data Rx register */
*i2cRdBuf++ = CSL_FEXT(i2cHandle->i2cRegs->ICDRR, I2C_ICDRR_D);
/* Check for Overflow status */
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR, I2C_ICSTR_RSFULL);
if(statusByte == TRUE)
{
return(CSL_I2C_RECEIVE_OVERFLOW_ERR);
}
}
}
else
{
return(CSL_ESYS_INVPARAMS);
}
return(CSL_SOK);
}
/** ============================================================================
* @n@b I2C_write
*
* @b Description
* @n Transmits the I2C data to I2C device.
*
* @b Arguments
* @verbatim
i2cWrBuf I2C Data buffer pointer
dataLength Number bytes to transmit
slaveAddr Address of the slave device
masterMode Master mode flag
startStopFlag Flag for the start and stop bits
timeout Time out variable
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
* @li CSL_I2C_BUS_BUSY_ERR - Busy Bit Error
* @li CSL_I2C_TIMEOUT_ERROR - Time out Error has occured
* @li CSL_I2C_NACK_ERR - No acknowledgement Error
*
* <b> Pre Condition </b>
* @n I2C_init and I2C_config/I2C_setup should be called successfully
*
* <b> Post Condition </b>
* @n Transmits the I2C data
*
* @b Modifies
* @n I2C transmit register
*
* @b Example
* @verbatim
#define CSL_I2C_SYS_CLK (12) // In MHz
#define CSL_I2C_BUS_FREQ (10) // In KHz
#define CSL_I2C_DATA_SIZE (16)
#define CSL_I2C_EEPROM_ADDR (0x50)
Uint16 i2cDataBuf[CSL_I2C_DATA_SIZE];
CSL_Status status;
CSL_I2cSetup i2cSetup;
i2cSetup.addrMode = CSL_I2C_ADDR_7BIT;
i2cSetup.bitCount = CSL_I2C_BC_8BITS;
i2cSetup.loopBack = CSL_I2C_LOOPBACK_DISABLE;
i2cSetup.freeMode = CSL_I2C_FREEMODE_DISABLE;
i2cSetup.repeatMode = CSL_I2C_REPEATMODE_DISABLE;
i2cSetup.ownAddr = CSL_I2C_OWN_ADDR;
i2cSetup.sysInputClk = CSL_I2C_SYS_CLK;
i2cSetup.i2cBusFreq = CSL_I2C_BUS_FREQ;
status = I2C_init(CSL_I2C0);
....
status = I2C_setup(&i2cSetup);
....
....
status = I2C_write(i2cDataBuf, CSL_I2C_DATA_SIZE,
CSL_I2C_EEPROM_ADDR, TRUE, 1,
CSL_I2C_MAX_TIMEOUT);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_write(Uint16 *i2cWrBuf,
Uint16 dataLength,
Uint16 slaveAddr,
Bool masterMode,
Uint16 startStopFlag,
Uint16 timeout)
{
Uint16 looper;
Uint16 dataCount;
Uint16 statusByte;
if((i2cWrBuf != NULL) && (dataLength !=0))
{
/* check for bus busy */
for(looper = 0; looper < timeout; looper++)
{
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR, I2C_ICSTR_BB);
if(statusByte == FALSE)
{
break;
}
}
if(looper >= timeout)
{
/* bus busy timeout error */
return(CSL_I2C_BUS_BUSY_ERR);
}
/* Set the Tx mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_TRX, SET);
/* Set the data length */
CSL_FINS(i2cHandle->i2cRegs->ICCNT, I2C_ICCNT_ICDC, dataLength);
if(masterMode == TRUE)
{
/* Set the slave address */
CSL_FINS(i2cHandle->i2cRegs->ICSAR, I2C_ICSAR_SADDR, slaveAddr);
/* Enable Master mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, SET);
/* Set the stop bit */
if((startStopFlag & CSL_I2C_STOP) == CSL_I2C_STOP)
{
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STP, SET);
}
/* Set the start bit */
if((startStopFlag & CSL_I2C_START) == CSL_I2C_START)
{
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_STT, SET);
}
}
else
{
/* Disable Master mode */
CSL_FINST(i2cHandle->i2cRegs->ICMDR, I2C_ICMDR_MST, CLEAR);
}
for(dataCount = 0; dataCount < dataLength; dataCount++)
{
/* Check for ICXRDY status */
for(looper = 0; looper < timeout; looper++)
{
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR,
I2C_ICSTR_ICXRDY);
if(statusByte == TRUE)
{
break;
}
}
if(looper >= timeout)
{
return(CSL_I2C_TIMEOUT_ERROR);
}
/* Write data to the data Tx register */
CSL_FINS(i2cHandle->i2cRegs->ICDXR, I2C_ICDXR_D, *i2cWrBuf++);
for(looper = 0; looper < timeout; looper++)
{
/* Check for NACK status */
statusByte = CSL_FEXT(i2cHandle->i2cRegs->ICSTR,
I2C_ICSTR_NACK);
if(statusByte == FALSE)
{
break;
}
}
if(looper >= timeout)
{
return(CSL_I2C_NACK_ERR);
}
}
}
else
{
return(CSL_ESYS_INVPARAMS);
}
return(CSL_SOK);
}
int DRV_imageTuneSaveData(IMAGE_TUNE_SaveDataInfo *info)
{
char *filename;
Uint32 doneFlag;
int status;
switch (info->dataFormat)
{
case DRV_DATA_FORMAT_RAW:
if (!DRV_imageTuneIsSaveRawData() && !DRV_imageTuneIsSendRawData())
{
return OSA_EFAIL;
}
filename = gDRV_imageTuneObj.rawDataSaveFileName;
doneFlag = DRV_IMAGE_TUNE_DAVE_SAVE_FLAG_RAW;
break;
case DRV_DATA_FORMAT_YUV422:
case DRV_DATA_FORMAT_YUV420:
if (!DRV_imageTuneIsSaveYuvData() && !DRV_imageTuneIsSendYuvData())
{
return OSA_EFAIL;
}
filename = gDRV_imageTuneObj.yuvDataSaveFileName;
doneFlag = DRV_IMAGE_TUNE_DAVE_SAVE_FLAG_YUV;
break;
default:
return OSA_EFAIL;
}
info->rawDataStartPhase = 0;
info->rawDataBitsPerPixel = 0;
info->rawDataFormat = 0;
if (info->dataFormat == DRV_DATA_FORMAT_RAW)
{
// extract info from ISIF registers
info->rawDataStartPhase = DRV_imageTuneGetRawDataStartPhase();
//info->rawDataStartPhase = CSL_FEXT(gCSL_vpssHndl.isifRegs->CCOLP, ISIF_CCOLP_CP01_0);
info->rawDataBitsPerPixel = 16 - CSL_FEXT(gCSL_vpssHndl.isifRegs->CGAMMAWD, ISIF_CGAMMAWD_GWDI);
info->rawDataFormat = 0; // normal (no compression)
if (CSL_FEXT(gCSL_vpssHndl.isifRegs->MISC, ISIF_MISC_DPCMEN))
{
info->rawDataFormat = 2; // DPCM compression 12bits/pixel packed in DDR
info->rawDataBitsPerPixel = 12; // after Inverse DPCM
}
else if (CSL_FEXT(gCSL_vpssHndl.isifRegs->CGAMMAWD, ISIF_CGAMMAWD_CCDTBL))
{
// A-law compression, 8bits/pixel packed in DDR
info->rawDataFormat = 1;
info->rawDataBitsPerPixel = 10; // after Inverse A-law
}
#if 0
OSA_printf(" DRV:IMAGE TUNE: phase = %d, format = %d, bits/pixel = %d\n",
info->rawDataStartPhase,
info->rawDataFormat,
info->rawDataBitsPerPixel
);
#endif
}
status = ALG_aewbGetTTawb(&info->awbData); // IT
/* H3A Regs */
memcpy(info->awbData.h3aRegs, csl_h3aRegs,sizeof(info->awbData.h3aRegs)); //(Uint32*)CSL_H3A_0_REGS
status = IMAGE_TUNE_SaveData(filename, info);
if (DRV_imageTuneIsSaveRawData() || DRV_imageTuneIsSaveYuvData())
{
if (info->dataFormat==DRV_DATA_FORMAT_RAW)
{
gDRV_imageTuneObj.isRawDataSave = FALSE;
}
else
{
gDRV_imageTuneObj.isYuvDataSave = FALSE;
}
}
else if (DRV_imageTuneIsSendRawData() || DRV_imageTuneIsSendYuvData()) //ETH
{
if (info->dataFormat==DRV_DATA_FORMAT_RAW)
{
gDRV_imageTuneObj.isRawDataSend = FALSE;
doneFlag = DRV_IMAGE_TUNE_DAVE_SEND_FLAG_RAW;
}
else
{
gDRV_imageTuneObj.isYuvDataSend = FALSE;
doneFlag = DRV_IMAGE_TUNE_DAVE_SEND_FLAG_YUV;
}
}
OSA_flgSet(&gDRV_imageTuneObj.dataSaveFlg, doneFlag);
return status;
}
void usbProcessing(void)
{
static Bool usbDevDisconnect = TRUE;
Uint16 saveIndex;
Uint16 bytesRem;
pUsbEpHandle tempEpH;
Uint16 *strDescPtr;
Uint16 endpt;
CSL_UsbBoolean txRxStatus;
int i;
if(usbDevDisconnect == TRUE) {
// wait for connecting
if(CSL_FEXT(usbRegisters->DEVCTL, USB_DEVCTL_VBUS) ==
CSL_USB_DEVCTL_VBUS_ABOVEVBUSVALID) {
usbDevDisconnect = FALSE;
// connectDev
CSL_FINS(usbRegisters->FADDR_POWER, USB_FADDR_POWER_SOFTCONN, TRUE);
}
}
if((taskList & USBPROCESSING) == 0) return;
/* Read the masked interrupt status register */
pContext->dwIntSourceL = usbRegisters->INTMASKEDR1;
pContext->dwIntSourceH = usbRegisters->INTMASKEDR2;
/* Reset interrupt */
if(pContext->dwIntSourceH & CSL_USB_GBL_INT_RESET) {
usbRegisters->INDEX_TESTMODE &= 0x00ff;
if(usbBulkOutEpObj.epNum == CSL_USB_IN_EP1)
CSL_FINS(usbRegisters->INDEX_TESTMODE,
USB_INDEX_TESTMODE_EPSEL, CSL_USB_EP1);
else
CSL_FINS(usbRegisters->INDEX_TESTMODE,
USB_INDEX_TESTMODE_EPSEL, CSL_USB_EP2);
CSL_FINS(usbRegisters->PERI_CSR0_INDX,
USB_PERI_CSR0_INDX_RXPKTRDY, TRUE);
}
/* Resume interrupt */
if(pContext->dwIntSourceH & CSL_USB_GBL_INT_RESUME) {
pContext->remoteWkpStat = CSL_USB_TRUE;
CSL_FINS(usbRegisters->FADDR_POWER, USB_FADDR_POWER_RESUME, TRUE);
/* Give 10 msecs delay before resetting resume bit */
EZDSP5535_waitusec(10000);
CSL_FINS(usbRegisters->FADDR_POWER, USB_FADDR_POWER_RESUME, FALSE);
}
/* Check end point0 interrupts */
if(pContext->dwIntSourceL & CSL_USB_TX_RX_INT_EP0) {
saveIndex = usbRegisters->INDEX_TESTMODE;
CSL_FINS(usbRegisters->INDEX_TESTMODE,
USB_INDEX_TESTMODE_EPSEL, CSL_USB_EP0);
USB_getSetupPacket(CSL_USB0, &usbSetup, TRUE);
if(usbRegisters->PERI_CSR0_INDX & CSL_USB_PERI_CSR0_INDX_RXPKTRDY_MASK) {
/* Service the RXPKTRDY after reading the FIFO */
CSL_FINS(usbRegisters->PERI_CSR0_INDX,
USB_PERI_CSR0_INDX_SERV_RXPKTRDY, TRUE);
/* GET DESCRIPTOR Req */
switch(usbSetup.bRequest) {
/* zero data */
case CSL_USB_SET_FEATURE:
switch(usbSetup.wValue) {
case CSL_USB_FEATURE_ENDPOINT_STALL:
/* updated set and clear endpoint stall
* to work with logical endpoint num
*/
endpt = (usbSetup.wIndex) & 0xFF;
hEPx = USB_epNumToHandle(CSL_USB0, endpt);
if(!(USB_getEndptStall(hEPx, &status)))
USB_stallEndpt(hEPx);
break;
case CSL_USB_FEATURE_REMOTE_WAKEUP:
if(!pContext->remoteWkpStat)
pContext->remoteWkpStat = CSL_USB_TRUE;
break;
default:
break;
}
CSL_FINS(usbRegisters->PERI_CSR0_INDX,
USB_PERI_CSR0_INDX_SERV_RXPKTRDY, TRUE);
CSL_FINS(usbRegisters->PERI_CSR0_INDX,
USB_PERI_CSR0_INDX_DATAEND, TRUE);
break;
case CSL_USB_CLEAR_FEATURE:
switch(usbSetup.wValue) {
case CSL_USB_FEATURE_ENDPOINT_STALL:
endpt = (usbSetup.wIndex) & 0xFF;
hEPx = USB_epNumToHandle(CSL_USB0, endpt);
if(USB_getEndptStall(hEPx, &status))
USB_clearEndptStall(hEPx);
break;
case CSL_USB_FEATURE_REMOTE_WAKEUP:
if(pContext->remoteWkpStat)
pContext->remoteWkpStat = CSL_USB_FALSE;
break;
default:
break;
}
break;
case CSL_USB_SET_CONFIGURATION:
case CSL_USB_SET_INTERFACE:
endpt = (usbSetup.wIndex) & 0xFF;
hEPx = USB_epNumToHandle(CSL_USB0, endpt);
USB_postTransaction(hEPx, 0, NULL, CSL_USB_IOFLAG_NONE);
/* DataEnd + ServicedRxPktRdy */
CSL_FINS(usbRegisters->PERI_CSR0_INDX,
USB_PERI_CSR0_INDX_SERV_RXPKTRDY, TRUE);
CSL_FINS(usbRegisters->PERI_CSR0_INDX,
USB_PERI_CSR0_INDX_DATAEND, TRUE);
break;
case CSL_USB_GET_DESCRIPTOR:
switch(usbSetup.wValue >> 8) {
case CSL_USB_DEVICE_DESCRIPTOR_TYPE:
status = USB_postTransaction(hEpObjArray[1],
deviceDesc[0]&0xFF, deviceDesc,
CSL_USB_IN_TRANSFER);
break;
case CSL_USB_CONFIGURATION_DESCRIPTOR_TYPE:
if(usbSetup.wLength == 0x0009)
status = USB_postTransaction(hEpObjArray[1],
9, cfgDesc,
CSL_USB_IN_TRANSFER);
else
status = USB_postTransaction(hEpObjArray[1],
cfgDesc[1], cfgDesc,
CSL_USB_IN_TRANSFER);
break;
case CSL_USB_STRING_DESCRIPTOR_TYPE:
i = usbSetup.wValue & 0xFF;
if(i < 4) {
strDescPtr = (Uint16 *)strDesc[i];
status = USB_postTransaction(hEpObjArray[1],
strDesc[i][0]&0xFF, strDescPtr,
CSL_USB_IN_TRANSFER);
}
break;
default:
break;
}
CSL_FINS(usbRegisters->PERI_CSR0_INDX,
USB_PERI_CSR0_INDX_TXPKTRDY, TRUE);
CSL_FINS(usbRegisters->PERI_CSR0_INDX,
USB_PERI_CSR0_INDX_DATAEND, TRUE);
break;
case CSL_USB_SET_ADDRESS:
devAddr = usbSetup.wValue;
CSL_FINS(usbRegisters->PERI_CSR0_INDX,
USB_PERI_CSR0_INDX_SERV_RXPKTRDY, TRUE);
CSL_FINS(usbRegisters->PERI_CSR0_INDX,
USB_PERI_CSR0_INDX_DATAEND, TRUE);
break;
default:
break;
}
} else {
