/** ============================================================================
* @n@b Convert_CoreLocal2GlobalAddr
*
* @b Description
* @n This API converts a core local L2 address to a global L2 address.
*
* @param[in]
* @n addr L2 address to be converted to global.
*
* @return UInt32
* @n >0 Global L2 address
* =============================================================================
*/
UInt32 Convert_CoreLocal2GlobalAddr (UInt32 addr)
{
uint32_t coreNum;
/* Get the core number. */
coreNum = CSL_chipReadDNUM();
/* Check if the address is a valid Local L2 address to convert */
if ( (addr >= (uint32_t) 0x800000) &&
(addr < (uint32_t) 0x880000) )
{
/* Compute the global address. */
return ((1 << 28) | (coreNum << 24) | (addr & 0x00ffffff));
}
else
{
return (addr);
}
// UInt32 coreNum;
//
// /* Get the core number. */
// coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);
//
// /* Compute the global address. */
// return ((1 << 28) | (coreNum << 24) | (addr & 0x00ffffff));
}
/**
* ============================================================================
* @n@b Osal_biosInterruptCsExit
*
* @b brief
* @n This API needs to be called to exit a previously
* acquired critical section lock using @a Osal_biosInterruptCsEnter ()
* API. It restores the saved interrupt context and enables back the
* interrupts.
*
* @param[in] None
*
* @return None
* =============================================================================
*/
Void Osal_biosInterruptCsExit ()
{
/* Enable all interrupts.
*
* Release interrupt lock.
*/
Hwi_restore(coreKey [CSL_chipReadDNUM ()]);
return;
}
/**
* ============================================================================
* @n@b Osal_fftcGlobal2Local
*
* @b brief
* @n Utility function which converts a global to core local address.
*
* @param[in] gaddr
* Global address to be converted
*
* @return
* Local Address
* =============================================================================
*/
static UInt32 Osal_fftcGlobal2Local (UInt32 gaddr)
{
UInt32 corenum;
/* Get the core number. */
corenum = CSL_chipReadDNUM ();
/* Compute the global address. */
return (gaddr & ~((1 << 28) | (corenum << 24)));
}
/**
* ============================================================================
* @n@b Osal_fftcLocal2Global
*
* @b brief
* @n Utility function which converts a core local address to a global
* address.
*
* @param[in] addr
* Local address to be converted
*
* @return
* Global Address
* =============================================================================
*/
static UInt32 Osal_fftcLocal2Global (UInt32 addr)
{
UInt32 corenum;
/* Get the core number. */
corenum = CSL_chipReadDNUM ();
/* Compute the global address. */
return ((1 << 28) | (corenum << 24) | (addr & 0x00ffffff));
}
/**
* ============================================================================
* @n@b Osal_biosInterruptCsEnter
*
* @b brief
* @n This API ensures protection against interrupts to the caller. It prevents
* the caller from switching to interrupt context from the application
* thread/process context.
*
* @param[in] None
*
* @return None
* =============================================================================
*/
Void Osal_biosInterruptCsEnter ()
{
/* Disable all interrupts.
*
* Acquire interrupt lock to protect from any context switches
* from application thread/process context.
*/
coreKey [CSL_chipReadDNUM ()] = Hwi_disable();
return;
}
/**
* ============================================================================
* @n@b Osal_qmssCsExit
*
* @b brief
* @n This API needs to be called to exit a previously
* acquired critical section lock using @a Osal_fftcQmssCsEnter ()
* API. It resets the multi-core and multi-threaded lock,
* enabling another process/core to grab QMSS access.
*
* @param[in] CsHandle
* Handle for unlocking critical section.
*
* @return None
* =============================================================================
*/
Void Osal_qmssCsExit (Void* CsHandle)
{
/* Enable all interrupts and enables the OS scheduler back on.
*
* Release multi-threaded / multi-process lock on this core.
*/
Hwi_restore(coreKey [CSL_chipReadDNUM ()]);
/* Release the hardware semaphore
*
* Release multi-core lock.
*/
CSL_semReleaseSemaphore (QMSS_HW_SEM);
return;
}
/**
* ============================================================================
* @n@b Osal_qmssCsEnter
*
* @b brief
* @n This API ensures multi-core and multi-threaded
* synchronization to the caller.
*
* This is a BLOCKING API.
*
* This API ensures multi-core synchronization between
* multiple processes trying to access QMSS shared
* library at the same time.
*
* @param[in] None
*
* @return
* Handle used to lock critical section
* =============================================================================
*/
Void* Osal_qmssCsEnter (Void)
{
/* Get the hardware semaphore.
*
* Acquire Multi core QMSS synchronization lock
*/
while ((CSL_semAcquireDirect (QMSS_HW_SEM)) == 0);
/* Disable all interrupts and OS scheduler.
*
* Acquire Multi threaded / process synchronization lock.
*/
coreKey [CSL_chipReadDNUM ()] = Hwi_disable();
return NULL;
}
VOID Signal_Post( Signal *pThis )
{
//SEM_postBinary(pThis->Handle);
#ifdef ToFindExcpError
//LOG_TRACE1("Inside signalpost pThis->Handle : 0x%x",pThis->Handle);
if(CSL_chipReadDNUM ()==1)
{
NumSignal++;
LOG_TRACE1("signal posting :%d ",NumSignal);
}
#endif
Semaphore_post(pThis->Handle);
#ifdef ToFindExcpError
// LOG_TRACE0(" signal posted");
#endif
}
