int
sme_send(void *dev, char *buf, unsigned len)
{
struct local *l = dev;
volatile struct desc *txd;
unsigned txstat, loop;
/* send a single frame with no T1_TER|T1_TCH designation */
wbinv(buf, len);
txd = &l->txd[l->tx];
txd->xd2 = htole32(VTOPHYS(buf));
txd->xd1 = htole32(T1_FS | T1_LS | (len & T1_FL));
txd->xd0 = htole32(T0_OWN | (len & T0_FL) << 16);
wbinv(txd, sizeof(struct desc));
CSR_WRITE(l, TXPOLLD, 01); /* start transmission */
loop = 100;
do {
txstat = le32toh(txd->xd0);
if (txstat & T0_ES)
break;
if ((txstat & T0_OWN) == 0)
goto done;
DELAY(10);
inv(txd, sizeof(struct desc));
} while (--loop != 0);
printf("xmit failed\n");
return -1;
done:
l->tx ^= 1;
return len;
}
int
kse_send(void *dev, char *buf, unsigned len)
{
struct local *l = dev;
volatile struct desc *txd;
unsigned txstat, loop;
wbinv(buf, len);
txd = &l->txd;
txd->xd2 = htole32(VTOPHYS(buf));
txd->xd1 = htole32(T1_FS | T1_LS | (len & T1_TBS_MASK));
txd->xd0 = htole32(T0_OWN);
wbinv(txd, sizeof(struct desc));
CSR_WRITE(l, MDTSC, 01); /* start transmission */
loop = 100;
do {
txstat = le32toh(txd->xd0);
if ((txstat & T0_OWN) == 0)
goto done;
DELAY(10);
inv(txd, sizeof(struct desc));
} while (--loop != 0);
printf("xmit failed\n");
return -1;
done:
return len;
}
static int s3c4510b_putc(char c)
{
CSR_WRITE(DEBUG_TX_BUFF_BASE, c);
while(!(CSR_READ(DEBUG_CHK_STAT_BASE) & DEBUG_TX_DONE_CHECK_BIT));
if(c == '\n')
s3c4510b_putc('\r');
}
int
sme_recv(void *dev, char *buf, unsigned maxlen, unsigned timo)
{
struct local *l = dev;
volatile struct desc *rxd;
unsigned bound, rxstat, len;
uint8_t *ptr;
bound = 1000 * timo;
printf("recving with %u sec. timeout\n", timo);
again:
rxd = &l->rxd[l->rx];
do {
inv(rxd, sizeof(struct desc));
rxstat = le32toh(rxd->xd0);
if ((rxstat & R0_OWN) == 0)
goto gotone;
DELAY(1000); /* 1 milli second */
} while (--bound > 0);
errno = 0;
return -1;
gotone:
if (rxstat & R0_ES) {
rxd->xd0 = htole32(R0_OWN);
wbinv(rxd, sizeof(struct desc));
l->rx ^= 1;
CSR_WRITE(l, RXPOLLD, 01); /* restart receiving */
goto again;
}
/* good frame */
len = (rxstat & R0_FL) >> 16 /* no FCS included */;
if (len > maxlen)
len = maxlen;
ptr = l->rxstore[l->rx];
inv(ptr, len);
memcpy(buf, ptr, len);
rxd->xd0 = htole32(R0_OWN);
wbinv(rxd, sizeof(struct desc));
l->rx ^= 1;
CSR_WRITE(l, RXPOLLD, 01); /* necessary? */
return len;
}
void
mii_write(struct local *l, int phy, int reg, int val)
{
uint32_t ctl;
do {
ctl = CSR_READ(l, MIIADDR);
} while (ctl & 01);
ctl = (phy << 11) | (reg << 6) | (1 << 1); /* WRITE op */
CSR_WRITE(l, MIIDATA, val);
}
/* Map the CompactFlash interface to our system */
static void InitCFI(UINT8 dbus)
{
UINT32 val;
// Use EXTIO0 as CFI
if(!dbus)//8-bit
val=(EBIO0_BA<<1)|0x00007FFD;
else//16-bit
val=(EBIO0_BA<<1)|0x00007FFE;
CSR_WRITE(EXT0CON,val);
//KDEBUG("Map the CompactFlash interface to our system");
}
static int
mii_read(struct local *l, int phy, int reg)
{
uint32_t ctl;
do {
ctl = CSR_READ(l, MIIADDR);
} while (ctl & 01);
ctl = (phy << 11) | (reg << 6) | (0 << 1); /* READ op */
CSR_WRITE(l, MIIADDR, ctl);
do {
ctl = CSR_READ(l, MIIADDR);
} while (ctl & 01);
return CSR_READ(l, MIIDATA);
}
static int s3c4510b_decomp_setup()
{
CSR_WRITE(DEBUG_UARTLCON_BASE, DEBUG_ULCON_REG_VAL);
CSR_WRITE(DEBUG_UARTCONT_BASE, DEBUG_UCON_REG_VAL);
CSR_WRITE(DEBUG_UARTBRD_BASE, DEBUG_UBRDIV_REG_VAL);
}
/*!
* \brief Initialize system timer.
*
* This function is automatically called by Nut/OS
* during system initialization.
*
* Nut/OS uses on-chip timer 0 for its timer services.
* Applications should not modify any registers of this
* timer, but make use of the Nut/OS timer API. Timer 1
* and timer 2 are available to applications.
*/
void NutRegisterTimer(void (*handler) (void *))
{
os_handler = handler;
#if defined(MCU_AT91R40008)
/* Disable the Clock Counter */
outr(TC0_CCR, TC_CLKDIS);
/* Disable all interrupts */
outr(TC0_IDR, 0xFFFFFFFF);
/* Clear the status register. */
dummy = inr(TC0_SR);
/* Select divider and compare trigger */
outr(TC0_CMR, TC_CLKS_MCK32 | TC_CPCTRG);
/* Enable the Clock counter */
outr(TC0_CCR, TC_CLKEN);
/* Validate the RC compare interrupt */
outr(TC0_IER, TC_CPCS);
/* Disable timer 0 interrupts. */
outr(AIC_IDCR, _BV(TC0_ID));
/* Set the TC0 IRQ handler address */
outr(AIC_SVR(4), (unsigned int)Timer0Entry);
/* Set the trigg and priority for timer 0 interrupt */
/* Level 7 is highest, level 0 lowest. */
outr(AIC_SMR(4), (AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 0x4));
/* Clear timer 0 interrupt */
outr(AIC_ICCR, _BV(TC0_ID));
/* Enable timer 0 interrupts */
outr(AIC_IECR, _BV(TC0_ID));
/* Set compare value for 1 ms. */
outr(TC0_RC, 0x80F);
/* Software trigger starts the clock. */
outr(TC0_CCR, TC_SWTRG);
#elif defined(MCU_S3C4510B)
INT_DISABLE(IRQ_TIMER);
CSR_WRITE(TCNT0, 0);
CSR_WRITE(TDATA0, CLOCK_TICK_RATE);
CSR_WRITE(TMOD, TMOD_TIMER0_VAL);
CLEAR_PEND_INT(IRQ_TIMER);
NutRegisterIrqHandler(
&InterruptHandlers[IRQ_TIMER], handler, 0);
INT_ENABLE(IRQ_TIMER);
#elif defined(MCU_GBA)
/* Disable master interrupt. */
outw(REG_IME, 0);
/* Set global interrupt vector. */
NutRegisterIrqHandler(&sig_TMR3, Timer3Entry, 0);
/* Enable timer and timer interrupts. */
outdw(REG_TMR3CNT, TMR_IRQ_ENA | TMR_ENA | 48756);
/* Enable timer 3 interrupts. */
outw(REG_IE, inw(REG_IE) | INT_TMR3);
/* Enable master interrupt. */
outw(REG_IME, 1);
#else
#warning "MCU not defined"
#endif
}
void *
sme_init(unsigned tag, void *data)
{
struct local *l;
struct desc *txd, *rxd;
unsigned mac32, mac16, val, fdx;
uint8_t *en;
l = ALLOC(struct local, 32); /* desc alignment */
memset(l, 0, sizeof(struct local));
l->csr = DEVTOV(pcicfgread(tag, 0x1c)); /* BAR3 mem space, LE */
l->phy = 1; /* 9420 internal PHY */
en = data;
mac32 = CSR_READ(l, ADDRL);
mac16 = CSR_READ(l, ADDRH);
en[0] = mac32;
en[1] = mac32 >> 8;
en[2] = mac32 >> 16;
en[3] = mac32 >> 24;
en[4] = mac16;
en[5] = mac16 >> 8;
printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
en[0], en[1], en[2], en[3], en[4], en[5]);
DPRINTF(("PHY %d (%04x.%04x)\n", l->phy,
mii_read(l, l->phy, 2), mii_read(l, l->phy, 3)));
mii_dealan(l, 5);
/* speed and duplexity can be seen in MII 31 */
val = mii_read(l, l->phy, 31);
fdx = !!(val & (1U << 4));
printf("%s", (val & (1U << 3)) ? "100Mbps" : "10Mbps");
if (fdx)
printf("-FDX");
printf("\n");
txd = &l->txd[0];
rxd = &l->rxd[0];
rxd[0].xd0 = htole32(R0_OWN);
rxd[0].xd1 = htole32(R1_RCH | FRAMESIZE);
rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0]));
rxd[0].xd3 = htole32(VTOPHYS(&rxd[1]));
rxd[1].xd0 = htole32(R0_OWN);
rxd[1].xd1 = htole32(R1_RER | FRAMESIZE);
rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1]));
/* R1_RER neglects xd3 */
l->tx = l->rx = 0;
wbinv(l, sizeof(struct local));
CSR_WRITE(l, TXDBASE, VTOPHYS(txd));
CSR_WRITE(l, RXDBASE, VTOPHYS(rxd));
val = MACCR_TXEN | MACCR_RXEN;
if (fdx)
val |= MACCR_FDPX;
CSR_WRITE(l, BUSMODE, 0);
CSR_WRITE(l, DMACCTL, DMACCTL_ST | DMACCTL_SR);
CSR_WRITE(l, MAC_CR, val); /* (FDX), Tx/Rx enable */
CSR_WRITE(l, RXPOLLD, 01); /* start receiving */
return l;
}
void winbond_watchdog_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
CSR_WRITE(WTCR, (CSR_READ(WTCR)&0xF7)|0x01);
}
void winbond_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
CSR_WRITE(TISR,2); /* clear TIF0 */
do_timer(regs);
}
