__externC void hal_system_init( void )
{
CYG_ADDRESS base;
// Enable peripheral clocks in RCC
base = CYGHWR_HAL_STM32_RCC;
// All GPIO ports
// FIXME: this should be done in variant HAL at point of gpio_set
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB1ENR,
#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) // enable CCM clock
BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN) |
#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) |
BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOB) |
BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) |
BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) |
BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOE) |
BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOF) |
BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOG) |
BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOH) |
BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOI) );
// Enable FSMC
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3ENR,
BIT_(CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC) );
#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_ROMINT) | defined(CYG_HAL_STARTUP_SRAM)
// Reset FSMC in case it was already enabled. This should set
// all regs back to default documented values, so we don't need
// to do any precautionary resets.
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3RSTR,
BIT_(CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC) );
// Bring out of reset:
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3RSTR, 0 );
#endif
#if defined(CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO)
// Use HSE clock as the MCO1 clock signals for PHY
{
cyg_uint32 acr;
HAL_READ_UINT32(base + CYGHWR_HAL_STM32_RCC_CFGR, acr);
acr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE |
CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1;
HAL_WRITE_UINT32(base + CYGHWR_HAL_STM32_RCC_CFGR, acr);
}
#endif
// Set all unused GPIO lines to input with pull down to prevent
// them floating and annoying any external hardware.
// GPIO Ports C..I reset GPIOx_MODER to 0x00000000
// GPIO Ports A..I reset GPIOx_OTYPER to 0x00000000
// CPIO Ports A,C..I reset GPIOx_OSPEEDR to 0x00000000
// GPIO Ports C..I reset GPIOx_PUPDR to 0x00000000
// GPIO Port A resets GPIOA_MODER to 0xA8000000
// GPIO Port A resets GPIOA_PUPDR to 0x64000000
// GPIO Port A keeps the default JTAG pins on PA13,14,15
base = CYGHWR_HAL_STM32_GPIOA;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x02AAAAAA );
// GPIO Port B resets GPIOB_MODER to 0x00000280
// GPIO Port B resets GPIOB_OSPEEDR to 0x000000C0
// GPIO Port B resets GPIOB_PUPDR to 0x00000100
// GPIO Port B keeps the default JTAG pins on PB3,4
base = CYGHWR_HAL_STM32_GPIOB;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAAAA82A );
// GPIO Port C - setup PC7 for LED4 as GPIO out, RS232 (USART4) on PC10,11.
// Rest stay default, with pulldowns on all except PC14,15 (OSC32)
// just in case that is important.
base = CYGHWR_HAL_STM32_GPIOC;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0x00008800 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x0A0A2AAA );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00A04000 );
// GPIO Port D - setup FSMC for SRAM (PD0-1,3-15) and MicroSDcard (PD2) alternate functions
base = CYGHWR_HAL_STM32_GPIOD;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0xCCCCCCCC );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCCCCCC );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAAAAAAAA );
// TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
// GPIO Port E - setup FSMC alternate function. PE0-1,3-4,7-15.
// But not PE5 (A21), PE6(A22), PE2(A23) which are not connected to SRAM.
base = CYGHWR_HAL_STM32_GPIOE;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0xC00CC0CC );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCCCCCC );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00002820 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAAAA828A );
// TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
// GPIO Port F - setup FSMC alternate function. PF0-5,12-15.
// But not PF6-11 which aren't connected to SRAM.
base = CYGHWR_HAL_STM32_GPIOF;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0x00CCCCCC );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCC0000 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00AAA000 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAA000AAA );
// TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
// GPIO Port G - setup FSMC alternate function. PG0-5,9,10.
// Other FSMC pins not connected to SRAM.
// LED1 is PG6, LED2 is PG8, so set as GPIO out.
base = CYGHWR_HAL_STM32_GPIOG;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0x00CCCCCC );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0x00000CC0 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAA808000 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00291AAA );
// TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz
// GPIO Port H stays default, with pulldowns on all except PH0,1 (OSC) just in case that is important.
base = CYGHWR_HAL_STM32_GPIOH;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAAAAAA0 );
// GPIO Port I - setup PI9 for LED3 as GPIO out, rest stay default, with pulldowns
base = CYGHWR_HAL_STM32_GPIOI;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAA2AAAA );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00040000 );
// Set up FSMC NOR/SRAM bank 2 for SRAM
base = CYGHWR_HAL_STM32_FSMC;
#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4)
// NOTEs:
// - The "STM32 20-21-45-46 G-EVAL" boards we have are populated with the
// IS61WV102416BLL-10MLI part and not the Cypress CY7C1071DV33 part.
// - The F4[01][57]xx devices can operate upto 168MHz (or 144MHz) so maximum HCLK
// timing of 6ns (or 6.94444ns).
//
// NOTE: The code does NOT set BWTR2 for SRAM write-cycle timing (so will be
// the default reset value of 0x0FFFFFFF) since BCRx:EXTMOD bit is NOT set.
// TODO:IMPROVE: Derive values based on CLK settings. The following "fixed"
// values are based on a 168MHz SYSCLK:
// BCR2 = MBKEN | MWID=0b01 (16bits) | WREN
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001015 );
// BTR2:
// ADDSET=3 (3 HCLK cycles)
// ADDHLD=0 (SRAM:do not care)
// DATAST=6 (6 HCLK cycles)
// BUSTURN=1 (1 HCLK cycle)
// CLKDIV=0 (SRAM:do not care)
// DATLAT=0 (SRAM:do not care)
// ACCMOD=0 (access mode A)
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x00010603 );
#else // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001011 );
// SRAM timings for the fitted CY7C1071DV33-12BAXI async SRAM
// We could try and make this depend on hclk as it should, but that's
// probably overkill for now. With an hclk of 120MHz, each hclk period
// is 8.33ns, so we just use that. This might mean being slightly
// suboptimal at lower configured hclk speeds.
// It's tricky to get the waveforms in the STM32 FSMC docs and the SRAM
// datasheet, to match up, so there's a small amount of guess work involved
// here. From the SRAM datasheet, ADDSET should be at least 7ns (tHZWE), and
// DATAST should be at least 9ns (tPWE) plus one HCLK (from Fig 397 in FSMC
// docs showing Mode 1 write accesses). This gives ADDSET=1 and
// DATAST=3.
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x00000301 );
#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2
// Enable flash prefetch buffer, cacheability and set latency to 2 wait states.
// Latency has to be set before clock is switched to a higher speed.
{
cyg_uint32 acr;
base = CYGHWR_HAL_STM32_FLASH;
HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN;
acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN;
acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES);
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
}
}
__externC void hal_system_init( void )
{
CYG_ADDRESS base;
#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_ROMINT) | defined(CYG_HAL_STARTUP_SRAM)
// Enable peripheral clocks in RCC
base = CYGHWR_HAL_STM32_RCC;
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHBENR,
BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_FSMC) |
BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_FLITF) |
BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_SRAM) );
HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_APB2ENR,
BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA) |
BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB) |
BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC) |
BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD) |
BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE) |
BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF) |
BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG) );
// Set all unused GPIO lines to input with pull down to prevent
// them floating and annoying any external hardware.
base = CYGHWR_HAL_STM32_GPIOA;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 );
base = CYGHWR_HAL_STM32_GPIOB;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 );
base = CYGHWR_HAL_STM32_GPIOC;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 );
// Set up GPIO lines for external bus
base = CYGHWR_HAL_STM32_GPIOD;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bb44bb );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbbbbbb );
base = CYGHWR_HAL_STM32_GPIOE;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0xbbbbb4bb );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbbbbbb );
base = CYGHWR_HAL_STM32_GPIOF;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bbbbbb );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbb4444 );
base = CYGHWR_HAL_STM32_GPIOG;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bbbbbb );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x44444bb4 );
// Set up FSMC NOR/SRAM bank 2 for NOR Flash
base = CYGHWR_HAL_STM32_FSMC;
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001059 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x10000705 );
// Set up FSMC NOR/SRAM bank 3 for SRAM
/* disabled by reille 2013.04.20
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR3, 0x00001011 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR3, 0x00000200 );
*/
// Added by reille 2013.04.20
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR3, 0x00001011 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR3, 0x00000300 );
// Modified by gyr 2013.04.29
// HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR3, 0x00000301 );
// Added by reille 2013.04.29
// Set up FSMC NOR/SRAM bank 4 for LCD
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR4, 0x00001059 );
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR4, 0x10000502 );
#endif
// Enable flash prefetch buffer and set latency to 2 wait states.
{
cyg_uint32 acr;
base = CYGHWR_HAL_STM32_FLASH;
HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTBE;
acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(2);
HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr );
}
}
