CY_CFG_SECTION
static void ClockSetup(void)
{
/* Enable HALF_EN before trimming for the flash accelerator. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(24u);
/* Disable HALF_EN since it is not required at this IMO frequency. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT12), 0x00000010u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00000000u);
/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000138u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_MATCH), 0x0000FFFEu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000005u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000008u);
while ((CY_GET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL)) & 0x00000008u) != 0u) { }
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000001u);
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Start the WCO */
CySysClkWcoStart();
CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */
(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(48u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
/* Enable fast start mode for XO */
CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
/*Set XTAL(ECO) divider*/
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG), 0x00000000u);
/* Disable Crystal Stable Interrupt before enabling ECO */
CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
/* Start the ECO and do not check status since it is not needed for HFCLK */
(void)CySysClkEcoStart(2000u);
CyDelayUs(1500u); /* Wait to stabalize */
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00BB7F00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x0001A000u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);
/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000041u);
/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);
(void)CyIntSetVector(8u, &CySysWdtIsr);
CyIntEnable(8u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_MATCH), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000005u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000008u);
while ((CY_GET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL)) & 0x00000008u) != 0u) { }
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000001u);
}
/*******************************************************************************
* Function Name: SetAnalogRoutingPumps
********************************************************************************
*
* Summary:
* Enables or disables the analog pumps feeding analog routing switches.
* Intended to be called at startup, based on the Vdda system configuration;
* may be called during operation when the user informs us that the Vdda voltage crossed the pump threshold.
*
* Parameters:
* enabled - 1 to enable the pumps, 0 to disable the pumps
*
* Return:
* void
*
*******************************************************************************/
void SetAnalogRoutingPumps(uint8 enabled)
{
uint32 regValue = CY_GET_XTND_REG32((void *)(CYREG_SAR_PUMP_CTRL));
if (enabled != 0u)
{
regValue |= 0x80000000u;
}
else
{
regValue &= ~0x80000000u;
}
CY_SET_XTND_REG32((void *)(CYREG_SAR_PUMP_CTRL), regValue);
}
/*******************************************************************************
* Function Name: SetAnalogRoutingPumps
********************************************************************************
*
* Summary:
* Enables or disables the analog pumps feeding analog routing switches.
* Intended to be called at startup, based on the Vdda system configuration;
* may be called during operation when the user informs us that the Vdda voltage crossed the pump threshold.
*
* Parameters:
* enabled - 1 to enable the pumps, 0 to disable the pumps
*
* Return:
* void
*
*******************************************************************************/
void SetAnalogRoutingPumps(uint8 enabled)
{
uint32 regValue = CY_GET_XTND_REG32((void *)(CYREG_HSIOM_PUMP_CTL));
if (enabled != 0u)
{
regValue |= 0x80000000u;
}
else
{
regValue &= ~0x80000000u;
}
CY_SET_XTND_REG32((void *)(CYREG_HSIOM_PUMP_CTL), regValue);
regValue = CY_GET_XTND_REG32((void *)(CYREG_CLK_SELECT));
if (enabled != 0u)
{
regValue |= 0x00000020u;
}
else
{
regValue &= ~0x00000020u;
}
CY_SET_XTND_REG32((void *)(CYREG_CLK_SELECT), regValue);
}
/*******************************************************************************
* Function Name: WriteUserSFlashRow
********************************************************************************
* Summary:
* This routine calls the PSoC 4 BLE device supervisory ROM APIs to update
* the user configuration area of Supervisory Flash (SFlash).
*
* Parameters:
* userRowNUmber - User config SFlash row number to which data is to be written
* dataPointer - Pointer to the data to be written. This API writes one row of
* user config SFlash row at a time.
*
* Return:
* uint32 - state of the user config SFlash write operation.
*
*******************************************************************************/
#if defined (__GNUC__)
#pragma GCC optimize ("O0")
#endif /* End of #if defined (__GNUC__) */
uint32 WriteUserSFlashRow(uint8 userRowNUmber, uint32 *dataPointer)
{
#ifdef STORE_SFLASH_NODE_ADDRESS
uint8 localCount;
volatile uint32 retValue=0;
volatile uint32 cmdDataBuffer[(CY_FLASH_SIZEOF_ROW/4) + 2];
volatile uint32 reg1,reg2,reg3,reg4,reg5,reg6;
/* Store the clock settings temporarily */
reg1 = CY_GET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT));
reg2 = CY_GET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG));
reg3 = CY_GET_XTND_REG32((void CYFAR *)(CYREG_PWR_BG_TRIM4));
reg4 = CY_GET_XTND_REG32((void CYFAR *)(CYREG_PWR_BG_TRIM5));
reg5 = CY_GET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_TRIM1));
reg6 = CY_GET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_TRIM2));
/* Initialize the clock necessary for flash programming */
CY_SET_REG32(CYREG_CPUSS_SYSARG, 0x0000e8b6);
CY_SET_REG32(CYREG_CPUSS_SYSREQ, 0x80000015);
/******* Initialize SRAM parameters for the LOAD FLASH command ******/
/* byte 3 (i.e. 00) is the Macro_select */
/* byte 2 (i.e. 00) is the Start addr of page latch */
/* byte 1 (i.e. d7) is the key 2 */
/* byte 0 (i.e. b6) is the key 1 */
cmdDataBuffer[0]=0x0000d7b6;
/****** Initialize SRAM parameters for the LOAD FLASH command ******/
/* byte 3,2 and 1 are null */
/* byte 0 (i.e. 7F) is the number of bytes to be written */
cmdDataBuffer[1]=0x0000007F;
/* Initialize the SRAM buffer with data bytes */
for(localCount = 0; localCount < (CY_FLASH_SIZEOF_ROW/4); localCount++)
{
cmdDataBuffer[localCount + 2] = dataPointer[localCount];
}
/* Write the following to registers to execute a LOAD FLASH bytes */
CY_SET_REG32(CYREG_CPUSS_SYSARG, &cmdDataBuffer[0]);
CY_SET_REG32(CYREG_CPUSS_SYSREQ, LOAD_FLASH);
/****** Initialize SRAM parameters for the WRITE ROW command ******/
/* byte 3 & 2 are null */
/* byte 1 (i.e. 0xeb) is the key 2 */
/* byte 0 (i.e. 0xb6) is the key 1 */
cmdDataBuffer[0] = 0x0000ebb6;
/* byte 7,6 and 5 are null */
/* byte 4 is desired SFlash user row
* Allowed values 0 - row 4
1 - row 5
2 - row 6
3 - row 7 */
cmdDataBuffer[1] = (uint32) userRowNUmber;
/* Write the following to registers to execute a WRITE USER SFlash ROW command */
CY_SET_REG32(CYREG_CPUSS_SYSARG, &cmdDataBuffer[0]);
CY_SET_REG32(CYREG_CPUSS_SYSREQ, WRITE_USER_SFLASH_ROW);
/* Read back SYSARG for the result. 0xA0000000 = SUCCESS; */
retValue = CY_GET_REG32(CYREG_CPUSS_SYSARG);
/* Restore the clock settings after the flash programming is done */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT),reg1);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG),reg2);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PWR_BG_TRIM4),reg3);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PWR_BG_TRIM5),reg4);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_TRIM1),reg5);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_TRIM2),reg6);
return retValue;
#else
return (0);
#endif
}
