static void WriteInitialRegisterValues ( void )
{
TX_DEBUG_PRINT(("WriteInitialRegisterValues\n"));
SiiRegWrite(REG_POWER_EN, 0x3F);
SiiRegWrite(REG_MHLTX_CTL6, 0xBC);
SiiRegWrite(REG_MHLTX_CTL2, 0x3C);
SiiRegWrite(REG_MHLTX_CTL4, 0xC8);
SiiRegWrite(REG_MHLTX_CTL7, 0x03);
SiiRegWrite(REG_MHLTX_CTL8, 0x0A);
SiiRegWrite(REG_TMDS_CCTRL, 0x08);
SiiRegWrite(REG_USB_CHARGE_PUMP_MHL, 0x03);
SiiRegWrite(REG_USB_CHARGE_PUMP, 0x8C);
SiiRegWrite(REG_SYS_CTRL1, 0x35);
SiiRegWrite(REG_DISC_CTRL5, 0x57);
SiiRegWrite(REG_DISC_CTRL9, 0x24);
SiiRegWrite(REG_DISC_CTRL1, 0x27);
SiiRegWrite(REG_DISC_CTRL3, 0x86);
CbusReset();
InitCBusRegs();
SiiRegModify(REG_LM_DDC, VID_MUTE, SET_BITS);
SiiRegModify(REG_AUDP_TXCTRL, BIT2, SET_BITS);
}
///////////////////////////////////////////////////////////////////////////
// WriteInitialRegisterValues
//
//
///////////////////////////////////////////////////////////////////////////
static void WriteInitialRegisterValues (void)
{
//TX_DEBUG_PRINT(("Drv: WriteInitialRegisterValues\n"));
// Power Up
SiiRegWrite(REG_DPD, 0x3F); // Power up CVCC 1.2V core
SiiRegWrite(REG_TMDS_CLK_EN, 0x01); // Enable TxPLL Clock
SiiRegWrite(REG_TMDS_CH_EN, 0x11); // Enable Tx Clock Path & Equalizer
SiiRegWrite(REG_MHLTX_CTL1, 0x10); // TX Source termination ON
SiiRegWrite(REG_MHLTX_CTL6, 0xBC); // Enable 1X MHL clock output
SiiRegWrite(REG_MHLTX_CTL2, 0x3C); // TX Differential Driver Config
SiiRegWrite(REG_MHLTX_CTL4, 0xC8);
SiiRegWrite(REG_MHLTX_CTL7, 0x03); // 2011-10-10
SiiRegWrite(REG_MHLTX_CTL8, 0x0A); // PLL bias current, PLL BW Control
// Analog PLL Control
SiiRegWrite(REG_TMDS_CCTRL, 0x08); // Enable Rx PLL clock 2011-10-10 - select BGR circuit for voltage references
SiiRegWrite(REG_USB_CHARGE_PUMP, 0x8C); // 2011-10-10 USB charge pump clock
SiiRegWrite(REG_TMDS_CTRL4, 0x02);
SiiRegWrite(REG_TMDS0_CCTRL2, 0x00);
SiiRegModify(REG_DVI_CTRL3, BIT5, 0); // 2011-10-10
SiiRegWrite(REG_TMDS_TERMCTRL1, 0x60);
SiiRegWrite(REG_PLL_CALREFSEL, 0x03); // PLL Calrefsel
SiiRegWrite(REG_PLL_VCOCAL, 0x20); // VCO Cal
SiiRegWrite(REG_EQ_DATA0, 0xE0); // Auto EQ
SiiRegWrite(REG_EQ_DATA1, 0xC0); // Auto EQ
SiiRegWrite(REG_EQ_DATA2, 0xA0); // Auto EQ
SiiRegWrite(REG_EQ_DATA3, 0x80); // Auto EQ
SiiRegWrite(REG_EQ_DATA4, 0x60); // Auto EQ
SiiRegWrite(REG_EQ_DATA5, 0x40); // Auto EQ
SiiRegWrite(REG_EQ_DATA6, 0x20); // Auto EQ
SiiRegWrite(REG_EQ_DATA7, 0x00); // Auto EQ
SiiRegWrite(REG_BW_I2C, 0x0A); // Rx PLL BW ~ 4MHz
SiiRegWrite(REG_EQ_PLL_CTRL1, 0x06); // Rx PLL BW value from I2C
SiiRegWrite(REG_MON_USE_COMP_EN, 0x06);
// synchronous s/w reset
SiiRegWrite(REG_ZONE_CTRL_SW_RST, 0x60); // Manual zone control
SiiRegWrite(REG_ZONE_CTRL_SW_RST, 0xE0); // Manual zone control
SiiRegWrite(REG_MODE_CONTROL, 0x00); // PLL Mode Value
SiiRegWrite(REG_SYS_CTRL1, 0x35); // bring out from power down (script moved this here from above)
SiiRegWrite(REG_DISC_CTRL2, 0xAD);
SiiRegWrite(REG_DISC_CTRL5, 0x57); // 1.8V CBUS VTH 5K pullup for MHL state
SiiRegWrite(REG_DISC_CTRL6, 0x11); // RGND & single discovery attempt (RGND blocking)
SiiRegWrite(REG_DISC_CTRL8, 0x82); // Ignore VBUS
SiiRegWrite(REG_DISC_CTRL9, 0x24); // No OTG, Discovery pulse proceed, Wake pulse not bypassed
SiiRegWrite(REG_DISC_CTRL4, 0x8C); // Pull-up resistance off for IDLE state.
SiiRegWrite(REG_DISC_CTRL1, 0x27); // Enable CBUS discovery
SiiRegWrite(REG_DISC_CTRL7, 0x20); // use 1K only setting
SiiRegWrite(REG_DISC_CTRL3, 0x86); // MHL CBUS discovery
CLR_BIT(REG_INT_CTRL, 6);//change hpd out pin from defult open-drain to push-pull by garyyuan
if (fwPowerState != TX_POWER_STATE_D3) { // Don't force HPD to 0 during wake-up from D3
SiiRegModify(REG_INT_CTRL, BIT5 | BIT4, BIT4); // Force HPD to 0 when not in MHL mode.
}
SiiRegWrite(REG_SRST, 0x84); // Enable Auto soft reset on SCDT = 0
SiiRegWrite(REG_DCTL, 0x1C); // HDMI Transcode mode enable
CbusReset();
InitCBusRegs();
}
