/**
* @brief main routine for timer example
* @return Function should not exit.
*/
int main(void)
{
uint32_t timerBaseClock;
SystemCoreClockUpdate();
Board_Init();
Board_LED_Set(0, false);
Board_LED_Set(1, false);
/* Initialize Timer 0 and Timer 1 */
Chip_TIMER_Init(LPC_TIMER0);
Chip_TIMER_Init(LPC_TIMER1);
/* Setup prescale value on Timer 0 to PCLK */
Chip_TIMER_PrescaleSet(LPC_TIMER0, 0);
/* Setup prescale value on Timer 1 for lower resolution */
Chip_TIMER_PrescaleSet(LPC_TIMER1, PRESCALE_HZ2);
/* Reset timers */
Chip_TIMER_Reset(LPC_TIMER0);
Chip_TIMER_Reset(LPC_TIMER1);
/* Enable both timers to generate interrupts when time matches */
Chip_TIMER_MatchEnableInt(LPC_TIMER0, 1);
Chip_TIMER_MatchEnableInt(LPC_TIMER1, 1);
/* Get rate of timer base clock */
timerBaseClock = Chip_Clock_GetAsyncSyscon_ClockRate();
/* Setup Timer 0 for a match every 1s */
Chip_TIMER_SetMatch(LPC_TIMER0, 1, (timerBaseClock / TICKRATE_HZ1));
/* Setup Timer 1 for a match twice in a second */
Chip_TIMER_SetMatch(LPC_TIMER1, 1, (timerBaseClock / ((PRESCALE_HZ2 + 1) * TICKRATE_HZ2)) );
/* Setup both timers to restart when match occurs */
Chip_TIMER_ResetOnMatchEnable(LPC_TIMER0, 1);
Chip_TIMER_ResetOnMatchEnable(LPC_TIMER1, 1);
/* Start both timers */
Chip_TIMER_Enable(LPC_TIMER0);
Chip_TIMER_Enable(LPC_TIMER1);
/* Clear both timers of any pending interrupts */
NVIC_ClearPendingIRQ(CT32B0_IRQn);
NVIC_ClearPendingIRQ(CT32B1_IRQn);
/* Enable both timer interrupts */
NVIC_EnableIRQ(CT32B0_IRQn);
NVIC_EnableIRQ(CT32B1_IRQn);
/* Wait for timers to generate interrupts (LEDs toggle in interrupt handlers) */
while (1) {
__WFI();
}
return 0;
}
/* Initialize stopwatch */
void StopWatch_Init(void)
{
/* Set prescaler to divide by 8 */
const uint32_t prescaleDivisor = 8;
Chip_TIMER_Init(LPC_TIMER32_1);
Chip_TIMER_PrescaleSet(LPC_TIMER32_1, prescaleDivisor - 1);
Chip_TIMER_Enable(LPC_TIMER32_1);
/* Pre-compute tick rate. */
ticksPerSecond = Chip_Clock_GetAsyncSyscon_ClockRate() / prescaleDivisor;
ticksPerMs = ticksPerSecond / 1000;
ticksPerUs = ticksPerSecond / 1000000;
}
static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct lpc_uart *uart;
UART_BAUD_T baud;
UART_CFG_T UART_cfg;
RT_ASSERT(serial != RT_NULL);
uart = (struct lpc_uart *)serial->parent.user_data;
/* Initialize UART Configuration parameter structure to default state:
* Baudrate = 115200 b
* 8 data bit
* 1 Stop bit
* None parity
*/
/* Set up baudrate parameters */
baud.clk = Chip_Clock_GetAsyncSyscon_ClockRate(); /* Clock frequency */
baud.baud = cfg->baud_rate; /* Required baud rate */
baud.ovr = 0; /* Set the oversampling to the recommended rate */
baud.mul = baud.div = 0;
if(!baud.mul)
{
_UART_CalcMul(&baud);
}
_UART_CalcDiv(&baud);
/* Set fractional control register */
LPC_ASYNC_SYSCON->FRGCTRL = ((uint32_t) baud.mul << 8) | 0xFF;
/* Configure the UART */
UART_cfg.cfg = UART_CFG_8BIT;
UART_cfg.div = baud.div; /* Use the calculated div value */
UART_cfg.ovr = baud.ovr; /* Use oversampling rate from baud */
UART_cfg.res = UART_BIT_DLY(cfg->baud_rate);
/* P254,255,246 */
uart->UART->OSR = (UART_cfg.ovr - 1) & 0x0F;
uart->UART->BRG = (UART_cfg.div - 1) & 0xFFFF;
uart->UART->CFG = UART_CFG_ENABLE | (UART_cfg.cfg & ~UART_CFG_RES);
return RT_EOK;
}
/* Get UART base rate */
uint32_t Chip_Clock_GetFRGClockRate(void)
{
uint64_t inclk;
/* Get clock rate into FRG */
inclk = (uint64_t) Chip_Clock_GetAsyncSyscon_ClockRate();
if (inclk != 0) {
uint32_t mult, divmult;
divmult = LPC_SYSCON->FRGCTRL;
if ((divmult & 0xFF) == 0xFF) {
/* Fractional part is enabled, get multiplier */
mult = (divmult >> 8) & 0xFF;
/* Get fractional error */
inclk = (inclk * 256) / (uint64_t) (256 + mult);
}
/* Setup a timer for a periodic (repeat mode) rate */
static void setupMRT(uint8_t ch, MRT_MODE_T mode, uint32_t rate)
{
LPC_MRT_CH_T *pMRT;
/* Get pointer to timer selected by ch */
pMRT = Chip_MRT_GetRegPtr(ch);
/* Setup timer with rate based on MRT clock */
Chip_MRT_SetInterval(pMRT, (Chip_Clock_GetAsyncSyscon_ClockRate() / rate) |
MRT_INTVAL_LOAD);
/* Timer mode */
Chip_MRT_SetMode(pMRT, mode);
/* Clear pending interrupt and enable timer */
Chip_MRT_IntClear(pMRT);
Chip_MRT_SetEnabled(pMRT);
}
/* Configure UART ROM Driver and pripheral */
static int uartrom_config(void)
{
UART_CFG_T cfg;
UART_BAUD_T baud;
/* Set up baudrate parameters */
baud.clk = Chip_Clock_GetAsyncSyscon_ClockRate(); /* Clock frequency */
baud.baud = UART_BAUD_RATE; /* Required baud rate */
baud.ovr = 0; /* Set the oversampling to the recommended rate */
baud.mul = baud.div = 0;
if (ROM_UART_CalBaud(&baud) != LPC_OK) {
/* Unable to calculate the baud rate parameters */
while (1) {}
}
/* Set fractional control register */
Chip_SYSCON_SetUSARTFRGCtrl(baud.mul, 255);
/* See if the calculated baud is < +/- UART_BUAD_ERR% of the required baud */
if (ABS(baud.baud - UART_BAUD_RATE) > (UART_BAUD_RATE * UART_BUAD_ERR) / 100) {
/* WARNING: Baud rate is has more than UART_BUAD_ERR percentage */
/* Try to auto-detect the Oversampling rate by setting baud.ovr to 0 */
while (1) {}
}
/* Configure the UART */
cfg.cfg = UART_CFG_8BIT | UART_CFG_BRKRX;
cfg.div = baud.div; /* Use the calculated div value */
cfg.ovr = baud.ovr; /* Use oversampling rate from baud */
cfg.res = UART_BIT_DLY(UART_BAUD_RATE);
/* Configure the UART */
ROM_UART_Configure(hUART, &cfg);
NVIC_ClearPendingIRQ(UART0_IRQn);
NVIC_EnableIRQ(UART0_IRQn);
return 0;
}
/****************************************************************************************************
* @fn i2cs_setup_slave
* Helper routine to set up slave
*
***************************************************************************************************/
static void i2cs_setup_slave(i2cs_slave_t *pSlaveSetup)
{
uint32_t optimalDev;
/* Limit usable slave address indexes to the maximum the controller can support */
if (pSlaveSetup->SlaveIndex <= I2C_SLV_ADDR_NUM) {
Chip_I2CS_SetSlaveAddr(I2C_HOSTIF, pSlaveSetup->SlaveIndex, (pSlaveSetup->slaveAddr & I2C_SLV_ADDR_MSK));
/* Clear interrupt status */
Chip_I2CS_ClearStatus(I2C_HOSTIF, I2C_STAT_SLVDESEL);
if (pSlaveSetup->EnableSlave == 0) {
Chip_I2CS_DisableSlaveAddr(I2C_HOSTIF, pSlaveSetup->SlaveIndex);
}
else {
Chip_I2C_EnableInt(I2C_HOSTIF, I2C_INTENSET_SLVPENDING | I2C_INTENSET_SLVDESEL);
}
}
optimalDev = Chip_Clock_GetAsyncSyscon_ClockRate()/I2C_SLV_PCLK_FREQ;
Chip_I2C_SetClockDiv( I2C_HOSTIF, optimalDev );
/* Enable I2C slave interface */
Chip_I2CS_Enable(I2C_HOSTIF);
}
/**
* @brief Main routine for I2C example
* @return Function should not exit
*/
int main(void)
{
uint32_t memSize, *devMem, optimalDev;
ROM_I2CS_INIT_T i2csInit;
ROM_I2CS_SLAVE_T slaveSetup;
int i;
/* Generic Initialization */
SystemCoreClockUpdate();
Board_Init();
/* Setup I2C pin muxing, enable I2C clock and reset I2C peripheral */
Init_I2C_PinMux();
Chip_Clock_EnablePeriphClock(LPC_I2CS_CLOCK);
Chip_SYSCON_PeriphReset(LPC_I2CS_RESET);
/* Get needed size for driver context memory */
memSize = ROM_I2CS_GetMemSize();
if (memSize > sizeof(drvData)) {
errorOut("Can't allocate memory for I2C driver context\r\n");
}
devMem = drvData; /* Or just use malloc(memSize) */
/* Initialize driver */
i2csInit.pUserData = (void *) &xferDone;
i2csInit.base = (uint32_t) LPC_I2C_PORT;
i2csHandle = ROM_I2CS_Init(devMem, &i2csInit);
if (i2csHandle == NULL) {
/* Error initializing I2C */
errorOut("Error initializing ROM\r\n");
}
/* Register slave start and completion callbacks */
ROM_I2CS_RegisterCallback(i2csHandle, ROM_I2CS_DONE_CB, (void *) i2cSlaveCompleteFunc);
ROM_I2CS_RegisterCallback(i2csHandle, ROM_I2CS_START_CB, (void *) i2cSlaveStartFunc);
/* Setup slave address to respond to */
slaveSetup.slaveAddr = I2C_ADDR_7BIT;
slaveSetup.SlaveIndex = 0;
slaveSetup.EnableSlave = 1;
ROM_I2CS_SetupSlave(i2csHandle, &slaveSetup);
/* Setup clock rate for I2C - this must be done for master or slave modes.
This function is not set by the ROM API code. */
optimalDev = Chip_Clock_GetAsyncSyscon_ClockRate() / 4000000; /* 250nS */
LPC_I2C_PORT->CLKDIV = optimalDev;
/* Enable the interrupt for the I2C */
NVIC_EnableIRQ(LPC_I2CS_INT);
while (1) {
/* Populate some TX data and clear RX data */
for (i = 0; i < sizeof(slaveTx); i++) {
slaveTx[i] = 0x70 + i;
slaveRx[i] = 0;
}
sXfer.txBuff = slaveTx;
sXfer.rxBuff = slaveRx;
sXfer.txSz = sizeof(slaveTx);
sXfer.rxSz = sizeof(slaveRx);
/* Wait for a transfer from the master */
xferDone = false;
ROM_I2CS_Transfer(i2csHandle, &sXfer); /* Never blocks, always returns LPC_OK */
DEBUGOUT("Waiting for master\r\n");
/* Wait for transfer to complete. The slave data completion callback
will set xferDone when ready via it's completion callback. */
while (xferDone == false) {
__WFI();
}
/* Check status of the transfer */
DEBUGOUT("Transfer complete (%x)\r\n", sXfer.status);
DEBUGOUT("RX [%d]", sXfer.bytesRecv);
for (i = 0; i < sXfer.bytesRecv; i++) {
DEBUGOUT(" : %02x", slaveRx[i]);
}
DEBUGOUT("\r\n");
DEBUGOUT("TX [%d]", sXfer.bytesSent);
for (i = 0; i < sXfer.bytesSent; i++) {
DEBUGOUT(" : %02x", slaveTx[i]);
}
DEBUGOUT("\r\n");
}
/* Code never reaches here. Only used to satisfy standard main() */
return 0;
}
// Magicoe OSStatus platform_spi_init( const platform_spi_t* spi, const platform_spi_config_t* config )
OSStatus platform_spi_init( platform_spi_driver_t* driver, const platform_spi_t* peripheral, const platform_spi_config_t* config )
{
// SPI_InitTypeDef spi_init;
OSStatus err = kNoErr;
platform_mcu_powersave_disable();
uint32_t t1; //general var
require_action_quiet( ( peripheral != NULL ) && ( config != NULL ), exit, err = kParamErr);
require_action_quiet( ( peripheral->port == LPC_SPI0 ), exit, err = kParamErr);
driver->isRxDone = driver->isTxDone = 0;
#ifndef NO_MICO_RTOS
if (driver->sem_xfer_done == 0)
mico_rtos_init_semaphore(&driver->sem_xfer_done, 1);
#endif
// >>> Init Pin mux
t1 = IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF;
if (peripheral->port == LPC_SPI0)
{
if (config->speed >= 24000000)
t1 |= 1UL<<9; // enable fast slew
g_pIO->PIO[0][11] = IOCON_FUNC1 | t1;/* SPI0_SCK */
g_pIO->PIO[0][12] = IOCON_FUNC1 | t1; /* SPI0_MOSI */
g_pIO->PIO[0][13] = IOCON_FUNC1 | t1; /* SPI0_MISO */
// config CS pin as GPIO
g_pIO->PIO[config->chip_select->port][config->chip_select->pin_number] = IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF;
platform_gpio_output_high(config->chip_select);
platform_gpio_init(config->chip_select, OUTPUT_PUSH_PULL);
}
// <<<
// >>>
// initialize SPI peripheral
{
uint32_t bv;
LPC_SPI_T *pSPI = peripheral->port;
// >>>
bv = pSPI == LPC_SPI0 ? 1UL << 9 : 1UL<<10;
g_pASys->ASYNCAPBCLKCTRLSET = bv; // enable clock to SPI
g_pASys->ASYNCPRESETCTRLSET = bv;
g_pASys->ASYNCPRESETCTRLCLR = bv;
// <<<
// predly | postDly| fraDly | xferDly
pSPI->DLY = 1UL<<0 | 1UL<<4 | 1UL<<8 | 1UL<<12;
pSPI->DLY = 0;
t1 = Chip_Clock_GetAsyncSyscon_ClockRate();
t1 = (t1 + config->speed - 1) / config->speed;
pSPI->DIV = t1 - 1; // proper division
pSPI->TXCTRL = (config->bits - 1) << 24; // 8 bits per frame
// Enable | master | no loopback
t1 = 1UL<<0 | 1UL<<2 | 0UL<<7;
// determine SPI mode
if (config->mode & SPI_CLOCK_IDLE_HIGH) {
t1 |= 1UL<<5; // CPOL = 1
if (t1 & SPI_CLOCK_RISING_EDGE)
t1 |= 1UL<<4; // CPHA = 1
} else {
if (!(t1 & SPI_CLOCK_RISING_EDGE))
t1 |= 1UL<<4;
}
pSPI->CFG = t1;
}
// <<<
g_pDMA->DMACOMMON[0].ENABLESET = (1UL<<peripheral->dmaRxChnNdx) | (1UL<<peripheral->dmaTxChnNdx);
g_pDMA->DMACOMMON[0].INTENSET = (1UL<<peripheral->dmaRxChnNdx) | (1UL<<peripheral->dmaTxChnNdx);
g_pDMA->DMACH[peripheral->dmaRxChnNdx].CFG = DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_SNGL | DMA_CFG_CHPRIORITY(1);
g_pDMA->DMACH[peripheral->dmaTxChnNdx].CFG = DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_SNGL | DMA_CFG_CHPRIORITY(1);
exit:
platform_mcu_powersave_enable();
return err;
}
