/* Basic Ethernet interface initialization */
void Chip_ENET_Init(LPC_ENET_T *pENET)
{
LPC_CREG->CREG6 &= ~0x7;
/* Enable ethernet clock */
Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1);
/* PHY TX/RX base clock routing is setup as part of SystemInit() */
#if defined(USE_RMII)
LPC_CREG->CREG6 |= 0x4;
#endif
/* Reset ethernet and wait for reset to complete */
Chip_RGU_TriggerReset(RGU_ETHERNET_RST);
while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {}
/* Reset ethernet peripheral */
Chip_ENET_Reset(pENET);
/* Setup MII link divider to /102 and PHY address 1 */
Chip_ENET_SetupMII(pENET, 4, 1);
IP_ENET_Init(pENET);
}
/* Basic Ethernet interface initialization */
void Chip_ENET_Init(LPC_ENET_T *pENET)
{
Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1);
reset(pENET);
/* Setup MII link divider to /102 and PHY address 1 */
Chip_ENET_SetupMII(pENET, 4, 1);
/* Enhanced descriptors, burst length = 1 */
pENET->DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1);
/* Initial MAC configuration for checksum offload, full duplex,
100Mbps, disable receive own in half duplex, inter-frame gap
of 64-bits */
pENET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM |
MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3);
/* Setup default filter */
pENET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA;
/* Flush transmit FIFO */
pENET->DMA_OP_MODE = DMA_OM_FTF;
/* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at
64 bytes */
pENET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0);
/* Clear all MAC interrupts */
pENET->DMA_STAT = DMA_ST_ALL;
/* Enable MAC interrupts */
pENET->DMA_INT_EN = 0;
}
/* Low level init of the MAC and PHY */
STATIC err_t low_level_init(struct netif *netif)
{
lpc_enetdata_t *lpc_enetif = netif->state;
err_t err = ERR_OK;
#if defined(USE_RMII)
Chip_ENET_Init(LPC_ETHERNET, true);
#else
Chip_ENET_Init(LPC_ETHERNET, false);
#endif
/* Initialize the PHY */
Chip_ENET_SetupMII(LPC_ETHERNET, Chip_ENET_FindMIIDiv(LPC_ETHERNET, 2500000), LPC_PHYDEF_PHYADDR);
#if defined(USE_RMII)
if (lpc_phy_init(true, msDelay) != SUCCESS) {
return ERROR;
}
#else
if (lpc_phy_init(false, msDelay) != SUCCESS) {
return ERROR;
}
#endif
/* Save station address */
Chip_ENET_SetADDR(LPC_ETHERNET, netif->hwaddr);
/* Setup transmit and receive descriptors */
if (lpc_tx_setup(lpc_enetif) != ERR_OK) {
return ERR_BUF;
}
if (lpc_rx_setup(lpc_enetif) != ERR_OK) {
return ERR_BUF;
}
/* Enable packet reception */
#if IP_SOF_BROADCAST_RECV
Chip_ENET_EnableRXFilter(LPC_ETHERNET, ENET_RXFILTERCTRL_APE | ENET_RXFILTERCTRL_ABE);
#else
Chip_ENET_EnableRXFilter(ENET_RXFILTERCTRL_APE);
#endif
/* Clear and enable rx/tx interrupts */
Chip_ENET_EnableInt(LPC_ETHERNET, RXINTGROUP | TXINTGROUP);
/* Enable RX and TX */
Chip_ENET_TXEnable(LPC_ETHERNET);
Chip_ENET_RXEnable(LPC_ETHERNET);
return err;
}
