/**
* @brief main routine for blinky example
* @return Function should not exit.
*/
int main(void)
{
SystemCoreClockUpdate();
Board_Init();
Board_LED_Set(0, false);
#if 0
/* Enable SysTick Timer */
SysTick_Config(SystemCoreClock / TICKRATE_HZ);
/* Bail out after timeout */
while (sysTick <= TIMEOUT_TICKS) {
__WFI();
}
#else
/* Enable SysTick Timer */
SysTick_Config(SystemCoreClock / TICKRATE_HZ);
/* Custom Initialization */
Chip_SCT_Init(LPC_SCT);
/* Configure the SCT as a 32bit counter using the bus clock */
Chip_SCT_Config(LPC_SCT, (0xf << 9) | SCT_CONFIG_32BIT_COUNTER | SCT_CONFIG_CLKMODE_BUSCLK);
/* The match/capture REGMODE defaults to match mode */
/* Set the match count for match register 0 */
Chip_SCT_SetMatchCount(LPC_SCT, SCT_MATCH_0, SystemCoreClock / TICKRATE_HZ);
/* Set the match reload value */
Chip_SCT_SetMatchReload(LPC_SCT, SCT_MATCH_0, SystemCoreClock / TICKRATE_HZ);
LPC_SCT->EVENT[0].CTRL = 0x5000;
LPC_SCT->EVENT[0].STATE = 0x1;
LPC_SCT->LIMIT = 0x1;
/* Enable an Interrupt on the Match Event */
Chip_SCT_EnableEventInt(LPC_SCT, SCT_EVT_0);
/* Enable the IRQ for the SCT */
NVIC_EnableIRQ(SCT_IRQn);
LPC_SCT->CTRL_U &= ~(1 << 2); /* unhalt the SCT by clearing bit 2 of the unified CTRL register */
while (1) {
__WFI();
}
#endif
return 0;
}
/**
* @brief Main entry point
* @return Nothing
*/
int main(void)
{
uint32_t SCT_FRQ;
Board_Init();
/* Initialize SCT */
Chip_SCT_Init(LPC_SCT);
LPC_SCU->SFSCLK[3] = SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC1; /* function 1; CGU clk out, pull up */
/* Attach IRC clock to divider B with a divider of 16 */
Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IRC, 16);
/* Route divider B output to Clock output base clock and enable base out clock */
Chip_Clock_SetBaseClock(CLK_BASE_OUT, CLKIN_IDIVB, true, false);
/* Configure SCT pins */
SCT_PinsConfigure();
SCT_FRQ = Chip_Clock_GetRate(CLK_MX_SCT);
DEBUGOUT("SCT_FRQ: %d\r\n", SCT_FRQ);
Chip_SCT_ControlSetClr(LPC_SCT, SCT_CTRL_CLRCTR_L | SCT_CTRL_HALT_L | SCT_CTRL_PRE_L(256 - 1)
| SCT_CTRL_HALT_H | SCT_CTRL_CLRCTR_H | SCT_CTRL_PRE_H(256 - 1),
ENABLE);
/* Now use the FSM code to configure the state machine */
sct_fsm_init();
/* initialize random seed: */
srand(0x5EED);
/* 12000000 / 256 / 16 = 2929 Hz
* 65535 / 2929 =~ 22 */
/* generate a random delay from 1 to 22 seconds */
delay = (rand() % 22 + 1) * 2929;
NVIC_ClearPendingIRQ(SCT_IRQn);
NVIC_EnableIRQ(SCT_IRQn);
/* Start the SCT */
Chip_SCT_ControlSetClr(LPC_SCT, SCT_CTRL_STOP_L | SCT_CTRL_HALT_L | SCT_CTRL_STOP_H | SCT_CTRL_HALT_H, DISABLE);
while (1) {
__WFI();
}
}
int execute_SCT_match_test( LPC_SCT_T *pSCT, CounterWidth counter_width, CHIP_SCT_MATCH_REG_T match_register,
uint32_t match_count, SCTClock sct_clock, SCTInputEdge sct_input_edge) {
uint32_t cfg = 0, evt_ctrl = 0;
int i;
/* Custom Initialization */
Chip_SCT_Init(pSCT);
switch (counter_width) {
case kCounterWidth16Bits:
cfg |= SCT_CONFIG_16BIT_COUNTER;
break;
case kCounterWidth32Bits:
cfg |= SCT_CONFIG_32BIT_COUNTER;
break;
}
switch (sct_clock) {
case kSystemClock:
cfg |= SCT_CONFIG_CLKMODE_SYSCLK;
break;
case kPrescaledSystemClock:
cfg |= SCT_CONFIG_CLKMODE_PRESCALED_SYSCLK;
break;
case kSCTInput:
cfg |= SCT_CONFIG_CLKMODE_SCT_INPUT;
break;
case kPrescaledSCTInput:
cfg |= SCT_CONFIG_CLKMODE_PRESCALED_SCT_INPUT;
break;
}
if ((sct_clock == kSCTInput) || (sct_clock == kPrescaledSCTInput)) {
switch (sct_input_edge) {
case kRisingInput0:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_0;
break;
case kFallingInput0:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_0;
break;
case kRisingInput1:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_1;
break;
case kFallingInput1:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_1;
break;
case kRisingInput2:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_2;
break;
case kFallingInput2:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_2;
break;
case kRisingInput3:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_3;
break;
case kFallingInput3:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_3;
break;
case kRisingInput4:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_4;
break;
case kFallingInput4:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_4;
break;
case kRisingInput5:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_5;
break;
case kFallingInput5:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_5;
break;
case kRisingInput6:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_6;
break;
case kFallingInput6:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_6;
break;
case kRisingInput7:
cfg |= SCT_CONFIG_CKSEL_RISING_IN_7;
break;
case kFallingInput7:
cfg |= SCT_CONFIG_CKSEL_FALLING_IN_7;
break;
}
}
Chip_SCT_Config(pSCT, cfg);
/* The match/capture REGMODE defaults to match mode */
/* Set the match count */
Chip_SCT_SetMatchCount(pSCT, match_register, match_count);
/* Set the match reload value */
Chip_SCT_SetMatchReload(pSCT, match_register, match_count);
/* Setup so that a match in the match_register when in State 0 causes Event 0.
* Setup so Event 0 causes a Limit condition
*/
evt_ctrl |= SCT_EV_CTRL_MATCHSEL(match_register) | SCT_EV_CTRL_HEVENT_L |
SCT_EV_CTRL_COMBMODE_MATCH;
Chip_SCT_EventControl(pSCT, 0, evt_ctrl);
Chip_SCT_EventStateMask(pSCT, 0, (1UL << 0));
Chip_SCT_Limit(pSCT, (1UL << 0));
/* Setup to toggle all outputs on match */
for (i = 0; i < CONFIG_SCT_nOU; i++) {
LPC_SCT->OUT[i].SET = (1UL << 0);
LPC_SCT->OUT[i].CLR = (1UL << 0);
Chip_SCT_SetConflictResolution(LPC_SCT, i, 0x3);
}
/* Enable an Interrupt on the Match Event */
Chip_SCT_EnableEventInt(pSCT, SCT_EVT_0);
/* Enable the IRQ for the SCT */
NVIC_EnableIRQ(SCT_IRQn);
/* Start the counter */
if (counter_width == kCounterWidth32Bits) {
Chip_SCT_ClearControl(pSCT, SCT_CTRL_HALT_L);
}
else {
// TODO deal with 16 bit counter mode
}
return 0;
}
int32_t main(void) {
int32_t i,cnt=0;
uint8_t RC5_System_prev=0;
uint8_t RC5_Command_prev=0;
CHIP_PMU_MCUPOWER_T mcupower=PMU_MCU_SLEEP;
SystemCoreClockUpdate();
// init GPIO
Chip_GPIO_Init(LPC_GPIO_PORT);
Chip_SYSCTL_PeriphReset(RESET_GPIO);
// init SPI0 at SystemCoreClock speed
Chip_SPI_Init(LPC_SPI0);
Chip_SPI_ConfigureSPI(LPC_SPI0,SPI_MODE_MASTER|
SPI_CLOCK_CPHA0_CPOL0|
SPI_DATA_MSB_FIRST|
SPI_SSEL_ACTIVE_LO);
LPC_SPI0->DIV=0;
Chip_SPI_Enable(LPC_SPI0);
// init MRT
Chip_MRT_Init();
// init SWM
Chip_SWM_Init();
Chip_SWM_DisableFixedPin(SWM_FIXED_SWCLK);//PIO0_3
Chip_SWM_DisableFixedPin(SWM_FIXED_SWDIO);//PIO0_2
Chip_SWM_DisableFixedPin(SWM_FIXED_ACMP_I2);//PIO0_1
Chip_SWM_DisableFixedPin(SWM_FIXED_ACMP_I1);//PIO0_0
Chip_SWM_MovablePinAssign(SWM_SPI0_SCK_IO,CLK_PIN);
Chip_SWM_MovablePinAssign(SWM_SPI0_MOSI_IO,MOSI_PIN);
Chip_SWM_MovablePinAssign(SWM_CTIN_0_I,IR_PIN);
Chip_SWM_Deinit();
// init onboard LED
Chip_GPIO_SetPinState(LPC_GPIO_PORT,0,LED_PIN,true);
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT,0,LED_PIN);
// init LCD reset pin
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT,0,RESET_PIN);
// init LCD
LCDInit();
LCDClearScreenBlack();
// init SCT
Chip_SCT_Init(LPC_SCT);
// set prescaler, SCT clock = 1 MHz, clear counter
LPC_SCT->CTRL_L |= SCT_CTRL_PRE_L(SystemCoreClock/1000000-1) | SCT_CTRL_CLRCTR_L;
sct_fsm_init();
NVIC_EnableIRQ(SCT_IRQn);
// init PIO0_3 pin interrupt for wakeup from sleep mode
Chip_SYSCTL_SetPinInterrupt(IR_IRQ,IR_PIN);
Chip_PININT_EnableIntLow(LPC_PININT, PININTCH(IR_IRQ));
NVIC_EnableIRQ(PININT3_IRQn);
Chip_SYSCTL_EnablePINTWakeup(IR_IRQ);
// set sleep options
Chip_SYSCTL_SetDeepSleepPD(SYSCTL_DEEPSLP_BOD_PD | SYSCTL_DEEPSLP_WDTOSC_PD);
Chip_SYSCTL_SetWakeup(~(SYSCTL_SLPWAKE_IRCOUT_PD | SYSCTL_SLPWAKE_IRC_PD | SYSCTL_SLPWAKE_FLASH_PD ));
LCDPutStr("kbiva.wordpress.com", MAX_X / 2 + 50, 10, WHITE, BLACK);
LCDPutStr("RC5 Decoder", MAX_X / 2 + 35, 35, WHITE, BLACK);
LCDPutStr("Frame:", MAX_X / 2 + 20, 1, WHITE, BLACK);
LCDPutStr("System:", MAX_X / 2 + 5 , 1, WHITE, BLACK);
LCDPutStr("Cmd:", MAX_X / 2 - 10, 1, WHITE, BLACK);
LCDPutStr("Toggle:", MAX_X / 2 - 25, 1, WHITE, BLACK);
LCDPutStr("Count:", MAX_X / 2 - 40, 1, WHITE, BLACK);
while (1) {
// put chip to sleep
switch(mcupower) {
case PMU_MCU_SLEEP:
default:
LCDPutStr("SLEEP ", MAX_X / 2 - 60, 10, WHITE, BLACK);
Chip_PMU_SleepState(LPC_PMU);
break;
case PMU_MCU_DEEP_SLEEP:
LCDPutStr("DEEP-SLEEP", MAX_X / 2 - 60, 10, WHITE, BLACK);
Chip_PMU_DeepSleepState(LPC_PMU);
break;
case PMU_MCU_POWER_DOWN:
LCDPutStr("POWER-DOWN", MAX_X / 2 - 60, 10, WHITE, BLACK);
Chip_PMU_PowerDownState(LPC_PMU);
break;
}
// start MRT timer channel 0
Chip_MRT_SetInterval(LPC_MRT_CH0, SystemCoreClock | MRT_INTVAL_LOAD);
Chip_MRT_SetMode(LPC_MRT_CH0,MRT_MODE_ONESHOT);
Chip_MRT_SetEnabled(LPC_MRT_CH0);
// turn on onboard LED
Chip_GPIO_SetPinState(LPC_GPIO_PORT,0,LED_PIN,false);
// start SCT
LPC_SCT->CTRL_L &= ~SCT_CTRL_HALT_L;
// wait for timeout
while(!RC5_timeout)
{};
// stop SCT
LPC_SCT->CTRL_L |= SCT_CTRL_HALT_L;
if (RC5_flag) {
// if frame received, output information on LCD
if((RC5_System != RC5_System_prev) || (RC5_Command != RC5_Command_prev)) {
cnt = 1;
}
else {
cnt++;
}
for (i = 3; i >= 0; i--){
LCDPutChar(ascii[(RC5_Frame >> (i * 4)) & 0x0F],MAX_X / 2 + 20,80+(3-i)*7,WHITE, BLACK);
if(i < 2) {
if((RC5_System!=RC5_System_prev) || (RC5_Command!=RC5_Command_prev)){
LCDPutChar(ascii[(RC5_System >> (i * 4)) & 0x0F],MAX_X / 2 + 5,66+(3-i)*7,WHITE, BLACK);
LCDPutChar(ascii[(RC5_Command >> (i * 4)) & 0x0F],MAX_X / 2 - 10,66+(3-i)*7,WHITE, BLACK);
}
}
LCDPutChar(ascii[(cnt >> (i * 4)) & 0x0F],MAX_X / 2 - 40,80+(3-i)*7,WHITE, BLACK);
}
LCDPutStr(RC5_Toggle ? "ON ":"OFF", MAX_X / 2 - 25, 80, WHITE, BLACK);
switch(RC5_Command) {
case 0x50:
mcupower = PMU_MCU_SLEEP;
break;
case 0x55:
if(RC5_Toggle){
spi0Transfer(SLEEPOUT);
spi0Transfer(DISPON);
}
else {
spi0Transfer(DISPOFF);
spi0Transfer(SLEEPIN);
}
break;
case 0x56:
mcupower = PMU_MCU_DEEP_SLEEP;
break;
case 0x6B:
mcupower = PMU_MCU_POWER_DOWN;
break;
}
RC5_System_prev = RC5_System;
RC5_Command_prev = RC5_Command;
}
// turn off onboard LED
Chip_GPIO_SetPinState(LPC_GPIO_PORT,0,LED_PIN,true);
// clear flags
RC5_flag = 0;
RC5_timeout = 0;
}
