/*******************************************************************************
* Function Name: main
********************************************************************************
* Summary:
* Main function performs following functions:
* 1. Starts Character LCD and print project info
* 2. Starts SPI Master component
* 3. Configures the DMA transfer for RX and TX directions
* 4. Displays the results on Character LCD
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void main()
{
uint8 i = 0u;
CyGlobalIntEnable;
for(i=0u; i<8u; i++)
{
m_rxBuffer[i] = 0u;
}
LCD_Start();
LCD_Position(0u,0u);
LCD_PrintString("SPI Master");
LCD_Position(1u,0u);
LCD_PrintString("example");
CyDelay(3000u);
Dma_M_Tx_Configuration();
Dma_M_Rx_Configuration();
CyDmaChEnable(M_TxChannel, 1u);
CyDmaChEnable(M_RxChannel, 1u);
LCD_Position(0u,0u);
LCD_PrintString("Master Tx data:");
LCD_Position(1u,0u);
for(i=0u; i<8u; i++)
{
LCD_PrintHexUint8(m_txBuffer[i]);
}
CyDelay(5000u);
SPIM_Start();
while(!(SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE));
LCD_ClearDisplay();
LCD_PrintString("Master Rx data:");
LCD_Position(1u,0u);
for(i=0u; i<8u; i++)
{
LCD_PrintHexUint8(m_rxBuffer[i]);
}
CyDelay(5000u);
LCD_ClearDisplay();
LCD_PrintString("SPI Master");
LCD_Position(1u,0u);
LCD_PrintString("example complete.");
for(;;)
{
}
}
void Configure_DMA(){
ADC2Filter_DMA_Chan = ADC2Filter_DMA_DmaInitialize(ADC2Filter_DMA_BYTES_PER_BURST, ADC2Filter_DMA_REQUEST_PER_BURST,
HI16(ADC2Filter_DMA_SRC_BASE), HI16(ADC2Filter_DMA_DST_BASE));
ADC2Filter_DMA_TD[0] = CyDmaTdAllocate();
ADC2Filter_DMA_TD[1] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(ADC2Filter_DMA_TD[0], 2, ADC2Filter_DMA_TD[1], TD_AUTO_EXEC_NEXT);
CyDmaTdSetConfiguration(ADC2Filter_DMA_TD[1], 2, ADC2Filter_DMA_TD[0], ADC2Filter_DMA__TD_TERMOUT_EN);
CyDmaTdSetAddress(ADC2Filter_DMA_TD[0], LO16((uint32)ADC_DelSig_1_DEC_SAMP_PTR), LO16((uint32)Filter_STAGEA_PTR));
CyDmaTdSetAddress(ADC2Filter_DMA_TD[1], LO16((uint32)ADC_DelSig_1_DEC_SAMP_PTR), LO16((uint32)Filter_STAGEB_PTR));
CyDmaChSetInitialTd(ADC2Filter_DMA_Chan, ADC2Filter_DMA_TD[0]);
CyDmaChEnable(ADC2Filter_DMA_Chan, 1);
/*Second buffer*/
DMA_2_Chan = DMA_2_DmaInitialize(DMA_2_BYTES_PER_BURST, DMA_2_REQUEST_PER_BURST,
HI16(DMA_2_SRC_BASE), HI16(DMA_2_DST_BASE));
DMA_2_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_2_TD[0], buffersize, CY_DMA_DISABLE_TD /* DMA_2_TD[0]*/, DMA_2__TD_TERMOUT_EN | TD_INC_SRC_ADR | TD_INC_DST_ADR);
CyDmaTdSetAddress(DMA_2_TD[0], LO16((uint32)ADC_samples), LO16((uint32)Buffer_samples));
CyDmaChSetInitialTd(DMA_2_Chan, DMA_2_TD[0]);
CyDmaChEnable(DMA_2_Chan, 1);
/*First buffer*/
DMA_1_Chan = DMA_1_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST,
HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE));
DMA_1_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_1_TD[0], buffersize,/* CY_DMA_DISABLE_TD*/ DMA_1_TD[0], DMA_1__TD_TERMOUT_EN | TD_INC_DST_ADR);
CyDmaTdSetAddress(DMA_1_TD[0], LO16((uint32)Filter_HOLDA_PTR), LO16((uint32)ADC_samples));
CyDmaChSetInitialTd(DMA_1_Chan, DMA_1_TD[0]);
CyDmaChEnable(DMA_1_Chan, 1);
DMA_3_Chan = DMA_3_DmaInitialize(DMA_3_BYTES_PER_BURST, DMA_3_REQUEST_PER_BURST,
HI16(DMA_3_SRC_BASE), HI16(DMA_3_DST_BASE));
DMA_3_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_3_TD[0], buffersize, DMA_3_TD[0], DMA_3__TD_TERMOUT_EN | TD_INC_DST_ADR);
CyDmaTdSetAddress(DMA_3_TD[0], LO16((uint32)Filter_HOLDB_PTR), LO16((uint32)LPF_samples));
CyDmaChSetInitialTd(DMA_3_Chan, DMA_3_TD[0]);
CyDmaChEnable(DMA_3_Chan, 1);
DMA_4_Chan = DMA_4_DmaInitialize(DMA_4_BYTES_PER_BURST, DMA_4_REQUEST_PER_BURST,
HI16(DMA_4_SRC_BASE), HI16(DMA_4_DST_BASE));
DMA_4_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_4_TD[0], buffersize, CY_DMA_DISABLE_TD /*DMA_4_TD[0]*/, DMA_4__TD_TERMOUT_EN | TD_INC_SRC_ADR | TD_INC_DST_ADR);
CyDmaTdSetAddress(DMA_4_TD[0], LO16((uint32)LPF_samples), LO16((uint32)LPF_buffer));
CyDmaChSetInitialTd(DMA_4_Chan, DMA_4_TD[0]);
CyDmaChEnable(DMA_4_Chan, 1);
}
static void
doTxSingleDMA(const uint8* data, uint32 count)
{
// Prepare DMA transfer
dmaInProgress = 1;
trace(trace_doTxSingleDMA);
CyDmaTdSetConfiguration(
scsiDmaTxTd[0],
count,
CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes
TD_INC_SRC_ADR |
SCSI_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete
);
CyDmaTdSetAddress(
scsiDmaTxTd[0],
LO16((uint32)data),
LO16((uint32)scsiTarget_datapath__F0_REG));
CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]);
// The DMA controller is a bit trigger-happy. It will retain
// a drq request that was triggered while the channel was
// disabled.
CyDmaClearPendingDrq(scsiDmaTxChan);
scsiTxDMAComplete = 0;
scsiRxDMAComplete = 1;
CyDmaChEnable(scsiDmaTxChan, 1);
}
/*******************************************************************************
* Function Name: AuxDetection_Start
********************************************************************************
* Summary:
* This routine starts the AUX detection process and enable I2S receive.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void AuxDetection_Start(void)
{
isr_Aux_StartEx(Aux_Interrupt);
CyDmaChEnable(I2SRxMDAChan, 1);
I2S_ClearRxFIFO();
I2S_RX_AUX_CONTROL_REG = I2S_RX_AUX_CONTROL_REG & (~FIFO_HALF_EMPTY_MASK);
I2S_EnableRx();
}
static void DMA_Start()
{
*(reg8*)Camera_FIFO_dp__F0_REG;
*(reg8*)Camera_FIFO_dp__F0_REG;
*(reg8*)Camera_FIFO_dp__F0_REG;
*(reg8*)Camera_FIFO_dp__F0_REG; //clear fifo
CyDmaClearPendingDrq(DMA_channel); //invalidate pending requests
CyDmaChSetInitialTd(DMA_channel,DMA_TD[0]); //set initial TD
CyDmaChEnable(DMA_channel,1); //enable channel (start streaming)
}
/*******************************************************************************
* Function Name: WaveDAC8_1_Enable
********************************************************************************
*
* Summary:
* Enables the DAC block and DMA operation.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void WaveDAC8_1_Enable(void)
{
WaveDAC8_1_VDAC8_Enable();
#if(WaveDAC8_1_OUT_MODE == WaveDAC8_1_BUFFER_MODE)
WaveDAC8_1_BuffAmp_Enable();
#endif /* WaveDAC8_1_OUT_MODE == WaveDAC8_1_BUFFER_MODE */
/*
* Enable the channel. It is configured to remember the TD value so that
* it can be restored from the place where it has been stopped.
*/
(void)CyDmaChEnable(WaveDAC8_1_Wave1Chan, 1u);
(void)CyDmaChEnable(WaveDAC8_1_Wave2Chan, 1u);
/* set the initial value */
WaveDAC8_1_SetValue(0u);
#if(WaveDAC8_1_CLOCK_SRC == WaveDAC8_1_CLOCK_INT)
WaveDAC8_1_DacClk_Start();
#endif /* WaveDAC8_1_CLOCK_SRC == WaveDAC8_1_CLOCK_INT */
}
/*******************************************************************************
* Function Name: main
********************************************************************************
* Summary:
* Main function performs following functions:
* 1. Starts Character LCD and print project info
* 2. Starts SPI Master component
* 3. Configures the DMA transfer for RX and TX directions
* 4. Displays the results on Character LCD
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
int main()
{
uint8 i;
LCD_Start();
LCD_Position(0u,0u);
LCD_PrintString("SPI Master");
LCD_Position(1u,0u);
LCD_PrintString("example");
CyDelay(2000u);
DmaTxConfiguration();
DmaRxConfiguration();
SPIM_Start();
CyDmaChEnable(rxChannel, STORE_TD_CFG_ONCMPLT);
CyDmaChEnable(txChannel, STORE_TD_CFG_ONCMPLT);
while (0u == (SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE))
{
}
LCD_ClearDisplay();
LCD_PrintString("Master Rx data:");
LCD_Position(1u,0u);
for(i=0u; i<BUFFER_SIZE; i++)
{
LCD_PrintHexUint8(rxBuffer[i]);
}
for(;;)
{
}
}
void `$INSTANCE_NAME`_Start() {
uint8* DMA_TD = (uint8*)`$INSTANCE_NAME`_DMA_TD;
uint8 numTD = `$INSTANCE_NAME`_numTD;
uint8* pwm_data_ptr = ((uint8*)&`$INSTANCE_NAME`_PWM_data) + 0x40;
uint8* dc_data_ptr = (uint8*)&`$INSTANCE_NAME`_PWM_data;
uint8 i,j,k;
for (i=0; i<4; i++)
for (j=0; j<8; j++)
`$INSTANCE_NAME`_PWM_data.dc[i][j] = 0;
for (i=0; i<4; i++)
for (j=0; j<16; j++)
`$INSTANCE_NAME`_PWM_data.pwm[i][j] = 0;
uint8 interruptState;
interruptState = CyEnterCriticalSection();
*(reg8*)`$INSTANCE_NAME`_C_TLC5940_WordCounter__CONTROL_AUX_CTL_REG |= 0x20u;
*(reg8*)`$INSTANCE_NAME`_C_TLC5940_BitCounter__CONTROL_AUX_CTL_REG |= 0x20u;
*(reg8*)`$INSTANCE_NAME`_C_TLC5940_WordCounter__PERIOD_REG = 0x08;
*(reg8*)`$INSTANCE_NAME`_C_TLC5940_gsclk_counter_GSCLKCounter_u0__D1_REG = 0x04;
`$INSTANCE_NAME`_DP_AUX_0 |= 5;
`$INSTANCE_NAME`_DP_AUX_1 |= 5;
`$INSTANCE_NAME`_DP_AUX_0 &= ~0x01;
`$INSTANCE_NAME`_DP_AUX_1 &= ~0x01;
CyExitCriticalSection(interruptState);
`$INSTANCE_NAME`_DMA_Chan = `$INSTANCE_NAME`_DMA_DmaInitialize(`$INSTANCE_NAME`_DMA_BYTES_PER_BURST, `$INSTANCE_NAME`_DMA_REQUEST_PER_BURST,
HI16(`$INSTANCE_NAME`_DMA_SRC_BASE), HI16(`$INSTANCE_NAME`_DMA_DST_BASE));
for (i = 0; i < numTD; i++)
DMA_TD[i] = CyDmaTdAllocate();
for (i = 0; i < numTD; i++) {
CyDmaTdSetConfiguration(DMA_TD[i], 16, DMA_TD[(i+1)%numTD], TD_TERMIN_EN | `$INSTANCE_NAME`_DMA__TD_TERMOUT_EN | TD_INC_SRC_ADR);
}
for (i = 0; i < 4; i++) {
CyDmaTdSetAddress(DMA_TD[i*3], LO16((uint32)dc_data_ptr + i*16 ), LO16((uint32)`$INSTANCE_NAME`_SHIFT_REG_FIFO));
CyDmaTdSetAddress(DMA_TD[i*3+1], LO16((uint32)pwm_data_ptr + i*32 ), LO16((uint32)`$INSTANCE_NAME`_SHIFT_REG_FIFO));
CyDmaTdSetAddress(DMA_TD[i*3+2], LO16((uint32)pwm_data_ptr + i*32 + 16 ), LO16((uint32)`$INSTANCE_NAME`_SHIFT_REG_FIFO));
}
CyDmaChSetInitialTd(`$INSTANCE_NAME`_DMA_Chan, DMA_TD[0]);
CyDmaChEnable(`$INSTANCE_NAME`_DMA_Chan, 1);
}
void DMA_2_Config()
{
// Variable declarations for DMA_2
// Move these variable declarations to the top of the function
uint8 DMA_2_Chan;
uint8 DMA_2_TD[1];
// DMA Configuration for DMA_2
#define DMA_2_BYTES_PER_BURST 2
#define DMA_2_REQUEST_PER_BURST 1
#define DMA_2_SRC_BASE (CYDEV_PERIPH_BASE)
#define DMA_2_DST_BASE (CYDEV_SRAM_BASE)
DMA_2_Chan = DMA_2_DmaInitialize(DMA_2_BYTES_PER_BURST, DMA_2_REQUEST_PER_BURST, HI16(DMA_2_SRC_BASE), HI16(DMA_2_DST_BASE));
DMA_2_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_2_TD[0], n*2, DMA_INVALID_TD, TD_SWAP_EN | DMA_2__TD_TERMOUT_EN | TD_INC_SRC_ADR | TD_INC_DST_ADR);
CyDmaTdSetAddress(DMA_2_TD[0], LO16((uint32)Filter_1_HOLDAM_PTR), LO16((uint32)V_Sample));
CyDmaChSetInitialTd(DMA_2_Chan, DMA_2_TD[0]);
CyDmaChEnable(DMA_2_Chan, 1);
}
void DMA_1_Config()
{
// Variable declarations for DMA_1
// Move these variable declarations to the top of the function
uint8 DMA_1_Chan;
uint8 DMA_1_TD[1];
// DMA Configuration for DMA_1
#define DMA_1_BYTES_PER_BURST 2
#define DMA_1_REQUEST_PER_BURST 1
#define DMA_1_SRC_BASE (CYDEV_PERIPH_BASE)
#define DMA_1_DST_BASE (CYDEV_PERIPH_BASE)
DMA_1_Chan = DMA_1_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST, HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE));
DMA_1_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_1_TD[0], 2, DMA_INVALID_TD, TD_INC_DST_ADR);
CyDmaTdSetAddress(DMA_1_TD[0], LO16((uint32)ADC_DelSig_1_DEC_SAMP_PTR), LO16((uint32)Filter_1_STAGEAM_PTR));
CyDmaChSetInitialTd(DMA_1_Chan, DMA_1_TD[0]);
CyDmaChEnable(DMA_1_Chan, 1);
}
/*main*/
void main(void)
{
/*Preliminary parts not important*/
LCD_Char_1_Start();
ADC_DelSig_1_Start();
ADC_DelSig_1_StartConvert();
Configure_DMA();
isr_1_StartEx(Buffer_complete);
isr_2_StartEx(LPF_buffer_complete);
ADC_DelSig_1_SetCoherency(ADC_DelSig_1_COHER_MID);
Filter_SetDalign(Filter_STAGEA_DALIGN,Filter_ENABLED);
Filter_SetDalign(Filter_HOLDA_DALIGN,Filter_ENABLED);
Filter_SetCoherency(Filter_STAGEA_COHER,Filter_KEY_MID);
Filter_SetCoherency(Filter_HOLDA_COHER,Filter_KEY_MID);
Filter_SetCoherency(Filter_CHANNEL_A,Filter_KEY_MID);
Filter_SetDalign(Filter_STAGEB_DALIGN,Filter_ENABLED);
Filter_SetDalign(Filter_HOLDB_DALIGN,Filter_ENABLED);
Filter_SetCoherency(Filter_STAGEB_COHER,Filter_KEY_MID);
Filter_SetCoherency(Filter_HOLDB_COHER,Filter_KEY_MID);
Filter_SetCoherency(Filter_CHANNEL_B,Filter_KEY_MID);
CyGlobalIntEnable;
Filter_Start();
/*Writes ADC values to ADC_samples array*/
while(1){
if (isr_BC_flag==1){
arm_cfft_q15(&arm_cfft_sR_q15_len256, Buffer_samples, 0, 1);
arm_cmplx_mag_q15(Buffer_samples, magoutput, fftlength);
CyDmaChEnable(DMA_2_Chan, 1);
isr_BC_flag=0;
isr_1_ClearPending();
}
}
}
/*******************************************************************************
* Function Name: USBFS_1_LoadInEP
********************************************************************************
*
* Summary:
* Loads and enables the specified USB data endpoint for an IN interrupt or bulk
* transfer.
*
* Parameters:
* epNumber: Contains the data endpoint number.
* Valid values are between 1 and 8.
* *pData: A pointer to a data array from which the data for the endpoint space
* is loaded.
* length: The number of bytes to transfer from the array and then send as a
* result of an IN request. Valid values are between 0 and 512.
*
* Return:
* None.
*
* Reentrant:
* No.
*
*******************************************************************************/
void USBFS_1_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
{
uint8 ri;
reg8 *p;
#if(USBFS_1_EP_MM == USBFS_1__EP_MANUAL)
uint16 i;
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_MANUAL */
if((epNumber > USBFS_1_EP0) && (epNumber < USBFS_1_MAX_EP))
{
ri = ((epNumber - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);
p = (reg8 *)(USBFS_1_ARB_RW1_DR_IND + ri);
#if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)
/* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */
if(length > (USBFS_1_EPX_DATA_BUF_MAX - USBFS_1_EP[epNumber].buffOffset))
{
length = USBFS_1_EPX_DATA_BUF_MAX - USBFS_1_EP[epNumber].buffOffset;
}
#endif /* End USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO */
/* Set the count and data toggle */
CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT0_IND + ri),
(length >> 8u) | (USBFS_1_EP[epNumber].epToggle));
CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT1_IND + ri), length & 0xFFu);
#if(USBFS_1_EP_MM == USBFS_1__EP_MANUAL)
if(pData != NULL)
{
/* Copy the data using the arbiter data register */
for (i = 0u; i < length; i++)
{
CY_SET_REG8(p, pData[i]);
}
}
USBFS_1_EP[epNumber].apiEpState = USBFS_1_NO_EVENT_PENDING;
/* Write the Mode register */
CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_EP[epNumber].epMode);
#else
/* Init DMA if it was not initialized */
if(USBFS_1_DmaTd[epNumber] == DMA_INVALID_TD)
{
USBFS_1_InitEP_DMA(epNumber, pData);
}
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_MANUAL */
#if(USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL)
USBFS_1_EP[epNumber].apiEpState = USBFS_1_NO_EVENT_PENDING;
if((pData != NULL) && (length > 0u))
{
/* Enable DMA in mode2 for transferring data */
(void) CyDmaChDisable(USBFS_1_DmaChan[epNumber]);
(void) CyDmaTdSetConfiguration(USBFS_1_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,
TD_TERMIN_EN | TD_INC_SRC_ADR);
(void) CyDmaTdSetAddress(USBFS_1_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));
/* Enable the DMA */
(void) CyDmaChSetInitialTd(USBFS_1_DmaChan[epNumber], USBFS_1_DmaTd[epNumber]);
(void) CyDmaChEnable(USBFS_1_DmaChan[epNumber], 1u);
/* Generate DMA request */
* (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) |= USBFS_1_ARB_EPX_CFG_DMA_REQ;
* (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_1_ARB_EPX_CFG_DMA_REQ));
/* Mode register will be written in arb ISR after DMA transfer complete */
}
else
{
/* When zero-length packet - write the Mode register directly */
CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_EP[epNumber].epMode);
}
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL */
#if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)
if(pData != NULL)
{
/* Enable DMA in mode3 for transferring data */
(void) CyDmaChDisable(USBFS_1_DmaChan[epNumber]);
(void) CyDmaTdSetConfiguration(USBFS_1_DmaTd[epNumber], length,
USBFS_1_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
(void) CyDmaTdSetAddress(USBFS_1_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));
/* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
(void) CyDmaClearPendingDrq(USBFS_1_DmaChan[epNumber]);
/* Enable the DMA */
(void) CyDmaChSetInitialTd(USBFS_1_DmaChan[epNumber], USBFS_1_DmaTd[epNumber]);
(void) CyDmaChEnable(USBFS_1_DmaChan[epNumber], 1u);
}
else
{
USBFS_1_EP[epNumber].apiEpState = USBFS_1_NO_EVENT_PENDING;
if(length > 0u)
{
/* Set Data ready status, This will generate DMA request */
* (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) |= USBFS_1_ARB_EPX_CFG_IN_DATA_RDY;
/* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */
}
else
{
/* When zero-length packet - write the Mode register directly */
CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_EP[epNumber].epMode);
}
}
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */
}
/*******************************************************************************
* Function Name: OSC1_ADC_SAR_Enable
********************************************************************************
*
* Summary:
* Enables DMA channels, address selection counter and FSM of Base component
*
* Parameters:
* None.
*
* Return:
* None.
*
* Side Effects:
* None.
*
* Reentrant:
* No.
*
*******************************************************************************/
void OSC1_ADC_SAR_Enable(void)
{
uint8 enableInterrupts;
static int16 OSC1_ADC_SAR_tempArray[OSC1_ADC_SAR_NUMBER_OF_CHANNELS];
(void)CyDmaClearPendingDrq(OSC1_ADC_SAR_tempChan);
(void)CyDmaClearPendingDrq(OSC1_ADC_SAR_finalChan);
/* Provides initialization procedure for the TempBuf DMA
* Configure this Td as follows:
* - The TD is looping on itself
* - Increment the destination address, but not the source address
*/
if (OSC1_ADC_SAR_tempTD == DMA_INVALID_TD)
{
OSC1_ADC_SAR_tempTD = CyDmaTdAllocate();
}
(void) CyDmaTdSetConfiguration(OSC1_ADC_SAR_tempTD, OSC1_ADC_SAR_TEMP_TRANSFER_COUNT,
OSC1_ADC_SAR_tempTD, ((uint8)OSC1_ADC_SAR_TempBuf__TD_TERMOUT_EN | (uint8)TD_INC_DST_ADR));
/* From the SAR to the TempArray */
(void) CyDmaTdSetAddress(OSC1_ADC_SAR_tempTD, (uint16)(LO16((uint32)OSC1_ADC_SAR_SAR_DATA_ADDR_0)),
(uint16)(LO16((uint32)OSC1_ADC_SAR_tempArray)));
/* Associate the TD with the channel */
(void) CyDmaChSetInitialTd(OSC1_ADC_SAR_tempChan, OSC1_ADC_SAR_tempTD);
/* Provides initialization procedure for the FinalBuf DMA
* Configure this Td as follows:
* - The TD is looping on itself
* - Increment the source and destination address
*/
if (OSC1_ADC_SAR_finalTD == DMA_INVALID_TD)
{
OSC1_ADC_SAR_finalTD = CyDmaTdAllocate();
}
(void) CyDmaTdSetConfiguration(OSC1_ADC_SAR_finalTD, (OSC1_ADC_SAR_FINAL_BYTES_PER_BURST),
OSC1_ADC_SAR_finalTD, ((uint8)(OSC1_ADC_SAR_FinalBuf__TD_TERMOUT_EN) | (uint8)TD_INC_SRC_ADR |
(uint8)TD_INC_DST_ADR));
/* From the the TempArray to Final Array */
(void) CyDmaTdSetAddress(OSC1_ADC_SAR_finalTD, (uint16)(LO16((uint32)OSC1_ADC_SAR_tempArray)),
(uint16)(LO16((uint32)OSC1_ADC_SAR_finalArray)));
/* Associate the TD with the channel */
(void) CyDmaChSetInitialTd(OSC1_ADC_SAR_finalChan, OSC1_ADC_SAR_finalTD);
(void) CyDmaChEnable(OSC1_ADC_SAR_tempChan, 1u);
(void) CyDmaChEnable(OSC1_ADC_SAR_finalChan, 1u);
/* Enable Counter and give Enable pulse to set an address of the last channel */
enableInterrupts = CyEnterCriticalSection();
OSC1_ADC_SAR_CYCLE_COUNTER_AUX_CONTROL_REG |= ((uint8)(OSC1_ADC_SAR_CYCLE_COUNTER_ENABLE));
CyExitCriticalSection(enableInterrupts);
/* Enable FSM of the Base Component */
OSC1_ADC_SAR_CONTROL_REG |= ((uint8)(OSC1_ADC_SAR_BASE_COMPONENT_ENABLE));
OSC1_ADC_SAR_CONTROL_REG |= ((uint8)(OSC1_ADC_SAR_LOAD_COUNTER_PERIOD));
#if(OSC1_ADC_SAR_IRQ_REMOVE == 0u)
/* Clear a pending interrupt */
CyIntClearPending(OSC1_ADC_SAR_INTC_NUMBER);
#endif /* End OSC1_ADC_SAR_IRQ_REMOVE */
}
/*******************************************************************************
* Function Name: DMA_Config
********************************************************************************
*
* Summary:
* Initializes and sets up DMA for use (generated by DMA Wizard)
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void DMA_Config(void)
{
/* Declare variable to hold the handle for DMA channel */
uint8 channelHandle;
/* Declare DMA Transaction Descriptor for memory transfer into
* Filter Channel.
*/
uint8 tdChanA;
/* Configure the DMA to Transfer the data in 1 burst with individual trigger
* for each burst.
*/
channelHandle = DMA_DmaInitialize(BYTES_PER_BURST, REQUEST_PER_BURST,
HI16(UPPER_SRC_ADDRESS), HI16(UPPER_DEST_ADDRESS));
/* This function allocates a TD for use with an initialized DMA channel */
tdChanA = CyDmaTdAllocate();
/* Configure the tdChanA to transfer 1 byte with no next TD */
CyDmaTdSetConfiguration(tdChanA, 1u, DMA_INVALID_TD, 0u);
/* Set the source address as ADC_DelSig and the destination as
* Filter Channel A.
*/
CyDmaTdSetAddress(tdChanA, LO16((uint32)ADC_DelSig_DEC_SAMP_PTR), LO16((uint32)Filter_STAGEAH_PTR));
/* Set tdChanA to be the initial TD associated with channelHandle */
CyDmaChSetInitialTd(channelHandle, tdChanA);
/* Enable the DMA channel represented by channelHandle and preserve the TD */
CyDmaChEnable(channelHandle, 1u);
uint8 DMA_1_Chan;
uint8 DMA_1_TD[1];
DMA_1_Chan = DMA_1_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST,
HI16(DMA_1_SRC_BASE), HI16(DMA_1_DST_BASE));
DMA_1_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_1_TD[0], buffersize, CY_DMA_DISABLE_TD, TD_INC_DST_ADR);
CyDmaTdSetAddress(DMA_1_TD[0], LO16((uint32)Filter_HOLDA_PTR), LO16((uint32)buffer));
CyDmaChSetInitialTd(DMA_1_Chan, DMA_1_TD[0]);
CyDmaChEnable(DMA_1_Chan, 1);
/* Variable declarations for DMA_2 */
/* Move these variable declarations to the top of the function */
uint8 DMA_2_Chan;
uint8 DMA_2_TD[1];
DMA_2_Chan = DMA_2_DmaInitialize(DMA_2_BYTES_PER_BURST, DMA_2_REQUEST_PER_BURST,
HI16(DMA_2_SRC_BASE), HI16(DMA_2_DST_BASE));
DMA_2_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_2_TD[0], 1, CY_DMA_DISABLE_TD, 0);
CyDmaTdSetAddress(DMA_2_TD[0], LO16((uint32)Filter_HOLDA_PTR), LO16((uint32)VDAC8_Data_PTR));
CyDmaChSetInitialTd(DMA_2_Chan, DMA_2_TD[0]);
CyDmaChEnable(DMA_2_Chan, 1);
}
void USBrefresh()
{
uint8 skipNextOut = 0u;
/* Check if configuration or interface settings are changed. */
if (0u != USBFS_IsConfigurationChanged())
{
/* Check active alternate setting. */
if ((0u != USBFS_GetConfiguration()) &&
(0u != USBFS_GetInterfaceSetting(AUDIO_INTERFACE)))
{
/* Alternate settings 1: Audio is streaming. */
/* Reset variables. */
inIndex = 0u;
outIndex = 0u;
syncDma = 0u;
skipNextOut = 0u;
syncDmaCounter = 0u;
/* Enable OUT endpoint to receive audio stream. */
USBFS_EnableOutEP(OUT_EP_NUM);
}
if (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(OUT_EP_NUM))
{
if (0u == skipNextOut)
{
/* Trigger DMA to copy data from OUT endpoint buffer. */
USBFS_ReadOutEP(OUT_EP_NUM, &soundBuffer[inIndex * TRANSFER_SIZE],
TRANSFER_SIZE);
/* Wait until DMA completes copying data from OUT endpoint buffer. */
while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(OUT_EP_NUM))
{
}
/* Move to the next buffer location and adjust to be within
* buffer size. Lock from DmaDone interruption.
*/
DmaDone_Disable();
++inIndex;
inIndex = (inIndex >= NUM_OF_BUFFERS) ? 0u : inIndex;
DmaDone_Enable();
++syncDmaCounter;
/* Enable OUT endpoint to receive data from host. */
USBFS_EnableOutEP(OUT_EP_NUM);
}
else
{
/* Ignore received data from host and arm OUT endpoint
* without reading if overflow is detected.
*/
USBFS_EnableOutEP(OUT_EP_NUM);
skipNextOut = 0u;
}
/* When internal 32-kHz clock is slower, compare to PC traffic
* then skip next transfer from PC.
*/
if (outIndex == inIndex)
{
skipNextOut = 1u;
}
}
/* Enable DMA transfers when sound buffer is half-full. */
if ((0u == syncDma) && (syncDmaCounter == (NUM_OF_BUFFERS / 2u)))
{
/* Start DMA operation. */
CyDmaChEnable(TxOutDmaCh, TX_DMA_ENABLE_PRESERVE_TD);
/* Disable underflow delayed start. */
syncDma = 1u;
}
}
}
void `$INSTANCE_NAME`_Enable() {
CyDmaChSetInitialTd(`$INSTANCE_NAME`_DMA_Chan, `$INSTANCE_NAME`_DMA_TD[0]);
CyDmaChEnable(`$INSTANCE_NAME`_DMA_Chan, 1);
`$INSTANCE_NAME`_CONTROL = 0x02;
}
