TCgReturnCode CgxDriverConstruct(void *pDriver, TCgxDriverState *pState)
{
//DBG_FUNC_NAME("CgxDriverConstruct")
TCgReturnCode rc = ECgOk;
rc = CgCpuAllocateVa();
memset(gChunksList,0,sizeof(TCgCpuDmaTask)*MAX_DMA_TRANSFER_TASKS);
gps_gpio_request();
#if 0
if (OK(rc)) rc = CgCpuDmaCreate(CG_DRIVER_DMA_CHANNEL_READ, CGCORE_BASE_ADDR + 0x00000070);
// set up DMA interrupt handler
if (OK(rc)) rc = CgxDriverDmaInterruptPrepare();
#endif
if (OK(rc)) rc = CgxDriverDataReadyInterruptHandlerStart(pDriver);
// set up internal synchronization mechanism
if (OK(rc)) rc = CgxDriverTransferEndCreate(pDriver);
// set up GPS interrupt handler
if (OK(rc)) rc = CgxDriverGpsInterruptPrepare();
if (OK(rc)) rc = CgxDriverGpsInterruptHandlerStart(pDriver);
#if 0
// enable IP (not-reset)
if (OK(rc)) rc = CgCpuGpioModeSet(CG_DRIVER_GPIO_GPS_MRSTN, ECG_CPU_GPIO_OUTPUT);
if (OK(rc)) rc = CgCpuIPMasterResetOn();
if (OK(rc)) rc = CgCpuDelay(CGCORE_RESET_DELAY);
if (OK(rc)) rc = CgCpuIPMasterResetClear();
// set up Sclk register
if (OK(rc)) rc = CGCoreSclkEnable(1);
DBGMSG1("CGCORE_CORE_SCLK_ENABLE = 0x%08X", CGCORE_ENABLE_SCLK);
// set up core-resets register
if (OK(rc)) rc = CGCORE_WRITE_REG( CGCORE_REG_OFFSET_CORE_RESETS, CGCORE_CORE_RESETS_ENABLE);
DBGMSG1("CGCORE_CORE_RESETS_ENABLE = 0x%08X", CGCORE_CORE_RESETS_ENABLE);
// Setup GPIO for RF-Power, and power up RF chip
//if (OK(rc)) rc = CgCpuGpioModeSet(CG_DRIVER_GPIO_RF_PD, ECG_CPU_GPIO_OUTPUT);
//if (OK(rc)) rc = CgxDriverRFPowerUp();
if (OK(rc)) rc = CgCpuGpioModeSet(CG_DRIVER_GPIO_TCXO_EN, ECG_CPU_GPIO_OUTPUT);
if (OK(rc)) rc = CgxDriverTcxoControl(TRUE);
#endif
pState->constructionRc = rc; // For later reference (if needed by application)
pState->flags.resume = FALSE;
#ifdef CGCORE_ACCESS_VIA_SPI
gps_chip_power_off();
#endif
return rc;
}
void panic(int led1, int led2)
{
DBGMSG1("Panic!");
for(;;) {
_delay_ms(1000);
setLed(led1);
_delay_ms(1000);
setLed(led2);
}
}
TCgReturnCode CGCoreReset(U32 aUnitToReset)
{
DBG_FUNC_NAME("CGCoreReset")
TCgReturnCode rc = ECgOk;
U32 coreResetsReg = 0;
U32 coreResetsRegOld = 0;
////////////////// Core Disable //////////////
rc = CGCORE_READ_REG(CGCORE_REG_OFFSET_CORE_RESETS,&coreResetsReg);
coreResetsRegOld = coreResetsReg;
REG_SET1(coreResetsReg, aUnitToReset, 0);
if (OK(rc)) rc = CGCORE_WRITE_REG(CGCORE_REG_OFFSET_CORE_RESETS,coreResetsReg);
DBGMSG1("Write [0x%08X]", coreResetsReg);
if (OK(rc)) rc = CgCpuDelay(CGCORE_RESET_DELAY);
////////////////// Core Enable //////////////
if (OK(rc)) rc = CGCORE_WRITE_REG( CGCORE_REG_OFFSET_CORE_RESETS, coreResetsRegOld);
DBGMSG1("Write [0x%08X]", coreResetsRegOld);
return rc;
}
TCgReturnCode CGCoreDisable(U32 aUnitToDisable)
{
DBG_FUNC_NAME("CGCoreDisable")
TCgReturnCode rc = ECgOk;
U32 disableValue = 0;
U32 coreResetsReg = 0;
rc = CGCORE_READ_REG(CGCORE_REG_OFFSET_CORE_RESETS,&coreResetsReg);
// DBGMSG1("Read coreResetsReg=0x%08X", coreResetsReg);
REG_SET1(coreResetsReg, aUnitToDisable, disableValue);
if (OK(rc)) rc = CGCORE_WRITE_REG(CGCORE_REG_OFFSET_CORE_RESETS,coreResetsReg);
DBGMSG1("Write [0x%08X]", coreResetsReg);
return ECgOk;
}
TCgReturnCode CgxDriverIsReadCanceled(TCgxDriverState *pState)
{
DBG_FUNC_NAME("CgxDriverIsReadCanceled")
TCgReturnCode rc = ECgOk;
// Check if snap was unconditionally canceled
if (pState->transfer.cancel.request && (pState->transfer.bytes.received > pState->transfer.cancel.onByte))
{
CGCoreReset(CGCORE_ENABLE_CORE);
CgCpuDmaStop(CG_DRIVER_DMA_CHANNEL_READ);
return ECgCanceled;
}
// Check if we have reached the cancel point
if (pState->transfer.cancel.request) {
U32 curDmaCount = 0;
U32 requestedDmaCount = 0;
rc = CgCpuDmaRequestedCount(CG_DRIVER_DMA_CHANNEL_READ, &requestedDmaCount); // how many bursts requested to receive
DBGMSG1("requestedDmaCount = %d", requestedDmaCount);
rc = CgCpuDmaCurCount(CG_DRIVER_DMA_CHANNEL_READ, &curDmaCount); // how many bursts left to receive
DBGMSG1("curDmaCount = %d", curDmaCount);
DBGMSG2("%d >= %d ? ==> canceled", pState->transfer.bytes.received + (requestedDmaCount - curDmaCount) , pState->transfer.cancel.onByte);
if (pState->transfer.bytes.received + (requestedDmaCount - curDmaCount) >= pState->transfer.cancel.onByte)
{
CGCoreReset(CGCORE_ENABLE_CORE);
CgCpuDmaStop(CG_DRIVER_DMA_CHANNEL_READ);
return ECgCanceled;
}
}
return ECgOk;
}
PPDERROR
BUFOBJ_GetString(
PBUFOBJ pBufObj,
PFILEOBJ pFileObj,
PSTR pCh,
BYTE charMask
)
/*++
Routine Description:
Read a character string from a file object into
a buffer object.
Arguments:
pBufObj - pointer to the buffer object
pFileObj - pointer to input file object
pCh - pointer to a character variable
on entry, this contains the first character of the string
on exit, this contains the string terminating character
charMask - mask for determining which characters are
allowed in the string
Return Value:
PPDERR_NONE - string was successfully read
PPDERR_xxx - an error occured
[Note:]
Zero length string is considered an error. On entry,
the buffer object is assumed to be in its initial state.
--*/
{
PPDERROR err = PPDERR_NONE;
if (! IsMaskChar(*pCh, charMask)) {
DBGMSG1(DBG_LEVEL_ERROR, "Illegal character: %c\n", *pCh);
}
// Read characters from the file object until
// we see a terminating character or there is
// an error.
while (IsMaskChar(*pCh, charMask) && err == PPDERR_NONE) {
// Add a character to the buffer object
err = BUFOBJ_AddChar(pBufObj, *pCh);
// Read the next character
if (err == PPDERR_NONE)
err = FILEOBJ_GetChar(pFileObj, pCh);
}
// Null-terminate the buffer object
pBufObj->pBuffer[pBufObj->curlen] = '\0';
// Check for zero length string
return (pBufObj->curlen == 0) ? PPDERR_SYNTAX : err;
}
PPDERROR
PARSEROBJ_ParseEntry(
PPARSEROBJ pParserObj,
PFILEOBJ pFileObj
)
/*++
Routine Description:
Parse one entry out of a PPD file. The parse results
(main keyword, option, translation string, and value)
are stored in the parser object.
Arguments:
pParserObj - Pointer to a parser objct.
pFileObj - Pointer to a file object.
Return Value:
PPDERR_NONE - a PPD entry was successfully parsed
PPDERR_EOF - encountered end-of-file
PPDERR_xxx - other error conditions
--*/
{
PPDERROR err;
char ch;
// Reset the parser object to its initial state
BUFOBJ_Reset(& pParserObj->keyword);
BUFOBJ_Reset(& pParserObj->option);
BUFOBJ_Reset(& pParserObj->xlation);
BUFOBJ_Reset(& pParserObj->value);
pParserObj->valueType = NO_VALUE;
// Parse the main keyword.
err = PARSEROBJ_ParseKeyword(pParserObj, pFileObj, &ch);
// If the main keyword is terminated by a space,
// then skip over any trailing spaces.
while (err == PPDERR_NONE && IsSpace(ch)) {
err = FILEOBJ_GetChar(pFileObj, &ch);
}
if (err != PPDERR_NONE)
return err;
// Decide what to do next based on the first non-space
// character after the main keyword.
if (IsNewline(ch)) {
// If the main keyword is terminated by a newline,
// then the entry only has a main keyword.
return PPDERR_NONE;
}
if (ch != SEPARATOR_CHAR) {
// Look for the option keyword next.
err = PARSEROBJ_ParseOption(pParserObj, pFileObj, &ch);
// If the option keyword is terminated by a space,
// then skip over any trailing spaces.
while (err == PPDERR_NONE && IsSpace(ch)) {
err = FILEOBJ_GetChar(pFileObj, &ch);
}
if (err != PPDERR_NONE)
return err;
// Decide what to do next based on the first non-space
// character after the option keyword.
if (ch == XLATION_CHAR) {
// The option keyword is terminated by a '/'.
// Look for translation string next.
err = PARSEROBJ_ParseXlation(pParserObj, pFileObj, &ch);
if (err != PPDERR_NONE)
return err;
}
// The option keyword and/or translation string must
// be terminated by a ':'. If not, return syntax error.
if (ch != SEPARATOR_CHAR) {
DBGMSG1(DBG_LEVEL_ERROR,
"Missing ':' in *%s entry\n",
BUFOBJ_Buffer(& pParserObj->keyword));
return PPDERR_SYNTAX;
}
}
return PARSEROBJ_ParseValue(pParserObj, pFileObj, &ch);
}
TCgReturnCode CgxDriverExecuteSpecific(
void *pDriver,
TCgxDriverState *pState,
U32 aRequest,
TCgDriverControl *pControl,
TCgDriverStatus *pResults)
{
DBG_FUNC_NAME("CgxDriverExecuteSpecific")
DBGMSG1("aRequest =%x",aRequest);
switch (aRequest) {
case CGX_IOCTL_INIT:
DBGMSG("CGX_IOCTL_INIT");
// This is 1st time initialization, meaning the software is restarted, not resumed, so set the state accordingly.
DBGMSG1("pState = 0x%x", pState);
pState->flags.resume = FALSE;
DBGMSG("after pState->flags.resume = FALSE;");
pResults->rc = CgxDriverInit(pDriver);
break;
case CGX_IOCTL_STOP:
pResults->rc = CgxDriverDestroy(pDriver);
break;
case CGX_IOCTL_READ_REG:
pState->transfer.cancel.request = FALSE;
// Verify register is of the CGX_sat_ram group
pResults->readReg.value = 0;
DBGMSG1("readReg.offset %x ",pControl->readReg.offset);
if ( pControl->readReg.offset >= CGCORE_REG_OFFSET_SAT_RAM && pControl->readReg.offset <= CGCORE_REG_OFFSET_SAT_RAM_LAST )
{
// Write read command to the APB (9 bits of the register offset, with 0x80000000, as the read command)
pResults->rc = CGCORE_WRITE_REG( CGCORE_REG_OFFSET_APB_COMMAND, (0x000001FF & pControl->readReg.offset) | 0x80000000);
// Wait 4 system clocks
CgCpuDelay(100); // TODO : what is the actual period of this wait. Is it 4 system clocks?
// Read data from the APB
if (OK(pResults->rc))
pResults->rc = CGCORE_READ_REG( CGCORE_REG_OFFSET_APB_DATA, &pResults->readReg.value);
}
else
{
// It is not part of the CGX_sat_ram. Read register normaly, via the APB
pResults->rc = CGCORE_READ_REG( pControl->readReg.offset, &pResults->readReg.value);
}
break;
case CGX_IOCTL_WRITE_REG:
pState->transfer.cancel.request = FALSE;
// Write to CGsnap register
pResults->rc = CGCORE_WRITE_REG( pControl->writeReg.offset, pControl->writeReg.value);
// DBGMSG2("CGX_IOCTL_WRITE_REG *0x%08X = 0x%08X", CGCORE_BASE_ADDR_VA + pControl->writeReg.offset, pControl->writeReg.value);
break;
case CGX_IOCTL_PREPARE_RECEIVE:
DBGMSG("CGX_IOCTL_PREPARE_RECEIVE");
// Prepare driver for massive data receive (snap)
pState->transfer.cancel.request = FALSE;
pResults->rc = CgxDriverPrepareRecieve(pState, pControl->read.buf, pControl->read.bufPhys,
pState->buffer.length, pControl->read.alignedLength, pControl->read.blockLength,
pControl->read.byteOrder);
break;
case CGX_IOCTL_STATUS:
pResults->rc = pState->constructionRc;
break;
case CGX_IOCTL_RESUME_CLEAR:
DBGMSG("CGX_IOCTL_RESUME_CLEAR!");
pState->flags.resume = FALSE;
pState->transfer.cancel.request = FALSE;
break;
case CGX_IOCTL_RESET:
DBGMSG1("CGX_IOCTL_RESET level %d", pControl->reset.resetLevel);
pState->transfer.cancel.request = FALSE;
switch( pControl->reset.resetLevel )
{
case 0: // Full reset
#if 0
if (OK(pResults->rc)) pResults->rc = CgCpuIPMasterResetOn();
if (OK(pResults->rc)) pResults->rc = CgCpuDelay(CGCORE_RESET_DELAY);
if (OK(pResults->rc)) pResults->rc = CgCpuIPMasterResetClear();
#endif
if (OK(pResults->rc)) pResults->rc = CGCORE_WRITE_REG( CGCORE_REG_OFFSET_CORE_RESETS, CGCORE_CORE_RESETS_ENABLE);
break;
case 1: // Semi reset
if (OK(pResults->rc)) pResults->rc = CGCoreReset(CGCORE_ENABLE_CORE);
#ifdef CGCORE_ACCESS_VIA_SPI
init_spi_block_var();
#endif
break;
case 2: // CPU reset
break;
default : // Semi reset, also.
if (OK(pResults->rc)) pResults->rc = CGCoreReset(CGCORE_ENABLE_CORE);
break;
}
pResults->rc = CgCpuDmaStop(CG_DRIVER_DMA_CHANNEL_READ);
break;
case CGX_IOCTL_COUNTER_RESET:
DBGMSG("CGX_IOCTL_COUNTER_RESET!");
pResults->rc = CgCpuDmaStop(CG_DRIVER_DMA_CHANNEL_READ);
if (OK(pResults->rc)) pResults->rc = CGCoreReset(CGCORE_ENABLE_TCXO);
break;
case CGX_IOCTL_POWER_DOWN:
DBGMSG("CGX_IOCTL_POWER_DOWN!");
flag_power_up = 0;
pResults->rc = CgxDriverPowerDown();
if (OK(pResults->rc)) pResults->rc = CgxDriverRFPowerDown();
break;
case CGX_IOCTL_POWER_UP:
flag_power_up = 1;
pState->transfer.cancel.request = FALSE;
pResults->rc = CgxDriverPowerUp();
if (OK(pResults->rc)) pResults->rc = CgxDriverRFPowerUp();
break;
case CGX_IOCTL_POWER_OFF :
pResults->rc = CgxDriverPowerOff();
break;
case CGX_IOCTL_POWER_ON :
pResults->rc = CgxDriverPowerOn();
break;
case CGX_IOCTL_GPIO_SET:
//DBGMSG2("CGX_IOCTL_GPIO_SET 0x%08X = %d", pControl->GPIO.code, pControl->GPIO.out);
if (pControl->GPIO.out)
pResults->rc = CgCpuGpioSet(pControl->GPIO.code);
else
pResults->rc = CgCpuGpioReset(pControl->GPIO.code);
//rc = CgxDriverDebugGpio((int)pControl->GPIO.code, (int)pControl->GPIO.out);
break;
case CGX_IOCTL_GPIO_GET:
//DBGMSG1("CGX_IOCTL_GPIO_GET 0x%08X", pControl->GPIO.code);
//pResults->GPIO.in = 0x5a5a;
//DBGMSG2("CGX_IOCTL_GPIO_GET before 0x%08X=0x%08X", pControl->GPIO.code, pResults->GPIO.in)
pResults->rc = CgCpuGpioGet(pControl->GPIO.code, (int *)&(pResults->GPIO.val));
pResults->GPIO.code = pControl->GPIO.code;
//DBGMSG2("CGX_IOCTL_GPIO_GET after 0x%08X=0x%08X", pControl->GPIO.code, pResults->GPIO.in)
//rc = CgxDriverDebugGpioRead((int)pResults->GPIO.code, (int*)&pResults->GPIO.in);
break;
case CGX_IOCTL_GET_VERSION:
memcpy(pResults->version.buildVersion, gCgDriverVersion.buildVersion, sizeof(pResults->version.buildVersion));
memcpy(pResults->version.buildMode, gCgDriverVersion.buildMode, sizeof(pResults->version.buildNumber));
memcpy(pResults->version.buildNumber, gCgDriverVersion.buildNumber, sizeof(pResults->version.buildNumber));
memcpy(pResults->version.buildTime, gCgDriverVersion.buildTime, sizeof(pResults->version.buildTime));
memcpy(pResults->version.buildDate, gCgDriverVersion.buildDate, sizeof(pResults->version.buildDate));
break;
case CGX_IOCTL_CANCEL_RECEIVE:
DBGMSG1("Request cancel on byte %d", pControl->cancel.onByteCount);
// set up receive abort flag.
// the flag is cleared be prepare receive command
if (pControl->cancel.onByteCount > (U32)CgxDriverSnapLengthExtraBytes) {
pState->transfer.cancel.onByte = pControl->cancel.onByteCount - CgxDriverSnapLengthExtraBytes;
CG_MATH_ALIGNMENT((pState->transfer.cancel.onByte), NUMBER_1K);
DBGMSG1("cancel on Byte: 0x%08X", pState->transfer.cancel.onByte);
}
else {
pState->transfer.cancel.onByte = 0; // Cancel snap req immediately
}
pState->transfer.cancel.request = TRUE;
DBGMSG1("cancel on Byte: 0x%08X", ((pState->transfer.cancel.onByte / 16) & 0x00FFFFF) | 0x0F000000);
CGCORE_WRITE_REG( 0x30, ((pState->transfer.cancel.onByte / 16) & 0x00FFFFF) | 0x0F000000);
CGCORE_WRITE_REG( 0x34, 0);
// check if cancel point passed
pResults->rc = CgxDriverIsReadCanceled(pState);
if ((pControl->cancel.onByteCount == 0) || // Cancel snap req immediately
(!OK(pResults->rc) && pState->flags.wait)) {// release a waiting thread, if any
CGCoreReset(CGCORE_ENABLE_CORE);
CgCpuDmaStop(CG_DRIVER_DMA_CHANNEL_READ);
CgxDriverDataReadyInterruptHandler(pDriver, pState);
}
break;
case CGX_IOCTL_ALLOC_BUFF:
DBGMSG1("CGX_IOCTL_ALLOC_BUFF, pControl->alloc.length=%d", pControl->alloc.length);
// pControl->alloc.length = 1 *1024 * 1024; // 1M
pResults->rc = CgxDriverAllocInternalBuff(pDriver, pControl->alloc.length,
(void**)&(pResults->buffer.bufferPhysAddr), pControl->alloc.processId);
DBGMSG1("alloc p =0x%08X", pState->buffer.virtAddr);
if (OK(pResults->rc)) {
pResults->buffer.size = pControl->alloc.length;
pResults->buffer.bufferAppVirtAddr = pState->buffer.virtAddr;
}
break;
case CGX_IOCTL_FREE_BUFF:
DBGMSG("CGX_IOCTL_FREE_BUFF");
pResults->rc = CgxDriverFreeInternalBuff(pDriver, pControl->alloc.processId);
break;
case CGX_IOCTL_READ_MEM:
DBGMSG("CGX_IOCTL_READ_MEM");
pState->transfer.cancel.request = FALSE;
DBGMSG1("read from 0x%08X", pControl->readReg.offset);
pResults->rc = CgxCpuReadMemory(pControl->readReg.offset, 0, &pResults->readReg.value);
break;
case CGX_IOCTL_CPU_REVISION:
pResults->rc = CgCpuRevision(pResults->cpuRevision.revisionCode); // TODO - fix CgCpuRevision so it reads from the right address
break;
case CGX_IOCTL_TCXO_ENABLE:
DBGMSG("CGX_IOCTL_TCXO_ENABLE");
pResults->rc = CgxDriverTcxoControl(pControl->tcxoControl.enable);
break;
case CGX_IOCTL_RF_WRITE_CONTROL:
DBGMSG("CGX_IOCTL_RF_WRITE_CONTROL");
pResults->rc = CgCpuRFControlWriteByte(pControl->writeReg.value);
break;
default:
return ECgGeneralFailure;
}
return ECgOk;
}
TCgReturnCode CgxDriverPrepareRecieve(
TCgxDriverState *pState,
unsigned char *apBuf,
U32 aBufPhys,
U32 aBufSize,
unsigned long aLength,
unsigned long aBlockLength,
TCgByteOrder aByteOrder)
{
DBG_FUNC_NAME("CgxDriverPrepareRecieve")
TCgReturnCode rc = ECgOk;
U32 blockIndex = 0;
U32 chunksInBlock = 0;
U32 chunkSize = 0;
U32 length = aLength + CgxDriverSnapLengthExtraBytes; // Potential patch
U32 numOfBlocksInBuffer = 0;
memset(gChunksList,0,sizeof(TCgCpuDmaTask)*MAX_DMA_TRANSFER_TASKS);
DBGMSG1("buffer v-address = 0x%x", apBuf);
DBGMSG1("start address value = 0x%x", *((U32*)apBuf) );
DBGMSG1("dest address value = 0x%x", *((U32*)apBuf + 128) );
pState->transfer.blockSize = ((aBlockLength == 0) || (length < aBlockLength)) ? length : aBlockLength;
/*bxd modify for not limted to 512k Bytes each block*/
chunkSize = pState->transfer.blockSize;
//chunkSize = MIN(MAX_DMA_CHUNK_SIZE, pState->transfer.blockSize);
chunksInBlock = pState->transfer.blockSize / chunkSize;
DBGMSG3("Requested %d bytes, Block=(%d bytes,%d chunks)", length, pState->transfer.blockSize, chunksInBlock);
DBGMSG1("Maximum DMA chunk size is set to %d bytes", chunkSize);
pState->flags.overrun = FALSE;
pState->transfer.cancel.request = FALSE;
pState->transfer.cancel.onByte = 0;
pState->transfer.cancel.onChunk = 0;
pState->transfer.done = 0;
pState->transfer.originalBuffer = apBuf;
pState->transfer.bufferPhys = pState->buffer.physAddr;
pState->transfer.byteOrder = aByteOrder;
pState->transfer.bytes.required = length;
pState->transfer.bytes.received = 0;
pState->transfer.blocks.required = (length + pState->transfer.blockSize - 1) / pState->transfer.blockSize;
#ifdef CGCORE_ACCESS_VIA_SPI
block_num = pState->transfer.blocks.required;
#endif
DBGMSG1("%d blocks required", pState->transfer.blocks.required);
pState->transfer.lastBlockSize = length - (pState->transfer.blocks.required - 1) * pState->transfer.blockSize;
DBGMSG1("last block size: %d bytes", pState->transfer.lastBlockSize);
pState->transfer.blocks.received = 0;
pState->transfer.chunks.required = 0;
pState->transfer.chunks.received = 0;
pState->transfer.chunks.active = 0;
// split snap to blocks
//////////////////////////////////////////////////////////////////////////
if (pState->transfer.blocks.required * chunksInBlock > MAX_DMA_TRANSFER_TASKS) {
DBGMSG2("ERROR! too many chunks! %d > %d", pState->transfer.blocks.required * chunksInBlock, MAX_DMA_TRANSFER_TASKS);
return ECgErrMemory;
}
numOfBlocksInBuffer = aBufSize / pState->transfer.blockSize;
DBGMSG2("aBufSize = %d, blockSize = %d", aBufSize, pState->transfer.blockSize );
for(blockIndex = 0; blockIndex < pState->transfer.blocks.required; blockIndex++)
{
// Init the snap's blocks' offsets
pState->transfer.bufferOffset[blockIndex] = pState->transfer.blockSize * (blockIndex % numOfBlocksInBuffer); // roll-over to start of buffer,
// if we reached end of buffer.
//DBGMSG2("buffer[%d] = 0x%08X", blockIndex, pState->transfer.bufferPhys + pState->transfer.bufferOffset[blockIndex])
}
// split blocks to chunks
//////////////////////////////////////////////////////////////////////////
for(blockIndex = 0; blockIndex < pState->transfer.blocks.required; blockIndex++) {
U32 chunkIndex = 0;
U32 more, dest;
more = (blockIndex == (pState->transfer.blocks.required-1)) ? pState->transfer.lastBlockSize : pState->transfer.blockSize;
dest = pState->transfer.bufferPhys + pState->transfer.bufferOffset[blockIndex];
// DBGMSG4("Block %02d/%02d: % 6d bytes @ 0x%08X", blockIndex + 1, pState->transfer.blocks.required,
for(chunkIndex = 0; chunkIndex < chunksInBlock-1; chunkIndex++) {
U32 size = MIN(more, chunkSize);
if ((more - size) < chunkSize)
break;
gChunksList[pState->transfer.chunks.required].address = dest;
gChunksList[pState->transfer.chunks.required].length = size;
more -= size;
// DBGMSG5("chunk %02d/%02d in block: length %d bytes @ 0x%08X (%d more)", chunkIndex + 1, chunksInBlock,
dest += size;
pState->transfer.chunks.required++;
}
// last chunk
gChunksList[pState->transfer.chunks.required].address = dest;
gChunksList[pState->transfer.chunks.required].length = more;
DBGMSG3("last chunk out of %02d in block: % 6d bytes @ 0x%08X", chunksInBlock, more, dest);
pState->transfer.chunks.required++;
}
DBGMSG1("%d chunks required", pState->transfer.chunks.required);
if (length > pState->transfer.blockSize * pState->transfer.blocks.required) {
// there are leftovers
U32 more = length - pState->transfer.blockSize * pState->transfer.blocks.required;
U32 dest = pState->transfer.bufferPhys + pState->transfer.bufferOffset[pState->transfer.blocks.required];
DBGMSG4("Extra Block % 2d/% 2d: % 6d bytes @ 0x%08X", pState->transfer.blocks.required, pState->transfer.blocks.required, more, dest);
for (; (more > 0) && (pState->transfer.chunks.required < MAX_DMA_TRANSFER_TASKS); pState->transfer.chunks.required++) {
U32 size = MIN(more, chunkSize);
gChunksList[pState->transfer.chunks.required].address = dest;
gChunksList[pState->transfer.chunks.required].length = size;
more -= size;
dest += size;
DBGMSG4("chunk % 4d: % 4d bytes @ 0x%08X (%d bytes left)", pState->transfer.chunks.required + 1, size, dest, more);
}
DBGMSG1("%d chunks required", pState->transfer.chunks.required);
}
// setup 1st DMA chunk
#ifndef CGCORE_ACCESS_VIA_SPI
rc = CgCpuDmaSetupFromGps(gChunksList, pState->transfer.chunks.required, CG_DRIVER_DMA_CHANNEL_READ, CGCORE_BASE_ADDR + 0x00000070);
rc = CgCpuDmaStart(CG_DRIVER_DMA_CHANNEL_READ);
#else
// rc =CgxCpuSpiReadData();
#endif
return rc;
}
VOID
SetResolution(
PDEVDATA pdev,
DWORD res,
WORD restype)
/*++
Routine Description:
Generate commands to set printer resolution.
Arguments:
pdev pointer to device data
res desired resolution
bPJL TRUE this is called at the beginning of a job
FALSE if this called during the setup section
Return Value:
NONE
--*/
{
HPPD hppd = pdev->hppd;
PRESOPTION pResOption;
// We only need to do something when the requested
// resolution type matches what the printer can do
if (restype != hppd->wResType)
return;
// Check if the desired resolution is supported
pResOption = PpdFindResolution(hppd, res);
// Ignore if the desired resolution is not found
if (pResOption == NULL) {
DBGMSG1(DBG_LEVEL_TERSE,
"No invocation string for resolution option: %d.\n", res);
return;
}
switch (restype) {
case RESTYPE_NORMAL: // Use normal PS code
if (pResOption->pInvocation == NULL) {
DBGMSG(DBG_LEVEL_ERROR, "Failed to set resolution.");
} else {
DscBeginFeature(pdev, "Resolution ");
psprintf(pdev, "%d\n", res);
psputs(pdev, pResOption->pInvocation);
DscEndFeature(pdev);
}
break;
case RESTYPE_JCL: // Use JCL code
if (! PpdSupportsProtocol(hppd,PROTOCOL_PJL) ||
pResOption->pJclCode == NULL)
{
DBGMSG(DBG_LEVEL_ERROR,
"Cannot set resolution using PJL commands.\n");
} else {
psputs(pdev, pResOption->pJclCode);
}
break;
case RESTYPE_EXITSERVER: // Use exitserver code
if (pResOption->pSetResCode == NULL) {
DBGMSG(DBG_LEVEL_ERROR, "Failed to set resolution.");
} else {
PSTR password = hppd->pPassword ? hppd->pPassword : "******";
psputs(pdev, "%%BeginExitServer: ");
psputs(pdev, password);
psprintf(pdev, "\n%%%%Resolution: %d\n", res);
psputs(pdev, password);
psputs(pdev, "\n");
psputs(pdev, pResOption->pSetResCode);
psputs(pdev, "\n%%EndExitServer\n");
}
break;
}
}
PINPUTSLOT
MatchFormToTray(
PDEVDATA pdev,
BOOL *pbManual
)
/*++
Routine Description:
description-of-function
Arguments:
pdev Pointer to DEVDATA structure
pbManual Pointer to a boolean variable for indicating
whether the form is in the manual feed tray
Return Value:
Pointer to input slot object. NULL if the form is not assigned
to any input slot or if it's in the manual feed tray.
--*/
{
FORM_TRAY_TABLE pFormTrayTable, pNextEntry;
PWSTR pFormName, pSlotName, pPrinterForm;
BOOL IsDefTray;
PINPUTSLOT pInputSlot = NULL;
PWSTR pManualSlotName;
// Get the name of manual feed slot
pManualSlotName = STDSTR_SLOT_MANUAL;
*pbManual = FALSE;
// Read form-to-tray assignment table from registry
pNextEntry = pFormTrayTable = CurrentFormTrayTable(pdev->hPrinter);
if (pFormTrayTable == NULL) {
DBGMSG(DBG_LEVEL_WARNING,
"Failed to read form-to-tray assignment table.\n");
} else {
while (*pNextEntry != NUL) {
// Extract information from the current table entry
// and move on to the next entry
pNextEntry = EnumFormTrayTable(
pNextEntry,
& pSlotName,
& pFormName,
& pPrinterForm,
& IsDefTray);
// If a form is in more than one tray, then IsDefTray
// may or may not be set. But if form is in only one
// tray, then IsDefTray will always be set.
if (IsDefTray && wcscmp(pFormName, pdev->CurForm.FormName) == EQUAL_STRING) {
if (wcscmp(pSlotName, pManualSlotName) == EQUAL_STRING) {
*pbManual = TRUE;
} else {
CHAR SlotName[MAX_OPTION_NAME];
// Find the INPUTSLOT object corresponding
// to the input slot name
CopyUnicode2Str(SlotName, pSlotName, MAX_OPTION_NAME);
pInputSlot = PpdFindInputSlot(pdev->hppd, SlotName);
if (pInputSlot == NULL) {
DBGMSG1(DBG_LEVEL_WARNING,
"No such input slot: %ws.\n",
pSlotName);
}
}
break;
}
}
// Free the memory occupied by form-to-tray assignment table
FreeFormTrayTable(pFormTrayTable);
}
return pInputSlot;
}
VOID
PsSelectPrinterFeatures(
PDEVDATA pdev,
WORD section
)
/*++
Routine Description:
Select printer specific feature to appear in a
given section.
Arguments:
pdev - Pointer to our DEVDATA structure
section - DSC section we're currently in
Return Value:
NONE
--*/
{
WORD index;
PFEATUREDATA pFeatureData;
PUIGROUP pUiGroup;
PUIOPTION pUiOption;
//
// Prepare data for handling printer specific feature if it's not done already.
//
if (!pdev->pFeatureData && !PrepareFeatureData(pdev)) {
DBGERRMSG("PrepareFeatureData");
return;
}
//
// For each requested feature, check if it should be sent to
// the printer in the current DSC section.
//
for (index = 0, pFeatureData = pdev->pFeatureData;
index < pdev->cSelectedFeature;
index ++, pFeatureData++)
{
//
// Find the UIOPTION object corresponding to the requested feature/selection.
//
// HACK: PageSize feature is handled differently here because it involves
// lots of legacy stuff which we don't want to touch at this point.
//
if (! (pFeatureData->section & section))
continue;
if (pdev->hppd->pPageSizes &&
pdev->hppd->pPageSizes->featureIndex == pFeatureData->feature)
{
PsSelectFormAndTray(pdev);
} else if (PpdFindFeatureSelection(
pdev->hppd,
pFeatureData->feature,
pFeatureData->option,
&pUiGroup,
&pUiOption))
{
DBGMSG1(DBG_LEVEL_VERBOSE, "Feature: %s\n", pUiGroup->pName);
DBGMSG1(DBG_LEVEL_VERBOSE, "Selection: %s\n", pUiOption->pName);
//
// If we're not in JCLSetup section, then enclose the feature
// invocation in a mark/cleartomark pair.
//
if (section != ODS_JCLSETUP) {
DscBeginFeature(pdev, pUiGroup->pName);
psprintf(pdev, " %s\n", pUiOption->pName);
}
if (pUiOption->pInvocation)
psputs(pdev, pUiOption->pInvocation);
if (section != ODS_JCLSETUP)
DscEndFeature(pdev);
}
}
}
int main(void)
{
SetupHardware();
setLed(RED);
state = init;
switch_port(0);
DBGMSG1("Ready.");
// Copy the hub descriptor into ram, vusb's
// usbFunctionSetup() callback can't handle stuff
// from FLASH
memcpy_P(HUB_Hub_Descriptor_ram, HUB_Hub_Descriptor, sizeof(HUB_Hub_Descriptor));
for (;;)
{
if (port_cur == 0)
HUB_Task();
if (port_cur == 5)
JIG_Task();
usbPoll();
// connect 1
if (state == hub_ready && expire == 0)
{
DBG1(0x00, "\x1", 1);
setLed(NONE);
connect_port(1);
state = p1_wait_reset;
}
if (state == p1_wait_reset && last_port_reset_clear == 1)
{
DBG1(0x00, "\x2", 1);
setLed(RED);
switch_port(1);
state = p1_wait_enumerate;
}
// connect 2
if (state == p1_ready && expire == 0)
{
DBG1(0x00, "\x3", 1);
setLed(NONE);
switch_port(0);
connect_port(2);
state = p2_wait_reset;
}
if (state == p2_wait_reset && last_port_reset_clear == 2)
{
DBG1(0x00, "\x4", 1);
setLed(RED);
switch_port(2);
state = p2_wait_enumerate;
}
// connect 3
if (state == p2_ready && expire == 0)
{
DBG1(0x00, "\x5", 1);
setLed(NONE);
switch_port(0);
connect_port(3);
state = p3_wait_reset;
}
if (state == p3_wait_reset && last_port_reset_clear == 3)
{
DBG1(0x00, "\x6", 1);
setLed(RED);
switch_port(3);
state = p3_wait_enumerate;
}
// disconnect 2
if (state == p3_ready && expire == 0)
{
DBG1(0x00, "\x7", 1);
setLed(NONE);
switch_port(0);
disconnect_port(2);
state = p2_wait_disconnect;
}
if (state == p2_wait_disconnect && last_port_conn_clear == 2)
{
DBG1(0x00, "\x8", 1);
setLed(RED);
state = p4_wait_connect;
expire = 15;
}
// connect 4
if (state == p4_wait_connect && expire == 0)
{
DBG1(0x00, "\x9", 1);
setLed(NONE);
connect_port(4);
state = p4_wait_reset;
}
if (state == p4_wait_reset && last_port_reset_clear == 4)
{
DBG1(0x00, "\x10", 1);
setLed(RED);
switch_port(4);
state = p4_wait_enumerate;
}
// connect 5
if (state == p4_ready && expire == 0)
{
DBG1(0x00, "\x11", 1);
setLed(NONE);
switch_port(0);
/* When first connecting port 5, we need to
have the wrong data toggle for the PS3 to
respond */
hub_int_force_data0 = 1;
connect_port(5);
state = p5_wait_reset;
}
if (state == p5_wait_reset && last_port_reset_clear == 5)
{
DBG1(0x00, "\x12", 1);
setLed(RED);
switch_port(5);
state = p5_wait_enumerate;
}
// disconnect 3
if (state == p5_responded && expire == 0)
{
DBG1(0x00, "\x13", 1);
setLed(NONE);
switch_port(0);
/* Need wrong data toggle again */
hub_int_force_data0 = 1;
disconnect_port(3);
state = p3_wait_disconnect;
}
if (state == p3_wait_disconnect && last_port_conn_clear == 3)
{
DBG1(0x00, "\x14", 1);
setLed(RED);
state = p3_disconnected;
expire = 45;
}
// disconnect 5
if (state == p3_disconnected && expire == 0)
{
DBG1(0x00, "\x15", 1);
setLed(NONE);
switch_port(0);
disconnect_port(5);
state = p5_wait_disconnect;
}
if (state == p5_wait_disconnect && last_port_conn_clear == 5)
{
DBG1(0x00, "\x16", 1);
setLed(RED);
state = p5_disconnected;
expire = 20;
}
// disconnect 4
if (state == p5_disconnected && expire == 0)
{
DBG1(0x00, "\x17", 1);
setLed(NONE);
switch_port(0);
disconnect_port(4);
state = p4_wait_disconnect;
}
if (state == p4_wait_disconnect && last_port_conn_clear == 4)
{
DBG1(0x00, "\x18", 1);
setLed(RED);
state = p4_disconnected;
expire = 20;
}
// disconnect 1
if (state == p4_disconnected && expire == 0)
{
DBG1(0x00, "\x19", 1);
setLed(NONE);
switch_port(0);
disconnect_port(1);
state = p1_wait_disconnect;
}
if (state == p1_wait_disconnect && last_port_conn_clear == 1)
{
DBG1(0x00, "\x20", 1);
setLed(RED);
state = p1_disconnected;
expire = 20;
}
// connect 6
if (state == p1_disconnected && expire == 0)
{
DBG1(0x00, "\x21", 1);
setLed(NONE);
switch_port(0);
connect_port(6);
state = p6_wait_reset;
}
if (state == p6_wait_reset && last_port_reset_clear == 6)
{
DBG1(0x00, "\x22", 1);
setLed(RED);
switch_port(6);
state = p6_wait_enumerate;
}
// done
if (state == done)
{
setLed(GREEN);
}
}
}
