u32 ddl_fw_init(struct ddl_buf_addr *dram_base)
{

	u8 *dest_addr;
/*HTC_START*/
	pr_info("[VID] enter ddl_fw_init()");
	dest_addr = DDL_GET_ALIGNED_VITUAL(*dram_base);
	if (vidc_video_codec_fw_size > dram_base->buffer_size ||
		!vidc_video_codec_fw) {
			pr_info("[VID] ddl_fw_init() failed");
			return false;
	}
	pr_info("[VID] FW Addr / FW Size : %x/%d", (u32)vidc_video_codec_fw, vidc_video_codec_fw_size);
	memset(dest_addr, 0, vidc_video_codec_fw_size);
	memcpy(dest_addr, vidc_video_codec_fw, vidc_video_codec_fw_size);
	msleep(10);
	if (memcmp(dest_addr, vidc_video_codec_fw,
		vidc_video_codec_fw_size)) {
		pr_err("[VID] SMI MEMORY issue firmware is not good\n");
		return false;
	}
/*HTC_END*/
	pr_info("[VID] Firmware in SMI is good continue\n");
#ifdef DDL_FW_CHANGE_ENDIAN
	pr_info("[VID] before ddl_fw_change_endian()");
	ddl_fw_change_endian(dest_addr, vidc_video_codec_fw_size);
	pr_info("[VID] leave ddl_fw_init()");
#endif
	return true;
}
Ejemplo n.º 2
0
u32 ddl_fw_init(struct ddl_buf_addr *dram_base)
{
	u8 *dest_addr;
	dest_addr = DDL_GET_ALIGNED_VITUAL(*dram_base);
	DDL_MSG_LOW("FW Addr / FW Size : %x/%d", (u32)vidc_video_codec_fw,
		vidc_video_codec_fw_size);
	if (res_trk_check_for_sec_session() && res_trk_is_cp_enabled()) {
		if (res_trk_enable_footswitch()) {
			pr_err("Failed to enable footswitch");
			return false;
		}
		if (res_trk_enable_iommu_clocks()) {
			res_trk_disable_footswitch();
			pr_err("Failed to enable iommu clocks\n");
			return false;
		}
		dram_base->pil_cookie = pil_get("vidc");
		if (res_trk_disable_iommu_clocks())
			pr_err("Failed to disable iommu clocks\n");
		if (IS_ERR_OR_NULL(dram_base->pil_cookie)) {
			res_trk_disable_footswitch();
			pr_err("pil_get failed\n");
			return false;
		}
	} else {
		if (vidc_video_codec_fw_size > dram_base->buffer_size ||
				!vidc_video_codec_fw)
			return false;
		memcpy(dest_addr, vidc_video_codec_fw,
				vidc_video_codec_fw_size);
	}
	return true;
}
u32 ddl_fw_init(struct ddl_buf_addr *dram_base)
{

	u8 *dest_addr;

	dest_addr = DDL_GET_ALIGNED_VITUAL(*dram_base);
	if (vidc_video_codec_fw_size > dram_base->buffer_size ||
		!vidc_video_codec_fw)
		return false;
	DDL_MSG_LOW("FW Addr / FW Size : %x/%d", (u32)vidc_video_codec_fw,
		vidc_video_codec_fw_size);
	memcpy(dest_addr, vidc_video_codec_fw,
		vidc_video_codec_fw_size);
	return true;
}
Ejemplo n.º 4
0
u32 ddl_fw_init(struct ddl_buf_addr *dram_base)
{

	u8 *dest_addr;

	dest_addr = DDL_GET_ALIGNED_VITUAL(*dram_base);
	if (vidc_video_codec_fw_size > dram_base->buffer_size ||
		!vidc_video_codec_fw)
		return false;
	DDL_MSG_LOW("FW Addr / FW Size : %x/%d", (u32)vidc_video_codec_fw,
		vidc_video_codec_fw_size);
	memcpy(dest_addr, vidc_video_codec_fw,
		vidc_video_codec_fw_size);
#ifdef DDL_FW_CHANGE_ENDIAN
	ddl_fw_change_endian(dest_addr, vidc_video_codec_fw_size);
#endif
	return true;
}