Ejemplo n.º 1
0
static void mutex_dump_analysis(void)
{
    int i=0;
    int j=0;
    char mutex_module[512]={'\0'};
    char * p = NULL;
    int len = 0;
    DDPDUMP("==DISP Mutex Analysis==\n");
    for (i = 0; i < 5; i++)
    {
        p = mutex_module;
        len = 0;
        if( DISP_REG_GET(DISP_REG_CONFIG_MUTEX_MOD(i))!=0 &&
           ((DISP_REG_GET(DISP_REG_CONFIG_MUTEX_EN(i)+0x20*i)==1 &&
            DISP_REG_GET(DISP_REG_CONFIG_MUTEX_SOF(i)+0x20*i)!=SOF_SINGLE ) ||
            DISP_REG_GET(DISP_REG_CONFIG_MUTEX_SOF(i)+0x20*i)==SOF_SINGLE))
        {
          len = sprintf(p,"MUTEX%d :mode=%s,module=(",
            i, ddp_mutex_sof_to_string( DISP_REG_GET(DISP_REG_CONFIG_MUTEX_SOF(i))));
          p += len;
          for(j=11;j<=25;j++)
          {
              if((DISP_REG_GET(DISP_REG_CONFIG_MUTEX_MOD(i))>>j)&0x1)
              {
                 len = sprintf(p,"%s,", ddp_get_mutex_module_name(j));
                 p += len;
              }
          }
          DDPDUMP("%s)\n",mutex_module);
        }
    }
Ejemplo n.º 2
0
void rdma_dump_analysis(DISP_MODULE_ENUM module)
{
    unsigned int idx = rdma_index(module);
    DDPDUMP("==DISP RDMA%d ANALYSIS==\n", idx); 
    DDPDUMP("rdma%d: en=%d, memory mode=%d, w=%d, h=%d, pitch=%d, addr=0x%x, fmt=%s, fifo_min=%d, \
    in_p_cnt=%d, in_l_cnt=%d, out_p_cnt=%d, out_l_cnt=%d, rdma_start_time=%lld ns,rdma_end_time=%lld ns\n",

        idx,
        DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_RDMA_INDEX_OFFSET*idx)&0x1,
        (DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_RDMA_INDEX_OFFSET*idx)&0x2)?1:0,
        DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_RDMA_INDEX_OFFSET*idx)&0xfff,
        DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_RDMA_INDEX_OFFSET*idx)&0xfffff,
        DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH+DISP_RDMA_INDEX_OFFSET*idx), 
        DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_RDMA_INDEX_OFFSET*idx),
        rdma_intput_format_name(
            (DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_RDMA_INDEX_OFFSET*idx)>>4)&0xf,
            (DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_RDMA_INDEX_OFFSET*idx)>>8)&0x1
            ),
        DISP_REG_GET(DISP_REG_RDMA_FIFO_LOG+DISP_RDMA_INDEX_OFFSET*idx),
        DISP_REG_GET(DISP_REG_RDMA_IN_P_CNT+DISP_RDMA_INDEX_OFFSET*idx),
        DISP_REG_GET(DISP_REG_RDMA_IN_LINE_CNT+DISP_RDMA_INDEX_OFFSET*idx),
        DISP_REG_GET(DISP_REG_RDMA_OUT_P_CNT+DISP_RDMA_INDEX_OFFSET*idx),
        DISP_REG_GET(DISP_REG_RDMA_OUT_LINE_CNT+DISP_RDMA_INDEX_OFFSET*idx),
        rdma_start_time[idx],
        rdma_end_time[idx]
    );
    DDPDUMP("irq cnt: start=%d, end=%d, underflow=%d, targetline=%d \n", 
      rdma_start_irq_cnt[idx], rdma_done_irq_cnt[idx], rdma_underflow_irq_cnt[idx], rdma_targetline_irq_cnt[idx]);
      
    return ;
}
Ejemplo n.º 3
0
static void ddp_check_mutex_l(int mutex_id, int* module_list, DDP_MODE ddp_mode)
{
    int i=0;
    kal_uint32 real_value = 0;
    kal_uint32 expect_value = 0;
    kal_uint32 real_sof  = 0;
    MUTEX_SOF  expect_sof  = SOF_SINGLE;
    int module_num = ddp_get_module_num_l(module_list);
    if(mutex_id < DISP_MUTEX_DDP_FIRST || mutex_id > DISP_MUTEX_DDP_LAST)
    {
        DDPDUMP("error:check mutex fail:exceed mutex max (0 ~ %d)\n",DISP_MUTEX_DDP_LAST);
        return;
    }
    real_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_MOD(mutex_id));
    for(i = 0 ; i < module_num ; i++)
    {
        if(module_mutex_map[module_list[i]].bit != -1)
            expect_value |= (1 << module_mutex_map[module_list[i]].bit);
    }
    if( expect_value != real_value )
    {
       DDPDUMP("error:mutex %d error: expect 0x%x, real 0x%x\n",mutex_id,expect_value,real_value);
    }
    real_sof  = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_SOF(mutex_id));
    expect_sof = ddp_get_mutex_sof(module_list[module_num-1],ddp_mode);
    if((kal_uint32)expect_sof != real_sof)
    {
       DDPDUMP("error:mutex %d sof error: expect %s, real %s\n", mutex_id,
             ddp_get_mutex_sof_name(expect_sof),
             ddp_get_mutex_sof_name((MUTEX_SOF)real_sof));
    }
}
Ejemplo n.º 4
0
void wdma_dump_reg(DISP_MODULE_ENUM module)
{
    unsigned int idx = wdma_index(module);
    unsigned int off_sft = idx*DISP_WDMA_INDEX_OFFSET;
    DDPDUMP("==DISP WDMA%d REGS==\n", idx);

	DDPDUMP("WDMA:0x000=0x%08x,0x004=0x%08x,0x008=0x%08x,0x00c=0x%08x\n",
	                        DISP_REG_GET(DISP_REG_WDMA_INTEN+off_sft),
	                        DISP_REG_GET(DISP_REG_WDMA_INTSTA+off_sft),
	                        DISP_REG_GET(DISP_REG_WDMA_EN+off_sft),
	                        DISP_REG_GET(DISP_REG_WDMA_RST+off_sft));
	
	DDPDUMP("WDMA:0x010=0x%08x,0x014=0x%08x,0x018=0x%08x,0x01c=0x%08x\n",
                        DISP_REG_GET(DISP_REG_WDMA_SMI_CON+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_CFG+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_SRC_SIZE+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_CLIP_SIZE+off_sft));
    
	DDPDUMP("WDMA:0x020=0x%08x,0x028=0x%08x,0x02c=0x%08x,0x038=0x%08x\n",
                        DISP_REG_GET(DISP_REG_WDMA_CLIP_COORD+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_DST_W_IN_BYTE+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_ALPHA+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_BUF_CON1+off_sft));    

	DDPDUMP("WDMA:0x03c=0x%08x,0x058=0x%08x,0x05c=0x%08x,0x060=0x%08x\n",
                        DISP_REG_GET(DISP_REG_WDMA_BUF_CON2+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_PRE_ADD0+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_PRE_ADD2+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_POST_ADD0+off_sft)); 
    
	DDPDUMP("WDMA:0x064=0x%08x,0x078=0x%08x,0x080=0x%08x,0x084=0x%08x\n",
                        DISP_REG_GET(DISP_REG_WDMA_POST_ADD2+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_DST_UV_PITCH+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_DST_ADDR_OFFSET0+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_DST_ADDR_OFFSET1+off_sft));     
    
	DDPDUMP("WDMA:0x088=0x%08x,0x0a0=0x%08x,0x0a4=0x%08x,0x0a8=0x%08x\n",
                        DISP_REG_GET(DISP_REG_WDMA_DST_ADDR_OFFSET2+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_FLOW_CTRL_DBG+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_EXEC_DBG+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_CT_DBG+off_sft)); 

 	DDPDUMP("WDMA:0x0ac=0x%08x,0xf00=0x%08x,0xf04=0x%08x,0xf08=0x%08x,\n",
                        DISP_REG_GET(DISP_REG_WDMA_DEBUG+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_DST_ADDR0+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_DST_ADDR1+off_sft),
                        DISP_REG_GET(DISP_REG_WDMA_DST_ADDR2+off_sft));   
    return ;
}
Ejemplo n.º 5
0
char* ddp_mutex_sof_to_string(unsigned int sof)
{
   switch(sof)
   {
       case 0: return "single";
       case 1: return "dsi0_vdo";
       case 2: return "dsi1_vdo";
       case 3: return "dpi";
       default:
           DDPDUMP("ddp_mutex_sof_to_string, unknown sof=%u\n", sof);
           return "unknown";
   }
   return "unknown";
}
Ejemplo n.º 6
0
static void  mutex_dump_reg(void)
{
    DDPDUMP("==DISP MUTEX REGS==\n");
    DDPDUMP("MUTEX:0x000=0x%08x,0x004=0x%08x,0x020=0x%08x,0x028=0x%08x\n",
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTSTA),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX0_EN),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX0_RST));

    DDPDUMP("MUTEX:0x02c=0x%08x,0x030=0x%08x,0x040=0x%08x,0x048=0x%08x\n",
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX0_MOD),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX0_SOF),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX1_EN),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX1_RST));

    DDPDUMP("MUTEX:0x04c=0x%08x,0x050=0x%08x,0x060=0x%08x,0x068=0x%08x\n",
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX1_MOD),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX1_SOF),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX2_EN),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX2_RST));

    DDPDUMP("MUTEX:0x06c=0x%08x,0x070=0x%08x,0x080=0x%08x,0x088=0x%08x\n",
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX2_MOD),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX2_SOF),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX3_EN),
                      DISP_REG_GET(DISP_REG_CONFIG_MUTEX3_RST));

    DDPDUMP("MUTEX:0x08c=0x%08x,0x090=0x%08x,0x0a0=0x%08x,0x0a8=0x%08x\n",
                       DISP_REG_GET(DISP_REG_CONFIG_MUTEX3_MOD),
                       DISP_REG_GET(DISP_REG_CONFIG_MUTEX3_SOF),
                       DISP_REG_GET(DISP_REG_CONFIG_MUTEX4_EN),
                       DISP_REG_GET(DISP_REG_CONFIG_MUTEX4_RST));

    DDPDUMP("MUTEX:0x0ac=0x%08x,0x0b0=0x%08x,0x0c0=0x%08x,0x0c8=0x%08x\n",
                       DISP_REG_GET(DISP_REG_CONFIG_MUTEX4_MOD),
                       DISP_REG_GET(DISP_REG_CONFIG_MUTEX4_SOF),
                       DISP_REG_GET(DISP_REG_CONFIG_MUTEX5_EN),
                       DISP_REG_GET(DISP_REG_CONFIG_MUTEX5_RST));
    DDPDUMP("MUTEX:0x0cc=0x%08x,0x0d0=0x%08x,0x200=0x%08x\n",
                       DISP_REG_GET(DISP_REG_CONFIG_MUTEX5_MOD),
                       DISP_REG_GET(DISP_REG_CONFIG_MUTEX5_SOF),
                       DISP_REG_GET(DISP_REG_CONFIG_DEBUG_OUT_SEL));

    return ;
}
Ejemplo n.º 7
0
void rdma_dump_analysis(DISP_MODULE_ENUM module)
{
    unsigned int idx = rdma_index(module);
    DDPDUMP("==DISP RDMA%d ANALYSIS==\n", idx); 
    DDPDUMP("rdma%d: en=%d, w=%d, h=%d, pitch=%d, addr=0x%x, fmt=%s, fifo_min=%d rdma_start_time=%lld ns,rdma_end_time=%lld ns\n",
        idx,
        DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_RDMA_INDEX_OFFSET*idx)&0x1,
        DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_RDMA_INDEX_OFFSET*idx)&0xfff,
        DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_RDMA_INDEX_OFFSET*idx)&0xfffff,
        DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH+DISP_RDMA_INDEX_OFFSET*idx), 
        DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_RDMA_INDEX_OFFSET*idx),
        rdma_intput_format_name(
            (DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_RDMA_INDEX_OFFSET*idx)>>4)&0xf,
            (DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_RDMA_INDEX_OFFSET*idx)>>8)&0x1
            ),
        DISP_REG_GET(DISP_REG_RDMA_FIFO_LOG+DISP_RDMA_INDEX_OFFSET*idx),
        rdma_start_time[idx],
        rdma_end_time[idx]
    );
    return ;
}
Ejemplo n.º 8
0
void wdma_dump_analysis(DISP_MODULE_ENUM module)
{
    unsigned int index = wdma_index(module);
    unsigned int idx_offst = index*DISP_WDMA_INDEX_OFFSET;
    DDPDUMP("==DISP WDMA%d ANALYSIS==\n",index);
    DDPDUMP("wdma%d:en=%d,w=%d,h=%d,clip=(%d,%d,%d,%d),pitch=(W=%d,UV=%d),addr=(0x%x,0x%x,0x%x),fmt=%s\n",
        index,
        DISP_REG_GET(DISP_REG_WDMA_EN+idx_offst),
        DISP_REG_GET(DISP_REG_WDMA_SRC_SIZE+idx_offst)&0x3fff,
        (DISP_REG_GET(DISP_REG_WDMA_SRC_SIZE+idx_offst)>>16)&0x3fff,
        
        DISP_REG_GET(DISP_REG_WDMA_CLIP_COORD+idx_offst)&0x3fff, 
        (DISP_REG_GET(DISP_REG_WDMA_CLIP_COORD+idx_offst)>>16)&0x3fff,
        DISP_REG_GET(DISP_REG_WDMA_CLIP_SIZE+idx_offst)&0x3fff, 
        (DISP_REG_GET(DISP_REG_WDMA_CLIP_SIZE+idx_offst)>>16)&0x3fff,

        DISP_REG_GET(DISP_REG_WDMA_DST_W_IN_BYTE+idx_offst),
        DISP_REG_GET(DISP_REG_WDMA_DST_UV_PITCH+idx_offst),

        DISP_REG_GET(DISP_REG_WDMA_DST_ADDR0+idx_offst),
        DISP_REG_GET(DISP_REG_WDMA_DST_ADDR1+idx_offst),
        DISP_REG_GET(DISP_REG_WDMA_DST_ADDR2+idx_offst),
        
        fmt_string(fmt_type(
            (DISP_REG_GET(DISP_REG_WDMA_CFG+idx_offst)>>4)&0xf,
            (DISP_REG_GET(DISP_REG_WDMA_CFG+idx_offst)>>11)&0x1
        ))
    );
    DDPDUMP("wdma%d:status=%s,in_req=%d,in_ack=%d, exec=%d, input_pixel=(L:%d,P:%d)\n",
        index,
        wdma_get_status(DISP_REG_GET_FIELD(FLOW_CTRL_DBG_FLD_WDMA_STA_FLOW_CTRL, DISP_REG_WDMA_FLOW_CTRL_DBG+idx_offst)),
        DISP_REG_GET_FIELD(EXEC_DBG_FLD_WDMA_IN_REQ, DISP_REG_WDMA_FLOW_CTRL_DBG+idx_offst),
        DISP_REG_GET_FIELD(EXEC_DBG_FLD_WDMA_IN_ACK, DISP_REG_WDMA_FLOW_CTRL_DBG+idx_offst),
        DISP_REG_GET(DISP_REG_WDMA_EXEC_DBG+idx_offst)&0x1f,
        (DISP_REG_GET(DISP_REG_WDMA_CT_DBG+idx_offst)>>16)&0xffff,
        DISP_REG_GET(DISP_REG_WDMA_CT_DBG+idx_offst)&0xffff
    );
   return;
}
Ejemplo n.º 9
0
void rdma_dump_reg(DISP_MODULE_ENUM module)
{
    unsigned int idx = rdma_index(module);
    unsigned int off_st = DISP_RDMA_INDEX_OFFSET*idx;
    DDPDUMP("== DISP RDMA%d REGS ==\n", idx);
    DDPDUMP("RDMA:0x000=0x%08x,0x004=0x%08x,0x010=0x%08x,0x014=0x%08x\n",
                  DISP_REG_GET(DISP_REG_RDMA_INT_ENABLE + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_INT_STATUS + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0 + off_st));

    DDPDUMP("RDMA:0x018=0x%08x,0x01c=0x%08x,0x024=0x%08x,0xf00=0x%08x\n",
                  DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1 + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_TARGET_LINE + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_MEM_CON + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR + off_st));
    
     DDPDUMP("RDMA:0x02c=0x%08x,0x030=0x%08x,0x034=0x%08x,0x038=0x%08x\n",
                  DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0 + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_MEM_SLOW_CON + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1 + off_st));   
             
     DDPDUMP("RDMA:0x040=0x%08x,0x044=0x%08x,0x078=0x%08x,0x07c=0x%08x\n",
                  DISP_REG_GET(DISP_REG_RDMA_FIFO_CON + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_FIFO_LOG + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_0 + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_1 + off_st));

      DDPDUMP("RDMA:0x080=0x%08x,0x084=0x%08x,0x088=0x%08x,0x08c=0x%08x\n",
                  DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_2 + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_POST_ADD_0 + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_POST_ADD_1 + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_POST_ADD_2 + off_st));
      
      DDPDUMP("RDMA:0x090=0x%08x,0x094=0x%08x,0x094=0x%08x\n",
                  DISP_REG_GET(DISP_REG_RDMA_DUMMY + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_DEBUG_OUT_SEL + off_st),
                  DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR + off_st));
    return;
}
Ejemplo n.º 10
0
static void process_dbg_opt(const char *opt)
{
    char *buf = dbg_buf + strlen(dbg_buf);
    static disp_session_config config;
    
    if (0 == strncmp(opt, "regr:", 5))
    {
        char *p = (char *)opt + 5;
        unsigned long addr = (unsigned long) simple_strtoul(p, &p, 16);

        if(is_reg_addr_valid(1, addr)==1)// (addr >= 0xf0000000U && addr <= 0xff000000U) 
        {
            unsigned int regVal = DISP_REG_GET(addr);
            DDPMSG("regr: 0x%lx = 0x%08X\n", addr, regVal);
            sprintf(buf, "regr: 0x%lx = 0x%08X\n", addr, regVal);
        } else {
            sprintf(buf, "regr, invalid address 0x%lx\n", addr);
            goto Error;
        }
    }
    else if (0 == strncmp(opt, "regw:", 5))
    {
        char *p = (char *)opt + 5;
        unsigned long addr = (unsigned long) simple_strtoul(p, &p, 16);
        unsigned int val = (unsigned int) simple_strtoul(p + 1, &p, 16);
        if(is_reg_addr_valid(1, addr)==1)// (addr >= 0xf0000000U && addr <= 0xff000000U) 
        {
            unsigned int regVal;
            DISP_CPU_REG_SET(addr, val);
            regVal = DISP_REG_GET(addr);
            DDPMSG("regw: 0x%lx, 0x%08X = 0x%08X\n", addr, val, regVal);
            sprintf(buf, "regw: 0x%lx, 0x%08X = 0x%08X\n", addr, val, regVal);
        } else {
            sprintf(buf, "regw, invalid address 0x%lx \n", addr);
            goto Error;
        }
    }
    else if (0 == strncmp(opt, "dbg_log:", 8))
    {
        char *p = (char *)opt + 8;
        unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
        if (enable)
            dbg_log_level = 1;
        else
            dbg_log_level = 0;

        sprintf(buf, "dbg_log: %d\n", dbg_log_level);
    }
    else if (0 == strncmp(opt, "irq_log:", 8))
    {
        char *p = (char *)opt + 8;
        unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
        if (enable)
            irq_log_level = 1;
        else
            irq_log_level = 0;
        
        sprintf(buf, "irq_log: %d\n", irq_log_level);        
    }
    else if (0 == strncmp(opt, "met_on:", 7))
    {
        char *p = (char *)opt + 7;
        int met_on = (int) simple_strtoul(p, &p, 10);
        int rdma0_mode = (int) simple_strtoul(p + 1, &p, 10);
        int rdma1_mode = (int) simple_strtoul(p + 1, &p, 10);
       // ddp_init_met_tag(met_on,rdma0_mode,rdma1_mode);
        DDPMSG("process_dbg_opt, met_on=%d,rdma0_mode %d, rdma1 %d \n", met_on,rdma0_mode,rdma1_mode);
        sprintf(buf, "met_on:%d,rdma0_mode:%d,rdma1_mode:%d\n", met_on,rdma0_mode,rdma1_mode);
    }    
    else if (0 == strncmp(opt, "backlight:", 10))
    {
        char *p = (char *)opt + 10;
        unsigned int level = (unsigned int) simple_strtoul(p, &p, 10);

        if (level) 
        {
            disp_bls_set_backlight(level);
            sprintf(buf, "backlight: %d\n", level); 
        } else {
            goto Error;
        }
    }
    else if (0 == strncmp(opt, "pwm0:", 5) || 0 == strncmp(opt, "pwm1:", 5))
    {
        char *p = (char *)opt + 5;
        unsigned int level = (unsigned int)simple_strtoul(p, &p, 10);

        if (level) 
        {
            disp_pwm_id_t pwm_id = DISP_PWM0;
            if (opt[3] == '1')
                pwm_id = DISP_PWM1;
                
            disp_pwm_set_backlight(pwm_id, level);
            sprintf(buf, "PWM 0x%x : %d\n", pwm_id, level); 
        } else {
            goto Error;
        }
    }
    else if (0 == strncmp(opt, "aal_dbg:", 8))
    {
        aal_dbg_en = (int)simple_strtoul(opt + 8, NULL, 10);
        sprintf(buf, "aal_dbg_en = 0x%x\n", aal_dbg_en); 
    }
    else if (0 == strncmp(opt, "dump_reg:", 9))
    {
        char *p = (char *)opt + 9;
        unsigned int module = (unsigned int) simple_strtoul(p, &p, 10);
        DDPMSG("process_dbg_opt, module=%d \n", module);
        if (module<DISP_MODULE_NUM) 
        {
            ddp_dump_reg(module);
            sprintf(buf, "dump_reg: %d\n", module); 
        } else {
            DDPMSG("process_dbg_opt2, module=%d \n", module);
            goto Error;
        }
    }
    else if (0 == strncmp(opt, "dump_path:", 10))
    {
        char *p = (char *)opt + 10;
        unsigned int mutex_idx = (unsigned int) simple_strtoul(p, &p, 10);
        DDPMSG("process_dbg_opt, path mutex=%d \n", mutex_idx);
        dpmgr_debug_path_status(mutex_idx);
        sprintf(buf, "dump_path: %d\n", mutex_idx);
    }
    else if (0 == strncmp(opt, "debug:", 6))
    {
        char *p = (char *)opt + 6;
        unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
        if(enable==1)
        {
            DDPMSG("[DDP] debug=1, trigger AEE\n");
            //aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT");
        }
        else if(enable==2)
        {
           ddp_mem_test();
        }
        else if(enable==3)
        {
           ddp_lcd_test();
        }
        else if(enable==4)
        {
            //DDPAEE("test 4");
        }
        else if(enable==5)
        {
            extern unsigned int gDDPError;
            if(gDDPError==0)
              gDDPError = 1;
            else
              gDDPError = 0;

            sprintf(buf, "bypass PQ: %d\n", gDDPError);
            DDPMSG("bypass PQ: %d\n", gDDPError);
        }
        else if(enable==6)
        {
            unsigned int i = 0;
            int * modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
            int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);

            printk("dump path status:");
            for(i=0;i<module_num;i++)
            {
                printk("%s-", ddp_get_module_name(modules[i]));
            }
            printk("\n");

            ddp_dump_analysis(DISP_MODULE_CONFIG);
            ddp_dump_analysis(DISP_MODULE_MUTEX);            
            for( i=0; i< module_num;i++)
            {
                ddp_dump_analysis(modules[i]);
            }
            
            ddp_dump_reg(DISP_MODULE_CONFIG);    
            ddp_dump_reg(DISP_MODULE_MUTEX);
            for( i=0; i< module_num;i++)
            {
                ddp_dump_reg(modules[i]);
            }   
        }
        else if(enable==7)
        {
            if(dbg_log_level<3)
               dbg_log_level++;
            else
                dbg_log_level=0;
                
            printk("DDP: dbg_log_level=%d\n", dbg_log_level);    
            sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
        }
#if 0
        else if(enable==8)
        {
            DDPDUMP("clock_mm setting:%u \n",
            DISP_REG_GET(DISP_REG_CONFIG_C11));
            if(DISP_REG_GET(DISP_REG_CONFIG_C11)&0xff000000!=0xff000000)
            {
                DDPDUMP("error, MM clock bit 24~bit31 should be 1, but real value=0x%x", DISP_REG_GET(DISP_REG_CONFIG_C11));
            }
        }
#endif
        else if(enable==9)
        {
            gOVLBackground = 0xFF0000FF;
            printk("DDP: gOVLBackground=%d\n", gOVLBackground);    
            sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
        }
        else if(enable==10)
        {
            gOVLBackground = 0xFF000000;
            printk("DDP: gOVLBackground=%d\n", gOVLBackground);    
            sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
        }
        else if(enable==11)
        {
            unsigned int i=0;
            for(i=0;i<DISP_REG_NUM;i++)
            {
                DDPDUMP("i=%d, module=%s, reg_va=0x%lx\n", i, ddp_get_reg_module_name(i), dispsys_reg[i]);
            }
        }
        else if(enable==12)
        {
            if(gUltraEnable==0)
              gUltraEnable = 1;
            else
              gUltraEnable = 0;

            printk("DDP: gUltraEnable=%d\n", gUltraEnable);    
            sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);              
        }
    }
    else if (0 == strncmp(opt, "mmp", 3))
    {
        init_ddp_mmp_events();
    }
    else
    {
        dbg_buf[0]='\0';
	    goto Error;
    }

    return;

Error:
    DDPERR("parse command error!\n%s\n\n%s", opt, STR_HELP);
}
Ejemplo n.º 11
0
void rdma_dump_reg(DISP_MODULE_ENUM module)
{
    unsigned int idx = rdma_index(module);
    DDPDUMP("== DISP RDMA%d REGS ==\n", idx); 
    DDPDUMP("(0x000)R_INTEN       =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_INT_ENABLE+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x004)R_INTS        =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_INT_STATUS+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x010)R_CON         =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x014)R_SIZE0       =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x018)R_SIZE1       =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x01c)R_TAR_LINE    =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_TARGET_LINE+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x024)R_M_CON       =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0xf00)R_M_S_ADDR    =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x02c)R_M_SRC_PITCH =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x030)R_M_GMC_SET0  =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x034)R_M_SLOW_CON  =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_SLOW_CON+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x038)R_M_GMC_SET1  =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x040)R_FIFO_CON    =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_FIFO_CON+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x044)R_FIFO_LOG    =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_FIFO_LOG+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x078)R_PRE_ADD0    =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_0+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x07c)R_PRE_ADD1    =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_1+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x080)R_PRE_ADD2    =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_2+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x084)R_POST_ADD0   =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_POST_ADD_0+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x088)R_POST_ADD1   =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_POST_ADD_1+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x08c)R_POST_ADD2   =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_POST_ADD_2+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x090)R_DUMMY       =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_DUMMY+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x094)R_OUT_SEL     =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_DEBUG_OUT_SEL+DISP_RDMA_INDEX_OFFSET*idx));
    DDPDUMP("(0x094)R_M_START     =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_RDMA_INDEX_OFFSET*idx));
    DDPDUMP("(0x0f0)R_IN_PXL_CNT  =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_IN_P_CNT+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x0f4)R_IN_LINE_CNT =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_IN_LINE_CNT+DISP_RDMA_INDEX_OFFSET*idx));             
    DDPDUMP("(0x0f8)R_OUT_PXL_CNT =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_OUT_P_CNT+DISP_RDMA_INDEX_OFFSET*idx));
    DDPDUMP("(0x0fc)R_OUT_LINE_CNT=0x%x\n", DISP_REG_GET(DISP_REG_RDMA_OUT_LINE_CNT+DISP_RDMA_INDEX_OFFSET*idx));

    return;
}
Ejemplo n.º 12
0
static void ddp_check_path_l(int *module_list)
{
    unsigned int i, j, k;
    int step = 0;
    int valid =0;
    unsigned int mout;
    unsigned int path_error = 0;
    unsigned int module_num = ddp_get_module_num_l(module_list);
    DDPDUMP("check_path: %s to %s\n",ddp_get_module_name(module_list[0])
            ,ddp_get_module_name(module_list[module_num-1]));
    // check mout
    for(i = 0 ; i < module_num - 1 ; i++)
    {
        for(j = 0 ; j < DDP_MOUT_NUM ; j++)
        {
            if(module_list[i] == mout_map[j].id)
            {
                mout = 0;
                //find next module which can be connected
                step = i+1;
                while(module_can_connect[module_list[step]].bit==0 && step<module_num)
                {
                   step++; 
                }
                ASSERT(step<module_num);
                for(k = 0 ; k < 5 ; k++)
                {
                    if(mout_map[j].out_id_bit_map[k].m == -1)
                        break;
                    if(mout_map[j].out_id_bit_map[k].m == module_list[step])
                    {
                        mout |= mout_map[j].out_id_bit_map[k].v;
                        valid =1;
                        break;
                    }
                }
                if(valid)
                {
                    valid =0;
                    if((DISP_REG_GET(mout_map[j].reg) & mout)==0)
                    {
                        path_error += 1;
                        DDPDUMP("error:%s mout, expect=0x%x, real=0x%x \n",
                            ddp_get_module_name(module_list[i]),
                            mout,
                            DISP_REG_GET(mout_map[j].reg));
                    }
                    else if(DISP_REG_GET(mout_map[j].reg) != mout)
                    {
                        DDPDUMP("warning: %s mout expect=0x%x, real=0x%x \n",
                            ddp_get_module_name(module_list[i]),
                            mout,      
                            DISP_REG_GET(mout_map[j].reg));
                    }
                }
                break;
             }
        }
    }
    // check out select
    for(i = 0 ; i < module_num - 1 ; i++)
    {
        for(j = 0 ; j < DDP_SEL_OUT_NUM ; j++)
        {
            if(module_list[i] == sel_out_map[j].id)
            {
                 //find next module which can be connected
                step = i+1;
                while(module_can_connect[module_list[step]].bit==0 && step<module_num)
                {
                   step++; 
                }
                ASSERT(step<module_num);
                for(k = 0 ; k < 4 ; k++)
                {
                    if(sel_out_map[j].id_bit_map[k] == -1)
                        break;
                    if(sel_out_map[j].id_bit_map[k] == module_list[step])
                    {
                        if(DISP_REG_GET(sel_out_map[j].reg) != k)
                        {
                            path_error += 1;
                            DDPDUMP("error:out_s %s not connect to %s, expect=0x%x, real=0x%x \n",
                               ddp_get_module_name(module_list[i]),ddp_get_module_name(module_list[step]),
                               k,
                               DISP_REG_GET(sel_out_map[j].reg));
                        }
                        break;
                    }
                 }
            }
        }
    }
    // check input select
    for(i = 1 ; i < module_num ; i++)
    {
        for(j = 0 ; j < DDP_SEL_IN_NUM ; j++)
        {
            if(module_list[i] == sel_in_map[j].id)
            {
                //find next module which can be connected
                step = i-1;
                while(module_can_connect[module_list[step]].bit==0 && step>0)
                {
                   step--; 
                }
                 ASSERT(step>=0);
                for(k = 0 ; k < 4 ; k++)
                {
                    if(sel_in_map[j].id_bit_map[k] == -1)
                        break;
                    if(sel_in_map[j].id_bit_map[k] == module_list[step])
                    {
                        if(DISP_REG_GET(sel_in_map[j].reg) != k)
                        {
                            path_error += 1;
                            DDPDUMP("error:in_s %s not connect to %s, expect=0x%x, real=0x%x \n",
                               ddp_get_module_name(module_list[step]),ddp_get_module_name(module_list[i]),
                               k,
                               DISP_REG_GET(sel_in_map[j].reg));
                        }
                        break;
                    }
                 }
            }
        }
    }
    if(path_error == 0)
    {
        DDPDUMP("path: %s to %s is connected\n",ddp_get_module_name(module_list[0]),
               ddp_get_module_name(module_list[module_num - 1]));
    }
    else
    {
        DDPDUMP("path: %s to %s not connected!!!\n",ddp_get_module_name(module_list[0]),
        ddp_get_module_name(module_list[module_num - 1]));
    }
}
Ejemplo n.º 13
0
static void disp_debug_api(unsigned int enable, char *buf)
{
	if (enable == 1) {
		DDPMSG("[DDP] debug=1, trigger AEE\n");
		/* aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); */
	} else if (enable == 2) {
		ddp_mem_test();
	} else if (enable == 3) {
		ddp_lcd_test();
	} else if (enable == 4) {
		DDPAEE("test enable=%d\n", enable);
		sprintf(buf, "test enable=%d\n", enable);
	} else if (enable == 5) {
		if (gDDPError == 0)
			gDDPError = 1;
		else
			gDDPError = 0;

		sprintf(buf, "bypass PQ: %d\n", gDDPError);
		DDPMSG("bypass PQ: %d\n", gDDPError);
	} else if (enable == 6) {
		/*ddp_dump_analysis(DISP_MODULE_DSI0);*/
		ddp_dump_reg(DISP_MODULE_DSI0);
	} else if (enable == 7) {
		if (dbg_log_level < 3)
			dbg_log_level++;
		else
			dbg_log_level = 0;

		pr_debug("DDP: dbg_log_level=%d\n", dbg_log_level);
		sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
	} else if (enable == 8) {
		DDPDUMP("clock_mm setting:%u\n",
			DISP_REG_GET(DISP_REG_CONFIG_C11));
		if (DISP_REG_GET(DISP_REG_CONFIG_C11) & 0xff000000 !=
		    0xff000000) {
			DDPDUMP
			    ("error, MM clock bit 24~bit31 should be 1, but real value=0x%x",
			     DISP_REG_GET(DISP_REG_CONFIG_C11));
		}
	} else if (enable == 9) {
		gOVLBackground = 0xFF0000FF;
		pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
		sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
	} else if (enable == 10) {
		gOVLBackground = 0xFF000000;
		pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
		sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
	} else if (enable == 11) {
		dispsys_irq[DISP_REG_NUM];
		ddp_irq_num[DISP_REG_NUM];
		unsigned int i = 0;
		char *buf_temp = buf;

		for (i = 0; i < DISP_REG_NUM; i++) {
			DDPDUMP
			    ("i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
			     i, ddp_get_reg_module_name(i), dispsys_reg[i],
			     ddp_reg_pa_base[i], dispsys_irq[i],
			     ddp_irq_num[i]);
			sprintf(buf_temp,
				"i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
				i, ddp_get_reg_module_name(i), dispsys_reg[i],
				ddp_reg_pa_base[i], dispsys_irq[i],
				ddp_irq_num[i]);
			buf_temp += strlen(buf_temp);
		}
	} else if (enable == 12) {
		if (gUltraEnable == 0)
			gUltraEnable = 1;
		else
			gUltraEnable = 0;

		pr_debug("DDP : gUltraEnable = %d\n", gUltraEnable);
		sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);
	} else if (enable == 13) {
		/*int ovl_status = ovl_get_status();
		   config.type = DISP_SESSION_MEMORY;
		   config.device_id = 0;
		   disp_create_session(&config);
		   pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
		   sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); */
	} else if (enable == 14) {
		/*int ovl_status = ovl_get_status();
		   disp_destroy_session(&config);
		   pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
		   sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); */
	} else if (enable == 15) {
		/* extern smi_dumpDebugMsg(void); */
		ddp_dump_analysis(DISP_MODULE_CONFIG);
		ddp_dump_analysis(DISP_MODULE_RDMA0);
		ddp_dump_analysis(DISP_MODULE_OVL0);
		ddp_dump_analysis(DISP_MODULE_OVL1);

		/* dump ultra/preultra related regs */
	DDPMSG("wdma_con1(2c) = 0x%x, wdma_con2(0x38) = 0x%x, rdma_gmc0(30) = 0x%x",
			DISP_REG_GET(DISP_REG_WDMA_BUF_CON1), DISP_REG_GET(DISP_REG_WDMA_BUF_CON2),
			DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0));
	DDPMSG(" rdma_gmc1(38) = 0x%x, fifo_con(40) = 0x%x\n ",
		     DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1),
		     DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
		DDPMSG(" ovl0_gmc : 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc : 0x%x, 0x%x, 0x%x, 0x%x\n ",
		       DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING),
		       DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING),
		       DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING),
		       DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING),
		       DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
		       DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
		       DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
		       DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET));

		/* dump smi regs */
		/* smi_dumpDebugMsg(); */

	} else if (enable == 16) {
		if (gDumpMemoutCmdq == 0)
			gDumpMemoutCmdq = 1;
		else
			gDumpMemoutCmdq = 0;

		pr_debug(" DDP : gDumpMemoutCmdq = %d\n ", gDumpMemoutCmdq);
		sprintf(buf, " gDumpMemoutCmdq :  %d\n ", gDumpMemoutCmdq);
	} else if (enable == 21) {
		if (gEnableSODIControl == 0)
			gEnableSODIControl = 1;
		else
			gEnableSODIControl = 0;

		pr_debug(" DDP : gEnableSODIControl = %d\n ", gEnableSODIControl);
		sprintf(buf, " gEnableSODIControl :  %d\n ", gEnableSODIControl);
	} else if (enable == 22) {
		if (gPrefetchControl == 0)
			gPrefetchControl = 1;
		else
			gPrefetchControl = 0;

		pr_debug(" DDP : gPrefetchControl = %d\n ", gPrefetchControl);
		sprintf(buf, " gPrefetchControl :  %d\n ", gPrefetchControl);
	} else if (enable == 23) {
		if (disp_low_power_enlarge_blanking == 0)
			disp_low_power_enlarge_blanking = 1;
		else
			disp_low_power_enlarge_blanking = 0;

		pr_debug(" DDP : disp_low_power_enlarge_blanking = %d\n ",
		       disp_low_power_enlarge_blanking);
		sprintf(buf, " disp_low_power_enlarge_blanking :  %d\n ",
			disp_low_power_enlarge_blanking);

	} else if (enable == 24) {
		if (disp_low_power_disable_ddp_clock == 0)
			disp_low_power_disable_ddp_clock = 1;
		else
			disp_low_power_disable_ddp_clock = 0;

		pr_debug(" DDP : disp_low_power_disable_ddp_clock = %d\n ",
		       disp_low_power_disable_ddp_clock);
		sprintf(buf, " disp_low_power_disable_ddp_clock :  %d\n ",
			disp_low_power_disable_ddp_clock);

	} else if (enable == 25) {
		if (disp_low_power_disable_fence_thread == 0)
			disp_low_power_disable_fence_thread = 1;
		else
			disp_low_power_disable_fence_thread = 0;

		pr_debug(" DDP : disp_low_power_disable_fence_thread = %d\n ",
		       disp_low_power_disable_fence_thread);
		sprintf(buf, " disp_low_power_disable_fence_thread :  %d\n ",
			disp_low_power_disable_fence_thread);

	} else if (enable == 26) {
		if (disp_low_power_remove_ovl == 0)
			disp_low_power_remove_ovl = 1;
		else
			disp_low_power_remove_ovl = 0;

		pr_debug(" DDP : disp_low_power_remove_ovl = %d\n ", disp_low_power_remove_ovl);
		sprintf(buf, " disp_low_power_remove_ovl :  %d\n ", disp_low_power_remove_ovl);

	} else if (enable == 27) {
		if (gSkipIdleDetect == 0)
			gSkipIdleDetect = 1;
		else
			gSkipIdleDetect = 0;

		pr_debug(" DDP : gSkipIdleDetect = %d\n ", gSkipIdleDetect);
		sprintf(buf, " gSkipIdleDetect :  %d\n ", gSkipIdleDetect);

	} else if (enable == 28) {
		if (gDumpClockStatus == 0)
			gDumpClockStatus = 1;
		else
			gDumpClockStatus = 0;

		pr_debug(" DDP : gDumpClockStatus = %d\n ", gDumpClockStatus);
		sprintf(buf, " gDumpClockStatus :  %d\n ", gDumpClockStatus);

	} else if (enable == 29) {
		if (gEnableUartLog == 0)
			gEnableUartLog = 1;
		else
			gEnableUartLog = 0;

		pr_debug(" DDP : gEnableUartLog = %d\n ", gEnableUartLog);
		sprintf(buf, " gEnableUartLog :  %d\n ", gEnableUartLog);

	} else if (enable == 30) {
		if (gEnableMutexRisingEdge == 0) {
			gEnableMutexRisingEdge = 1;
			DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF,
					   1);
		} else {
			gEnableMutexRisingEdge = 0;
			DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF,
					   0);
		}

		pr_debug(" DDP : gEnableMutexRisingEdge = %d\n ", gEnableMutexRisingEdge);
		sprintf(buf, " gEnableMutexRisingEdge :  %d\n ", gEnableMutexRisingEdge);

	} else if (enable == 31) {
		if (gEnableReduceRegWrite == 0)
			gEnableReduceRegWrite = 1;
		else
			gEnableReduceRegWrite = 0;

		pr_debug(" DDP : gEnableReduceRegWrite = %d\n ", gEnableReduceRegWrite);
		sprintf(buf, " gEnableReduceRegWrite :  %d\n ", gEnableReduceRegWrite);

	} else if (enable == 32) {
		/* DDPAEE(" DDP : (32) gEnableReduceRegWrite = %d\n ", gEnableReduceRegWrite); */
	} else if (enable == 33) {
		if (gDumpConfigCMD == 0)
			gDumpConfigCMD = 1;
		else
			gDumpConfigCMD = 0;

		pr_debug(" DDP : gDumpConfigCMD = %d\n ", gDumpConfigCMD);
		sprintf(buf, " gDumpConfigCMD :  %d\n ", gDumpConfigCMD);

	} else if (enable == 34) {
		if (gESDEnableSODI == 0)
			gESDEnableSODI = 1;
		else
			gESDEnableSODI = 0;

		pr_debug(" DDP : gESDEnableSODI = %d\n ", gESDEnableSODI);
		sprintf(buf, " gESDEnableSODI :  %d\n ", gESDEnableSODI);

	} else if (enable == 35) {
		if (gEnableOVLStatusCheck == 0)
			gEnableOVLStatusCheck = 1;
		else
			gEnableOVLStatusCheck = 0;

		pr_debug(" DDP : gEnableOVLStatusCheck = %d\n ", gEnableOVLStatusCheck);
		sprintf(buf, " gEnableOVLStatusCheck :  %d\n ", gEnableOVLStatusCheck);

	} else if (enable == 36) {
		if (gResetRDMAEnable == 0)
			gResetRDMAEnable = 1;
		else
			gResetRDMAEnable = 0;

		pr_debug(" DDP : gResetRDMAEnable = %d\n ", gResetRDMAEnable);
		sprintf(buf, " gResetRDMAEnable :  %d\n ", gResetRDMAEnable);
	} else if (enable == 37) {
		unsigned int reg_value = 0;

		if (gEnableIRQ == 0) {
			gEnableIRQ = 1;

			/* OVL0/OVL1 */
			DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e2);
			DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e2);

			/* Mutex0 */
			reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
			DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
					 reg_value | (1 << 0) | (1 << DISP_MUTEX_TOTAL));

			/* RDMA0 */
			DISP_CPU_REG_SET(DISP_REG_RDMA_INT_ENABLE, 0x3E);
		} else {
			gEnableIRQ = 0;

			/* OVL0/OVL1 */
			DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e0);
			DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e0);

			/* Mutex0 */
			reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
			DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
					 reg_value & (~(1 << 0)) & (~(1 << DISP_MUTEX_TOTAL)));

			/* RDMA0 */
			DISP_CPU_REG_SET(DISP_REG_RDMA_INT_ENABLE, 0x18);

		}

		pr_debug(" DDP : gEnableIRQ = %d\n ", gEnableIRQ);
		sprintf(buf, " gEnableIRQ :  %d\n ", gEnableIRQ);

	} else if (enable == 38) {
		if (gDisableSODIForTriggerLoop == 0)
			gDisableSODIForTriggerLoop = 1;
		else
			gDisableSODIForTriggerLoop = 0;

		pr_debug(" DDP : gDisableSODIForTriggerLoop = %d\n ", gDisableSODIForTriggerLoop);
		sprintf(buf, " gDisableSODIForTriggerLoop :  %d\n ", gDisableSODIForTriggerLoop);

	} else if (enable == 39) {
		cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_STREAM_EOF);
		cmdqCoreSetEvent(CMDQ_EVENT_DISP_RDMA0_EOF);
		sprintf(buf, " enable = %d\n ", enable);
	} else if (enable == 41) {
		if (gResetOVLInAALTrigger == 0)
			gResetOVLInAALTrigger = 1;
		else
			gResetOVLInAALTrigger = 0;

		pr_debug(" DDP : gResetOVLInAALTrigger = %d\n ", gResetOVLInAALTrigger);
		sprintf(buf, " gResetOVLInAALTrigger :  %d\n ", gResetOVLInAALTrigger);

	} else if (enable == 42) {
		if (gDisableOVLTF == 0)
			gDisableOVLTF = 1;
		else
			gDisableOVLTF = 0;

		pr_debug(" DDP : gDisableOVLTF = %d\n ", gDisableOVLTF);
		sprintf(buf, " gDisableOVLTF :  %d\n ", gDisableOVLTF);

	} else if (enable == 43) {
		if (gDumpESDCMD == 0)
			gDumpESDCMD = 1;
		else
			gDumpESDCMD = 0;

		pr_debug(" DDP : gDumpESDCMD = %d\n ", gDumpESDCMD);
		sprintf(buf, " gDumpESDCMD :  %d\n ", gDumpESDCMD);

	} else if (enable == 44) {
		disp_dump_emi_status();
		disp_dump_emi_status();
		sprintf(buf, " dump emi status !\n ");
	} else if (enable == 45) {
		if (gEnableCMDQProfile == 0)
			gEnableCMDQProfile = 1;
		else
			gEnableCMDQProfile = 0;

		pr_debug(" DDP : gEnableCMDQProfile = %d\n ", gEnableCMDQProfile);
		sprintf(buf, " gEnableCMDQProfile :  %d\n ", gEnableCMDQProfile);

	} else if (enable == 46) {
		disp_set_pll(156);
		pr_debug(" DDP : disp_set_pll = 156.\n ");
		sprintf(buf, " disp_set_pll = 156.\n ");
	} else if (enable == 47) {
		disp_set_pll(182);
		pr_debug(" DDP : disp_set_pll = 182.\n ");
		sprintf(buf, " disp_set_pll = 182.\n ");
	} else if (enable == 48) {
		disp_set_pll(364);
		pr_debug(" DDP : disp_set_pll = 364\n ");
		sprintf(buf, " disp_set_pll = 364.\n ");
	} else if (enable == 49) {
		if (gChangeRDMAThreshold == 0)
			gChangeRDMAThreshold = 1;
		else
			gChangeRDMAThreshold = 0;

		pr_debug(" DDP : gChangeRDMAThreshold = %d\n ", gChangeRDMAThreshold);
		sprintf(buf, " gChangeRDMAThreshold :  %d\n ", gChangeRDMAThreshold);

	} else if (enable == 50) {
		if (gChangeMMClock == 0)
			gChangeMMClock = 1;
		else
			gChangeMMClock = 0;

		pr_debug(" DDP : gChangeMMClock = %d\n ", gChangeMMClock);
		sprintf(buf, " gChangeMMClock :  %d\n ", gChangeMMClock);

	} else if (enable == 51) {
		if (gEnableUnderflowAEE == 0)
			gEnableUnderflowAEE = 1;
		else
			gEnableUnderflowAEE = 0;

		pr_debug(" DDP : gEnableUnderflowAEE = %d\n ", gEnableUnderflowAEE);
		sprintf(buf, " gEnableUnderflowAEE :  %d\n ", gEnableUnderflowAEE);

	} else if (enable == 52) {
		unsigned int time;
		cmdqRecHandle handle = NULL;
		cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);

		time = disp_set_pll_by_cmdq(156, handle);
		pr_debug(" DDP : disp_set_pll_by_cmdq = 156. estimate execute time = %d\n ", time);
		sprintf(buf, " disp_set_pll_by_cmdq = 156. estimate execute time = %d\n ", time);
		cmdqRecDestroy(handle);
	} else if (enable == 53) {
		unsigned int time;
		cmdqRecHandle handle = NULL;
		cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);

		time = disp_set_pll_by_cmdq(182, handle);
		pr_debug(" DDP : disp_set_pll_by_cmdq = 182. estimate execute time = %d\n ", time);
		sprintf(buf, " disp_set_pll_by_cmdq = 182. estimate execute time = %d\n ", time);
		cmdqRecDestroy(handle);
	} else if (enable == 54) {
		unsigned int time;
		cmdqRecHandle handle = NULL;
		cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);

		time = disp_set_pll_by_cmdq(364, handle);
		pr_debug(" DDP : disp_set_pll_by_cmdq = 364. estimate execute time = %d\n ", time);
		sprintf(buf, " disp_set_pll_by_cmdq = 364. estimate execute time = %d\n ", time);
		cmdqRecDestroy(handle);
	} else if (enable == 55) {
		if (gIssueRequestThreshold == 0)
			gIssueRequestThreshold = 1;
		else
			gIssueRequestThreshold = 0;

		pr_debug(" DDP : gIssueRequestThreshold = %d\n ", gIssueRequestThreshold);
		sprintf(buf, " gIssueRequestThreshold :  %d\n ", gIssueRequestThreshold);

	} else if (enable == 56) {
		if (gDisableIRQWhenIdle == 0)
			gDisableIRQWhenIdle = 1;
		else
			gDisableIRQWhenIdle = 0;

		pr_debug(" DDP : gDisableIRQWhenIdle = %d\n ", gDisableIRQWhenIdle);
		sprintf(buf, " gDisableIRQWhenIdle :  %d\n ", gDisableIRQWhenIdle);
	} else if (enable == 57) {
		if (gEnableSODIWhenIdle == 0)
			gEnableSODIWhenIdle = 1;
		else
			gEnableSODIWhenIdle = 0;

		pr_debug(" DDP : gEnableSODIWhenIdle = %d\n ", gEnableSODIWhenIdle);
		sprintf(buf, " gEnableSODIWhenIdle :  %d\n ", gEnableSODIWhenIdle);

	} else if (enable == 58) {
#ifdef DISP_ENABLE_LAYER_FRAME
		if (gAddFrame == 0)
			gAddFrame = 1;
		else
			gAddFrame = 0;

		pr_debug(" DDP : gAddFrame = %d\n ", gAddFrame);
		sprintf(buf, " gAddFrame :  %d\n ", gAddFrame);
#else
		pr_debug(" Please enable DISP_ENABLE_LAYER_FRAME in ddp_debug.h first !\n ");
		sprintf(buf, " Please enable DISP_ENABLE_LAYER_FRAME in ddp_debug.h first !\n ");
#endif
	} else if (enable == 40) {
		sprintf(buf, " version :  %d, %s\n ", 12, __TIME__);
	} else if (enable==59) {
        extern void ddp_reset_test(void);
        ddp_reset_test();
        sprintf(buf, " dp_reset_test called. \n ");
	} else if (enable == 60) {
		unsigned int i = 0;
		int *modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
		int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);

		pr_debug("dump path status:");
		for (i = 0; i < module_num; i++)
			pr_debug("%s-", ddp_get_module_name(modules[i]));

		pr_debug("\n");

		ddp_dump_analysis(DISP_MODULE_CONFIG);
		ddp_dump_analysis(DISP_MODULE_MUTEX);
		for (i = 0; i < module_num; i++)
			ddp_dump_analysis(modules[i]);

		if (primary_display_is_decouple_mode()) {
			ddp_dump_analysis(DISP_MODULE_OVL0);
			ddp_dump_analysis(DISP_MODULE_OVL1);
			ddp_dump_analysis(DISP_MODULE_WDMA0);
		}

		ddp_dump_reg(DISP_MODULE_CONFIG);
		ddp_dump_reg(DISP_MODULE_MUTEX);

		if (primary_display_is_decouple_mode()) {
			ddp_dump_reg(DISP_MODULE_OVL0);
			ddp_dump_reg(DISP_MODULE_OVL1);
			ddp_dump_reg(DISP_MODULE_WDMA0);
		}

		for (i = 0; i < module_num; i++)
			ddp_dump_reg(modules[i]);
	}
}
Ejemplo n.º 14
0
static void  mutex_dump_reg(void)
{
    DDPDUMP("==DISP MUTEX REGS==\n");
    DDPDUMP("(0x000)M_INTEN   =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN));  
    DDPDUMP("(0x004)M_INTSTA  =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTSTA));  
    DDPDUMP("(0x020)M0_EN     =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX0_EN));  
    DDPDUMP("(0x028)M0_RST    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX0_RST));  
    DDPDUMP("(0x02c)M0_MOD    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX0_MOD));  
    DDPDUMP("(0x030)M0_SOF    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX0_SOF));  
    DDPDUMP("(0x040)M1_EN     =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX1_EN));  
    DDPDUMP("(0x048)M1_RST    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX1_RST));  
    DDPDUMP("(0x04c)M1_MOD    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX1_MOD));  
    DDPDUMP("(0x050)M1_SOF    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX1_SOF));  
    DDPDUMP("(0x060)M2_EN     =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX2_EN));  
    DDPDUMP("(0x068)M2_RST    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX2_RST));  
    DDPDUMP("(0x06c)M2_MOD    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX2_MOD));  
    DDPDUMP("(0x070)M2_SOF    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX2_SOF));  
    DDPDUMP("(0x080)M3_EN     =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX3_EN));  
    DDPDUMP("(0x088)M3_RST    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX3_RST));  
    DDPDUMP("(0x08c)M3_MOD    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX3_MOD));  
    DDPDUMP("(0x090)M3_SOF    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX3_SOF));  
    DDPDUMP("(0x0a0)M4_EN     =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX4_EN));  
    DDPDUMP("(0x0a8)M4_RST    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX4_RST));  
    DDPDUMP("(0x0ac)M4_MOD    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX4_MOD));  
    DDPDUMP("(0x0b0)M4_SOF    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX4_SOF));  
    DDPDUMP("(0x0c0)M5_EN     =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX5_EN));  
    DDPDUMP("(0x0c8)M5_RST    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX5_RST));  
    DDPDUMP("(0x0cc)M5_MOD    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX5_MOD));  
    DDPDUMP("(0x0d0)M5_SOF    =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_MUTEX5_SOF));  
    DDPDUMP("(0x200)DEBUG_OUT_SEL =0x%x\n", DISP_REG_GET(DISP_REG_CONFIG_DEBUG_OUT_SEL)); 
    return ;
}
Ejemplo n.º 15
0
char* ddp_get_fmt_name(DISP_MODULE_ENUM module, unsigned int fmt)
{
   if(module==DISP_MODULE_WDMA0 || module==DISP_MODULE_WDMA1)
   {
       switch(fmt)
       {
           case 0: return "rgb565";
           case 1: return "rgb888";
           case 2: return "rgba8888";
           case 3: return "argb8888";
           case 4: return "uyvy";
           case 5: return "yuy2";
           case 7: return "y-only";
           case 8: return "iyuv";
           case 12:return "nv12";
           default: 
               DDPDUMP("ddp_get_fmt_name, unknown fmt=%d, module=%d \n", fmt, module);
               return "unknown";
       }
   }
   else if(module==DISP_MODULE_OVL0 || module==DISP_MODULE_OVL1)
   {
       switch(fmt)
       {
           case 0: return "rgb565";
           case 1: return "rgb888";
           case 2: return "rgba8888";
           case 3: return "argb8888";
           case 4: return "uyvy";
           case 5: return "yuyv";
           default: 
               DDPDUMP("ddp_get_fmt_name, unknown fmt=%d, module=%d \n", fmt, module);
               return "unknown"; 
       }   
   }
   else if(module==DISP_MODULE_RDMA0 || module==DISP_MODULE_RDMA1 || module==DISP_MODULE_RDMA2) // todo: confirm with designers
   {
       switch(fmt)
       {
           case 0: return "rgb565";
           case 1: return "rgb888";
           case 2: return "rgba8888";
           case 3: return "argb8888";
           case 4: return "uyvy";
           case 5: return "yuyv";
           default: 
               DDPDUMP("ddp_get_fmt_name, unknown fmt=%d, module=%d \n", fmt, module);
               return "unknown"; 
       }   
   }  
   else if(module==DISP_MODULE_MUTEX)
   {
       switch(fmt)
       {
           case 0: return "single";
           case 1: return "dsi0_vdo";
           case 2: return "dsi1_vdo";
           case 3: return "dpi";
           default: 
               DDPDUMP("ddp_get_fmt_name, unknown fmt=%d, module=%d \n", fmt, module);
               return "unknown"; 
       }
   } 
   else
   {
       DDPDUMP("ddp_get_fmt_name, unknown module=%d \n", module);
   }
   
   return "unknown";
}
Ejemplo n.º 16
0
static void process_dbg_debug(const char *opt)
{
	unsigned int enable = 0;
	static disp_session_config config;
	char *p;
	char *buf = dbg_buf + strlen(dbg_buf);
	int ret;

	p = (char *)opt + 6;
	ret = kstrtoul(p, 10, (long unsigned int *)&enable);
	if (ret)
		pr_err("DISP/%s: errno %d\n", __func__, ret);

	if (enable == 1) {
		DDPMSG("[DDP] debug=1, trigger AEE\n");
		/* aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); */
	} else if (enable == 2) {
		ddp_mem_test();
	} else if (enable == 3) {
		ddp_lcd_test();
	} else if (enable == 4) {
		DDPAEE("test enable=%d\n", enable);
		sprintf(buf, "test enable=%d\n", enable);
	} else if (enable == 5) {

		if (gDDPError == 0)
			gDDPError = 1;
		else
			gDDPError = 0;

		sprintf(buf, "bypass PQ: %d\n", gDDPError);
		DDPMSG("bypass PQ: %d\n", gDDPError);
	} else if (enable == 6) {
		unsigned int i = 0;
		int *modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
		int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);

		pr_debug("dump path status:");
		for (i = 0; i < module_num; i++)
			pr_debug("%s-", ddp_get_module_name(modules[i]));

		pr_debug("\n");

		ddp_dump_analysis(DISP_MODULE_CONFIG);
		ddp_dump_analysis(DISP_MODULE_MUTEX);
		for (i = 0; i < module_num; i++)
			ddp_dump_analysis(modules[i]);

		if (primary_display_is_decouple_mode()) {
			ddp_dump_analysis(DISP_MODULE_OVL0);
#if defined(OVL_CASCADE_SUPPORT)
			ddp_dump_analysis(DISP_MODULE_OVL1);
#endif
			ddp_dump_analysis(DISP_MODULE_WDMA0);
		}

		ddp_dump_reg(DISP_MODULE_CONFIG);
		ddp_dump_reg(DISP_MODULE_MUTEX);

		if (primary_display_is_decouple_mode()) {
			ddp_dump_reg(DISP_MODULE_OVL0);
			ddp_dump_reg(DISP_MODULE_OVL1);
			ddp_dump_reg(DISP_MODULE_WDMA0);
		}

		for (i = 0; i < module_num; i++)
			ddp_dump_reg(modules[i]);

	} else if (enable == 7) {
		if (dbg_log_level < 3)
			dbg_log_level++;
		else
			dbg_log_level = 0;

		pr_debug("DDP: dbg_log_level=%d\n", dbg_log_level);
		sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
	} else if (enable == 8) {
		DDPDUMP("clock_mm setting:%u\n", DISP_REG_GET(DISP_REG_CONFIG_C11));
		if ((DISP_REG_GET(DISP_REG_CONFIG_C11) & 0xff000000) != 0xff000000)
			DDPDUMP("error, MM clock bit 24~bit31 should be 1, but real value=0x%x",
				DISP_REG_GET(DISP_REG_CONFIG_C11));

	} else if (enable == 9) {
		gOVLBackground = 0xFF0000FF;
		pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
		sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
	} else if (enable == 10) {
		gOVLBackground = 0xFF000000;
		pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
		sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
	} else if (enable == 11) {
		unsigned int i = 0;
		char *buf_temp = buf;

		for (i = 0; i < DISP_REG_NUM; i++) {
			DDPDUMP("i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
				i, ddp_get_reg_module_name(i), dispsys_reg[i],
				ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]);
			sprintf(buf_temp, "i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n", i,
				ddp_get_reg_module_name(i), dispsys_reg[i],
				ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]);
			buf_temp += strlen(buf_temp);
		}
	} else if (enable == 12) {
		if (gUltraEnable == 0)
			gUltraEnable = 1;
		else
			gUltraEnable = 0;

		pr_debug("DDP: gUltraEnable=%d\n", gUltraEnable);
		sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);
	} else if (enable == 13) {
		int ovl_status = ovl_get_status();

		config.type = DISP_SESSION_MEMORY;
		config.device_id = 0;
		disp_create_session(&config);
		pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
		sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status,
			ovl_get_status());
	} else if (enable == 14) {
		int ovl_status = ovl_get_status();

		disp_destroy_session(&config);
		pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
		sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status,
			ovl_get_status());
	} else if (enable == 15) {
		/* extern smi_dumpDebugMsg(void); */
		ddp_dump_analysis(DISP_MODULE_CONFIG);
		ddp_dump_analysis(DISP_MODULE_RDMA0);
		ddp_dump_analysis(DISP_MODULE_OVL0);
#if defined(OVL_CASCADE_SUPPORT)
		ddp_dump_analysis(DISP_MODULE_OVL1);
#endif

		/* dump ultra/preultra related regs */
		DDPMSG("wdma_con1(2c)=0x%x, wdma_con2(0x38)=0x%x,\n",
			DISP_REG_GET(DISP_REG_WDMA_BUF_CON1),
			DISP_REG_GET(DISP_REG_WDMA_BUF_CON2));
		DDPMSG("rdma_gmc0(30)=0x%x, rdma_gmc1(38)=0x%x, fifo_con(40)=0x%x\n",
			DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0),
			DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1),
			DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
		DDPMSG("ovl0_gmc: 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc: 0x%x, 0x%x, 0x%x, 0x%x,\n",
			DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING),
			DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING),
			DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING),
			DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING),
			DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING +
					DISP_OVL_INDEX_OFFSET),
			DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING +
					DISP_OVL_INDEX_OFFSET),
			DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING +
					DISP_OVL_INDEX_OFFSET),
			DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING +
					DISP_OVL_INDEX_OFFSET));

		/* dump smi regs */
		/* smi_dumpDebugMsg(); */

	} else if (enable == 16) {
		if (gDumpMemoutCmdq == 0)
			gDumpMemoutCmdq = 1;
		else
			gDumpMemoutCmdq = 0;

		pr_debug("DDP: gDumpMemoutCmdq=%d\n", gDumpMemoutCmdq);
		sprintf(buf, "gDumpMemoutCmdq: %d\n", gDumpMemoutCmdq);
	} else if (enable == 21) {
		if (gEnableSODIControl == 0)
			gEnableSODIControl = 1;
		else
			gEnableSODIControl = 0;

		pr_debug("DDP: gEnableSODIControl=%d\n", gEnableSODIControl);
		sprintf(buf, "gEnableSODIControl: %d\n", gEnableSODIControl);
	} else if (enable == 22) {
		if (gPrefetchControl == 0)
			gPrefetchControl = 1;
		else
			gPrefetchControl = 0;

		pr_debug("DDP: gPrefetchControl=%d\n", gPrefetchControl);
		sprintf(buf, "gPrefetchControl: %d\n", gPrefetchControl);
	} else if (enable == 23) {
		if (disp_low_power_enlarge_blanking == 0)
			disp_low_power_enlarge_blanking = 1;
		else
			disp_low_power_enlarge_blanking = 0;

		pr_debug("DDP: disp_low_power_enlarge_blanking=%d\n",
			 disp_low_power_enlarge_blanking);
		sprintf(buf, "disp_low_power_enlarge_blanking: %d\n",
			disp_low_power_enlarge_blanking);

	} else if (enable == 24) {
		if (disp_low_power_disable_ddp_clock == 0)
			disp_low_power_disable_ddp_clock = 1;
		else
			disp_low_power_disable_ddp_clock = 0;

		pr_debug("DDP: disp_low_power_disable_ddp_clock=%d\n",
			 disp_low_power_disable_ddp_clock);
		sprintf(buf, "disp_low_power_disable_ddp_clock: %d\n",
			disp_low_power_disable_ddp_clock);

	} else if (enable == 25) {
		if (disp_low_power_disable_fence_thread == 0)
			disp_low_power_disable_fence_thread = 1;
		else
			disp_low_power_disable_fence_thread = 0;

		pr_debug("DDP: disp_low_power_disable_fence_thread=%d\n",
			 disp_low_power_disable_fence_thread);
		sprintf(buf, "disp_low_power_disable_fence_thread: %d\n",
			disp_low_power_disable_fence_thread);

	} else if (enable == 26) {
		if (disp_low_power_remove_ovl == 0)
			disp_low_power_remove_ovl = 1;
		else
			disp_low_power_remove_ovl = 0;

		pr_debug("DDP: disp_low_power_remove_ovl=%d\n", disp_low_power_remove_ovl);
		sprintf(buf, "disp_low_power_remove_ovl: %d\n", disp_low_power_remove_ovl);

	} else if (enable == 27) {
		if (gSkipIdleDetect == 0)
			gSkipIdleDetect = 1;
		else
			gSkipIdleDetect = 0;

		pr_debug("DDP: gSkipIdleDetect=%d\n", gSkipIdleDetect);
		sprintf(buf, "gSkipIdleDetect: %d\n", gSkipIdleDetect);

	} else if (enable == 28) {
		if (gDumpClockStatus == 0)
			gDumpClockStatus = 1;
		else
			gDumpClockStatus = 0;

		pr_debug("DDP: gDumpClockStatus=%d\n", gDumpClockStatus);
		sprintf(buf, "gDumpClockStatus: %d\n", gDumpClockStatus);

	} else if (enable == 29) {
		if (gEnableUartLog == 0)
			gEnableUartLog = 1;
		else
			gEnableUartLog = 0;

		pr_debug("DDP: gEnableUartLog=%d\n", gEnableUartLog);
		sprintf(buf, "gEnableUartLog: %d\n", gEnableUartLog);

	} else if (enable == 30) {
		if (gEnableMutexRisingEdge == 0) {
			gEnableMutexRisingEdge = 1;
			DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING,
					   DISP_REG_CONFIG_MUTEX0_SOF, 1);
		} else {
			gEnableMutexRisingEdge = 0;
			DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING,
					   DISP_REG_CONFIG_MUTEX0_SOF, 0);
		}

		pr_debug("DDP: gEnableMutexRisingEdge=%d\n", gEnableMutexRisingEdge);
		sprintf(buf, "gEnableMutexRisingEdge: %d\n", gEnableMutexRisingEdge);

	} else if (enable == 31) {
		if (gEnableReduceRegWrite == 0)
			gEnableReduceRegWrite = 1;
		else
			gEnableReduceRegWrite = 0;

		pr_debug("DDP: gEnableReduceRegWrite=%d\n", gEnableReduceRegWrite);
		sprintf(buf, "gEnableReduceRegWrite: %d\n", gEnableReduceRegWrite);

	} else if (enable == 32) {
		DDPAEE("DDP: (32)gEnableReduceRegWrite=%d\n", gEnableReduceRegWrite);
	} else if (enable == 33) {
		if (gDumpConfigCMD == 0)
			gDumpConfigCMD = 1;
		else
			gDumpConfigCMD = 0;

		pr_debug("DDP: gDumpConfigCMD=%d\n", gDumpConfigCMD);
		sprintf(buf, "gDumpConfigCMD: %d\n", gDumpConfigCMD);

	} else if (enable == 34) {
		if (gESDEnableSODI == 0)
			gESDEnableSODI = 1;
		else
			gESDEnableSODI = 0;

		pr_debug("DDP: gESDEnableSODI=%d\n", gESDEnableSODI);
		sprintf(buf, "gESDEnableSODI: %d\n", gESDEnableSODI);

	} else if (enable == 35) {
		if (gEnableOVLStatusCheck == 0)
			gEnableOVLStatusCheck = 1;
		else
			gEnableOVLStatusCheck = 0;

		pr_debug("DDP: gEnableOVLStatusCheck=%d\n", gEnableOVLStatusCheck);
		sprintf(buf, "gEnableOVLStatusCheck: %d\n", gEnableOVLStatusCheck);

	} else if (enable == 36) {
		if (gResetRDMAEnable == 0)
			gResetRDMAEnable = 1;
		else
			gResetRDMAEnable = 0;

		pr_debug("DDP: gResetRDMAEnable=%d\n", gResetRDMAEnable);
		sprintf(buf, "gResetRDMAEnable: %d\n", gResetRDMAEnable);
	} else if (enable == 37) {
		unsigned int reg_value = 0;

		if (gEnableIRQ == 0) {
			gEnableIRQ = 1;

			DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e2);
			DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e2);

			reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
			DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
					 reg_value | (1 << 0) | (1 << DISP_MUTEX_TOTAL));
		} else {
			gEnableIRQ = 0;

			DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e0);
			DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e0);

			reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
			DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
					 reg_value & (~(1 << 0)) &
					 (~(1 << DISP_MUTEX_TOTAL)));

		}

		pr_debug("DDP: gEnableIRQ=%d\n", gEnableIRQ);
		sprintf(buf, "gEnableIRQ: %d\n", gEnableIRQ);

	} else if (enable == 38) {
		if (gDisableSODIForTriggerLoop == 0)
			gDisableSODIForTriggerLoop = 1;
		else
			gDisableSODIForTriggerLoop = 0;

		pr_debug("DDP: gDisableSODIForTriggerLoop=%d\n",
			 gDisableSODIForTriggerLoop);
		sprintf(buf, "gDisableSODIForTriggerLoop: %d\n",
			gDisableSODIForTriggerLoop);

	} else if (enable == 39) {
		cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_STREAM_EOF);
		cmdqCoreSetEvent(CMDQ_EVENT_DISP_RDMA0_EOF);
		sprintf(buf, "enable=%d\n", enable);
	} else if (enable == 41) {
		if (gResetOVLInAALTrigger == 0)
			gResetOVLInAALTrigger = 1;
		else
			gResetOVLInAALTrigger = 0;

		pr_debug("DDP: gResetOVLInAALTrigger=%d\n", gResetOVLInAALTrigger);
		sprintf(buf, "gResetOVLInAALTrigger: %d\n", gResetOVLInAALTrigger);

	} else if (enable == 42) {
		if (gDisableOVLTF == 0)
			gDisableOVLTF = 1;
		else
			gDisableOVLTF = 0;

		pr_debug("DDP: gDisableOVLTF=%d\n", gDisableOVLTF);
		sprintf(buf, "gDisableOVLTF: %d\n", gDisableOVLTF);

	} else if (enable == 43) {
		if (gDumpESDCMD == 0)
			gDumpESDCMD = 1;
		else
			gDumpESDCMD = 0;

		pr_debug("DDP: gDumpESDCMD=%d\n", gDumpESDCMD);
		sprintf(buf, "gDumpESDCMD: %d\n", gDumpESDCMD);

	} else if (enable == 44) {
		/* extern void disp_dump_emi_status(void); */
		disp_dump_emi_status();
		sprintf(buf, "dump emi status!\n");
	} else if (enable == 40) {
		sprintf(buf, "version: %d, %s\n", 7, __TIME__);
	} else if (enable == 45) {
		ddp_aee_print("DDP AEE DUMP!!\n");
	} else if (enable == 46) {
		ASSERT(0);
	} else if (enable == 47) {
		if (gEnableDSIStateCheck == 0)
			gEnableDSIStateCheck = 1;
		else
			gEnableDSIStateCheck = 0;

		pr_debug("DDP: gEnableDSIStateCheck=%d\n", gEnableDSIStateCheck);
		sprintf(buf, "gEnableDSIStateCheck: %d\n", gEnableDSIStateCheck);
	} else if (enable == 48) {
		if (gMutexFreeRun == 0)
			gMutexFreeRun = 1;
		else
			gMutexFreeRun = 0;

		pr_debug("DDP: gMutexFreeRun=%d\n", gMutexFreeRun);
		sprintf(buf, "gMutexFreeRun: %d\n", gMutexFreeRun);
	}
}