void CSP_TmrIntClr (CSP_DEV_NBR tmr_nbr)
{
CSP_TMR_REG *p_tmr_reg;
CSP_DEV_NBR match_nbr;
CPU_INT32U reg_msk;
CPU_INT32U reg_stat;
CPU_INT32U reg_clr;
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
if (tmr_nbr > CSP_TMR_NBR_03) {
return;
}
#endif
p_tmr_reg = (CSP_TMR_REG *)CSP_TmrAddrTbl[tmr_nbr];
reg_clr = DEF_BIT_NONE;
reg_msk = p_tmr_reg->MCR;
reg_stat = p_tmr_reg->IR;
for (match_nbr = 0; match_nbr <= CSP_TMR_MATCH_NBR_03; match_nbr++) {
if ((DEF_BIT_IS_SET(reg_msk, CSP_TMR_BIT_MCR_MRIx(match_nbr)) == DEF_YES) &&
(DEF_BIT_IS_SET(reg_stat, DEF_BIT(match_nbr)) == DEF_YES)) {
DEF_BIT_SET(reg_clr, DEF_BIT(match_nbr));
}
}
p_tmr_reg->IR = reg_clr;
}
CPU_BOOLEAN CSP_DMA_XferStartExt (CSP_DEV_NBR ch_nbr,
void *p_dest,
void *p_src,
CPU_SIZE_T xfer_size,
CSP_OPT_FLAGS opt)
{
CSP_DMA_REG *p_dma_reg;
CSP_DMA_CH_REG *p_dma_ch_reg;
CPU_INT32U reg_ctrl;
CPU_SR_ALLOC();
/* ------------------ ARGUMENTS CHECKING -------------- */
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
if (ch_nbr > CSP_DMA_CH_MAX_NBR - 1u) { /* Invalid channel number? */
return (DEF_FAIL);
}
/* Channel not available? */
if (CSP_DMA_ChTbl[ch_nbr].State != CSP_DMA_CH_STATE_ALLOC) {
return (DEF_FAIL);
}
if ((p_dest == (void *)0) || /* Null pointers? */
(p_src == (void *)0)) {
return (DEF_FAIL);
}
#endif
p_dma_reg = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
reg_ctrl = p_dma_ch_reg->Ctrl;
DEF_BIT_CLR(reg_ctrl, CSP_DMA_MSK_CH_CTRL_XFER_SIZE |
CSP_DMA_BIT_CH_CTRL_SI |
CSP_DMA_BIT_CH_CTRL_DI |
CSP_DMA_BIT_CH_CTRL_I);
DEF_BIT_SET(reg_ctrl, (xfer_size & CSP_DMA_MSK_CH_CTRL_XFER_SIZE));
if (DEF_BIT_IS_SET(opt, CSP_DMA_OPT_FLAG_XFER_SRC_INC)) {
DEF_BIT_SET(reg_ctrl, CSP_DMA_BIT_CH_CTRL_SI);
}
if (DEF_BIT_IS_SET(opt, CSP_DMA_OPT_FLAG_XFER_DEST_INC)) {
DEF_BIT_SET(reg_ctrl, CSP_DMA_BIT_CH_CTRL_DI);
}
CPU_CRITICAL_ENTER();
p_dma_ch_reg->SrcAddr = (CPU_INT32U )p_src;
p_dma_ch_reg->DestAddr = (CPU_INT32U )p_dest;
p_dma_ch_reg->Ctrl = reg_ctrl;
DEF_BIT_CLR(p_dma_ch_reg->Cfg, CSP_DMA_BIT_CH_CFG_ITC |
CSP_DMA_BIT_CH_CFG_IE);
DEF_BIT_SET(p_dma_ch_reg->Cfg, CSP_DMA_BIT_CH_CFG_CH_EN);
CPU_CRITICAL_EXIT();
return (DEF_OK);
}
static void BSP_PLL_Init (void)
{
CPU_REG32 reg_val;
CPU_SR_ALLOC();
CPU_CRITICAL_ENTER();
/* System clock divider configuration. */
BSP_REG_SIM_CLKDIV1 = (BSP_SIM_CLKDIV1_OUTDIV1_DIV2 | /* Clock 1 divide by 2. */
BSP_SIM_CLKDIV1_OUTDIV4_DIV2); /* Clock 4 divide by 2. */
/* Multipurpose clock generator configuration. */
BSP_REG_MCG_C2 = (BSP_MCG_C2_LOCRE0 | /* Generate a reset request on a loss of ext ref clk. */
BSP_MCG_C2_RANGE_HIGH_FREQ | /* Select high freq range for the crystal oscillator. */
BSP_MCG_C2_EREFS0); /* Select oscillator as the source for the ext ref clk. */
BSP_REG_MCG_C1 = (BSP_MCG_C1_CLKS_EXT_CLK | /* Selects the ext ref clk as the clk source for MCG. */
BSP_MCG_C1_FRDIV_8); /* Divide the ext ref clk by 256 for the FLL. */
while (DEF_BIT_IS_SET(BSP_REG_MCG_S, BSP_MCG_S_IREFST)) { /* Wait for Reference clock Status bit to clear. */
;
}
do { /* Wait for clock status bits to show clock. */
reg_val = (BSP_REG_MCG_S & BSP_MCG_S_CLKST_MASK) >> 2u; /* source is ext ref clk. */
} while (reg_val != 0x2);
/* --------------------- PLL0 CFG --------------------- */
BSP_REG_MCG_C5 = BSP_MCG_C5_PRDIV0_4; /* Select PLL0 external reference divider. */
BSP_REG_MCG_C6 = (BSP_MCG_C6_PLLS | /* Select the PLL output. */
BSP_MCG_C6_CME0 | /* Enable the loss of clock monitoring circuit. */
BSP_MCG_C6_VDIV0_MUL_48);
while (DEF_BIT_IS_CLR(BSP_REG_MCG_S, BSP_MCG_S_PLLST)) { /* Wait for PLL status bit to set. */
;
}
while (DEF_BIT_IS_CLR(BSP_REG_MCG_S, BSP_MCG_S_LOCK0)) { /* Wait for LOCK bit to set. */
;
}
DEF_BIT_CLR(BSP_REG_MCG_C1, BSP_MCG_C1_CLKS_MASK); /* Clear CLKS to switch CLKS mux to PLL as MCG_OUT. */
do {
reg_val = (BSP_REG_MCG_S & BSP_MCG_S_CLKST_MASK) >> 2u;
} while (reg_val != 0x3); /* Wait for clock status bits to update. */
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Set PLLFLLSEL to select the PLL for this clk src. */
CPU_CRITICAL_EXIT();
}
CPU_SIZE_T BSP_SerWr (CPU_DATA port_id,
void *p_src,
CPU_SIZE_T size)
{
LM3SXXXX_STRUCT_UART *uart;
CPU_INT08U *p_src_08;
CPU_SIZE_T cnt;
CPU_INT08U datum;
CPU_INT32U fr;
if (port_id > BSP_SER_PORT_NBR_MAX) {
return (DEF_NO);
}
switch (port_id) {
case BSP_SER_ID_UART0:
uart = (LM3SXXXX_STRUCT_UART *)LM3SXXXX_BASE_UART0;
break;
#if (BSP_SER_PORT_NBR_MAX >= BSP_SER_ID_UART1)
case BSP_SER_ID_UART1:
uart = (LM3SXXXX_STRUCT_UART *)LM3SXXXX_BASE_UART1;
break;
#endif
#if (BSP_SER_PORT_NBR_MAX >= BSP_SER_ID_UART2)
case BSP_SER_ID_UART2:
uart = (LM3SXXXX_STRUCT_UART *)LM3SXXXX_BASE_UART2;
break;
#endif
default:
return (0u);
}
p_src_08 = (CPU_INT08U *)p_src;
cnt = 0u;
while (cnt < size) {
fr = uart->FR;
while (DEF_BIT_IS_SET(fr, LM3SXXXX_BIT_UARTFR_TXFF) == DEF_YES) {
BSP_OS_Dly_ms(1u);
fr = uart->FR;
}
datum = *p_src_08;
uart->DR = datum;
p_src_08++;
cnt++;
}
return (cnt);
}
CPU_SIZE_T BSP_SerRdLine(CPU_DATA port_id,
void *p_dest,
CPU_SIZE_T size)
{
LM3SXXXX_STRUCT_UART *uart;
CPU_INT08U *p_dest_08;
CPU_SIZE_T cnt;
CPU_INT08U datum;
CPU_INT32U fr;
CPU_BOOLEAN print;
if (port_id > BSP_SER_PORT_NBR_MAX) {
return (DEF_NO);
}
switch (port_id) {
case BSP_SER_ID_UART0:
uart = (LM3SXXXX_STRUCT_UART *)LM3SXXXX_BASE_UART0;
break;
#if (BSP_SER_PORT_NBR_MAX >= BSP_SER_ID_UART1)
case BSP_SER_ID_UART1:
uart = (LM3SXXXX_STRUCT_UART *)LM3SXXXX_BASE_UART1;
break;
#endif
#if (BSP_SER_PORT_NBR_MAX >= BSP_SER_ID_UART2)
case BSP_SER_ID_UART2:
uart = (LM3SXXXX_STRUCT_UART *)LM3SXXXX_BASE_UART2;
break;
#endif
default:
return (0u);
}
p_dest_08 = (CPU_INT08U *)p_dest;
cnt = 0u;
while (cnt < size - 1u) {
fr = uart->FR;
while (DEF_BIT_IS_SET(fr, LM3SXXXX_BIT_UARTFR_RXFE) == DEF_YES) {
BSP_OS_Dly_ms(1u);
fr = uart->FR;
}
datum = (CPU_INT08U)uart->DR;
print = ASCII_IS_PRINT(datum);
if (print == DEF_YES) {
*p_dest_08 = datum;
p_dest_08++;
BSP_SerWr(port_id, (void *)&datum, 1);
} else {
if (datum == ASCII_CHAR_BACKSPACE) {
if (cnt > 0u) {
BSP_SerWr(port_id, (void *)"\b \b", 3);
cnt--;
}
} else if (datum == ASCII_CHAR_CARRIAGE_RETURN) {
*p_dest_08 = (CPU_CHAR)ASCII_CHAR_NULL;
return (cnt);
}
}
cnt++;
}
*p_dest_08 = (CPU_CHAR)ASCII_CHAR_NULL;
return (cnt);
}
void BSP_Init (void)
{
CPU_INT16U reg_to;
CPU_INT32U reg_val;
CPU_SR_ALLOC();
/* ---------------- CLOCK INITIALIZATION -------------- */
BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_6 /* Set 6 cycles to acces the Flash memory. */
| BSP_MSK_FLASHCFG_RST_VAL;
/* ----------- MAIN OSCILLATOR INITIALIZATION --------- */
DEF_BIT_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCRANGE); /* Set the main oscillator range */
reg_to = BSP_VAL_MAX_TO;
DEF_BIT_SET(BSP_REG_SCS, BSP_BIT_SCS_OSCEN); /* Enable the Main Oscillator */
/* Wait until the main oscillator is enabled. */
while (DEF_BIT_IS_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCSTAT) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) { /* Configuration fail */
return;
}
BSP_REG_PCLKSEL0 = DEF_BIT_NONE; /* All peripheral clock runrs at CPU_Clk / 4 = 25 Mhz */
BSP_REG_PCLKSEL1 = DEF_BIT_NONE;
/* ------------------ PLL0 CONFIGURATION -------------- */
reg_val = (((25u - 1u) << 0u) & BSP_MSK_PLLCFG0_MSEL) /* PLL0 values M = 25 & N = 2 (see note #6) */
| ((( 2u - 1u) << 16u) & BSP_MSK_PLLCFG0_NSEL);
/* 1. Disconnect PLL0 with one feed sequence if PLL ... */
/* ... already connected. */
if (DEF_BIT_IS_SET(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLLC0_STAT)) {
DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);
BSP_PLL_FEED_SEQ(0u);
}
DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE); /* 2. Disable PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
BSP_REG_CCLKCFG = (1u - 1u); /* 3. Change the CPU clock divider setting to speed ... */
/* ... operation without PLL0 */
BSP_REG_CLKSRCSEL = BSP_BIT_CLKSRCSEL_MAIN; /* 4. Select the main osc. as the PLL0 clock source */
BSP_REG_PLLCFG(0u) = reg_val; /* 5. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(0u) /* ... one one feed sequence */
DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE); /* 6. Enable PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
BSP_REG_CCLKCFG = (3u - 1u); /* 7. Change the CPU clock divider setting for ... */
/* ... operation with PLL0 */
reg_to = BSP_VAL_MAX_TO; /* 8. Wait for PLL0 to achieve lock by monitoring ... */
/* ... the PLOCK0 bit in the PLL0STAT */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLOCK0) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) {
return;
}
DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC); /* 9. Connect PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
/* ------------------ PLL1 CONFIGURATION -------------- */
reg_val = (((4u - 1u) << 0u) & BSP_MSK_PLLCFG1_MSEL) /* PLL1 values M = 4; P = 2 coded as '01' (see note #6) */
| (((0x01u ) << 5u) & BSP_MSK_PLLCFG1_NSEL);
DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC); /* 1. Disconnect PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE); /* 2. Disable PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
BSP_REG_PLLCFG(1u) = reg_val; /* 3. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(1u); /* ... one one feed sequence */
DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE); /* 4. Enable PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
reg_to = BSP_VAL_MAX_TO; /* 5. Wait for PLL1 to achieve lock by monitoring ... */
/* ... the PLOCK1 bit in the PLL1STAT */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(1u), BSP_BIT_PLLSTAT_PLOCK1) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) {
return;
}
DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC); /* 6. Connect PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_5 /* Set 5 cycles to acces the Flash memory. */
| BSP_MSK_FLASHCFG_RST_VAL;
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_00,
BSP_GPIO0_LED2,
CSP_GPIO_DIR_OUT,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_01,
BSP_GPIO1_LED1,
CSP_GPIO_DIR_OUT,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_00,
BSP_GPIO0_BUT1,
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_02,
BSP_GPIO2_BUT2,
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
BSP_LED_Off(0);
CSP_GPIO_Cfg( CSP_GPIO_PORT_NBR_02,
(BSP_GPIO2_JOY_RIGHT |
BSP_GPIO2_JOY_DOWN |
BSP_GPIO2_JOY_LEFT |
BSP_GPIO2_JOY_RIGHT),
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg( CSP_GPIO_PORT_NBR_00,
BSP_GPIO0_JOY_CENTER,
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_IntInit();
CSP_IntDisAll(CSP_INT_CTRL_NBR_MAIN);
}
void OSTimeDlyHMSM (CPU_INT16U hours,
CPU_INT16U minutes,
CPU_INT16U seconds,
CPU_INT32U milli,
OS_OPT opt,
OS_ERR *p_err)
{
#if OS_CFG_ARG_CHK_EN > 0u
CPU_BOOLEAN opt_invalid;
CPU_BOOLEAN opt_non_strict;
#endif
OS_OPT opt_time;
OS_RATE_HZ tick_rate;
OS_TICK ticks;
CPU_SR_ALLOC();
#ifdef OS_SAFETY_CRITICAL
if (p_err == (OS_ERR *)0) {
OS_SAFETY_CRITICAL_EXCEPTION();
return;
}
#endif
#if OS_CFG_CALLED_FROM_ISR_CHK_EN > 0u
if (OSIntNestingCtr > (OS_NESTING_CTR)0u) { /* Not allowed to call from an ISR */
*p_err = OS_ERR_TIME_DLY_ISR;
return;
}
#endif
if (OSSchedLockNestingCtr > (OS_NESTING_CTR)0u) { /* Can't delay when the scheduler is locked */
*p_err = OS_ERR_SCHED_LOCKED;
return;
}
opt_time = opt & OS_OPT_TIME_MASK; /* Retrieve time options only. */
switch (opt_time) {
case OS_OPT_TIME_DLY:
case OS_OPT_TIME_TIMEOUT:
case OS_OPT_TIME_PERIODIC:
if (milli == (CPU_INT32U)0u) { /* Make sure we didn't specify a 0 delay */
if (seconds == (CPU_INT16U)0u) {
if (minutes == (CPU_INT16U)0u) {
if (hours == (CPU_INT16U)0u) {
*p_err = OS_ERR_TIME_ZERO_DLY;
return;
}
}
}
}
break;
case OS_OPT_TIME_MATCH:
break;
default:
*p_err = OS_ERR_OPT_INVALID;
return;
}
#if OS_CFG_ARG_CHK_EN > 0u /* Validate arguments to be within range */
opt_invalid = DEF_BIT_IS_SET_ANY(opt, ~OS_OPT_TIME_OPTS_MASK);
if (opt_invalid == DEF_YES) {
*p_err = OS_ERR_OPT_INVALID;
return;
}
opt_non_strict = DEF_BIT_IS_SET(opt, OS_OPT_TIME_HMSM_NON_STRICT);
if (opt_non_strict != DEF_YES) {
if (milli > (CPU_INT32U)999u) {
*p_err = OS_ERR_TIME_INVALID_MILLISECONDS;
return;
}
if (seconds > (CPU_INT16U)59u) {
*p_err = OS_ERR_TIME_INVALID_SECONDS;
return;
}
if (minutes > (CPU_INT16U)59u) {
*p_err = OS_ERR_TIME_INVALID_MINUTES;
return;
}
if (hours > (CPU_INT16U)99u) {
*p_err = OS_ERR_TIME_INVALID_HOURS;
return;
}
} else {
if (minutes > (CPU_INT16U)9999u) {
*p_err = OS_ERR_TIME_INVALID_MINUTES;
return;
}
if (hours > (CPU_INT16U)999u) {
*p_err = OS_ERR_TIME_INVALID_HOURS;
return;
}
}
#endif
/* Compute the total number of clock ticks required.. */
/* .. (rounded to the nearest tick) */
tick_rate = OSCfg_TickRate_Hz;
ticks = ((OS_TICK)hours * (OS_TICK)3600u + (OS_TICK)minutes * (OS_TICK)60u + (OS_TICK)seconds) * tick_rate
+ (tick_rate * ((OS_TICK)milli + (OS_TICK)500u / tick_rate)) / (OS_TICK)1000u;
if (ticks > (OS_TICK)0u) {
OS_CRITICAL_ENTER();
OSTCBCurPtr->TaskState = OS_TASK_STATE_DLY;
OS_TickListInsert(OSTCBCurPtr,
ticks,
opt_time,
p_err);
if (*p_err != OS_ERR_NONE) {
OS_CRITICAL_EXIT_NO_SCHED();
return;
}
OS_RdyListRemove(OSTCBCurPtr); /* Remove current task from ready list */
OS_CRITICAL_EXIT_NO_SCHED();
OSSched(); /* Find next task to run! */
*p_err = OS_ERR_NONE;
} else {
*p_err = OS_ERR_TIME_ZERO_DLY;
}
}
static void CSP_DMA_IntHandler (void *p_arg)
{
CSP_DMA_REG *p_dma_reg;
CSP_DMA_CH_REG *p_dma_ch_reg;
CSP_DMA_CH *p_dma_ch;
void *p_callback_arg;
CSP_DMA_CALLBACK_PTR callback_fnct;
CSP_DEV_NBR ch_nbr;
CPU_INT32U int_tc_stat;
CPU_INT32U int_err_stat;
CPU_BOOLEAN status;
CPU_INT16U xfer_size_rem;
p_dma_reg = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;
int_tc_stat = p_dma_reg->IntTCStat & DEF_BIT_FIELD(8u, 0u);
int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);
/* --------- INTERRUPT TERMINAL COUNT HANDLING -------- */
while (int_tc_stat != DEF_BIT_NONE) {
/* Get current DMA channel number */
ch_nbr = 31u - CPU_CntLeadZeros(int_tc_stat);
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
p_dma_ch = &(CSP_DMA_ChTbl[ch_nbr]);
callback_fnct = p_dma_ch->CallBackFnctPtr; /* Get the callback function */
p_callback_arg = p_dma_ch->CallBackArgPtr; /* Get the callback argument pointer. */
/* Get the remaining transfer size. */
xfer_size_rem = p_dma_ch_reg->Ctrl & DEF_BIT_FIELD(12u, 0u);
p_dma_reg->IntTCClr = DEF_BIT(ch_nbr); /* Clear the terminal count interrupt. */
if (DEF_BIT_IS_SET(int_err_stat, DEF_BIT(ch_nbr))) { /* If an error occured in the channel... */
status = DEF_FAIL; /* ... set the status, and clear the error interrupt. */
p_dma_reg->IntErrClr = DEF_BIT(ch_nbr);
} else {
status = DEF_OK;
}
callback_fnct(ch_nbr, /* Call the callback function. */
xfer_size_rem,
p_callback_arg,
status);
/* Read the terminal count and error interrupts status */
int_tc_stat = p_dma_reg->IntTCStat & DEF_BIT_FIELD(8u, 0u);
int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);
}
/* --------------- ERROR INTERRUPT HANDLING ------------ */
int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);
while (int_err_stat != DEF_BIT_NONE) {
ch_nbr = 31u - CPU_CntLeadZeros(int_err_stat);
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
p_dma_ch = &(CSP_DMA_ChTbl[ch_nbr]);
callback_fnct = p_dma_ch->CallBackFnctPtr;
p_callback_arg = p_dma_ch->CallBackArgPtr;
p_dma_ch->State = CSP_DMA_CH_STATE_ALLOC; /* Set the channel state = 'ALLOC' */
xfer_size_rem = p_dma_ch_reg->Ctrl & DEF_BIT_FIELD(12u, 0u);
status = DEF_FAIL;
p_dma_reg->IntErrClr = DEF_BIT(ch_nbr);
callback_fnct(ch_nbr,
xfer_size_rem,
p_callback_arg,
status);
int_err_stat = p_dma_reg->IntErrStat & DEF_BIT_FIELD(8u, 0u);
}
}
CPU_BOOLEAN CSP_DMA_XferAsyncStartExt (CSP_DEV_NBR ch_nbr,
void *p_dest,
void *p_src,
CPU_SIZE_T xfer_size,
CSP_DMA_CALLBACK_PTR callback,
void *p_arg,
CSP_OPT_FLAGS opt)
{
CSP_DMA_REG *p_dma_reg;
CSP_DMA_CH_REG *p_dma_ch_reg;
CSP_DMA_CH *p_dma_ch;
CPU_INT32U reg_ctrl;
CPU_SR_ALLOC();
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
if (ch_nbr > CSP_DMA_CH_MAX_NBR - 1u) { /* Invalid channel number? */
return (DEF_FAIL);
}
/* Channel not available? */
if (CSP_DMA_ChTbl[ch_nbr].State != CSP_DMA_CH_STATE_ALLOC) {
return (DEF_FAIL);
}
if (callback == (CSP_DMA_CALLBACK_PTR )0) {
return (DEF_FAIL);
}
if ((p_dest == (void *)0) ||
(p_src == (void *)0)) {
return (DEF_FAIL);
}
#endif
p_dma_reg = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;
p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
p_dma_ch = &(CSP_DMA_ChTbl[ch_nbr]);
reg_ctrl = p_dma_ch_reg->Ctrl;
DEF_BIT_CLR(reg_ctrl, CSP_DMA_MSK_CH_CTRL_XFER_SIZE | /* Clears the xfer size mask. */
CSP_DMA_BIT_CH_CTRL_SI | /* Clears the source increment flag. */
CSP_DMA_BIT_CH_CTRL_DI); /* Clears the destination increment flag. */
DEF_BIT_SET(reg_ctrl, xfer_size & CSP_DMA_MSK_CH_CTRL_XFER_SIZE);
DEF_BIT_SET(reg_ctrl, CSP_DMA_BIT_CH_CTRL_I);
if (DEF_BIT_IS_SET(opt, CSP_DMA_OPT_FLAG_XFER_SRC_INC)) {
DEF_BIT_SET(reg_ctrl, CSP_DMA_BIT_CH_CTRL_SI);
}
if (DEF_BIT_IS_SET(opt, CSP_DMA_OPT_FLAG_XFER_DEST_INC)) {
DEF_BIT_SET(reg_ctrl, CSP_DMA_BIT_CH_CTRL_DI);
}
CPU_CRITICAL_ENTER();
p_dma_ch_reg->SrcAddr = (CPU_INT32U )p_src;
p_dma_ch_reg->DestAddr = (CPU_INT32U )p_dest;
p_dma_ch->CallBackFnctPtr = callback;
p_dma_ch->CallBackArgPtr = p_arg;
p_dma_ch_reg->Ctrl = reg_ctrl;
DEF_BIT_SET(p_dma_ch_reg->Cfg, CSP_DMA_BIT_CH_CFG_ITC |
CSP_DMA_BIT_CH_CFG_IE);
DEF_BIT_SET(p_dma_ch_reg->Cfg, CSP_DMA_BIT_CH_CFG_CH_EN);
CPU_CRITICAL_EXIT();
return (DEF_OK);
}
void HTTPsConn_Process (HTTPs_INSTANCE *p_instance)
{
const HTTPs_CFG *p_cfg;
HTTPs_CONN *p_conn;
HTTPs_CONN *p_conn_next;
CPU_BOOLEAN done;
CPU_BOOLEAN hook_def;
CPU_BOOLEAN process;
CPU_BOOLEAN rdy_rd;
CPU_BOOLEAN rdy_wr;
CPU_BOOLEAN rdy_err;
#if (HTTPs_CFG_PERSISTENT_CONN_EN == DEF_ENABLED)
CPU_BOOLEAN persistent;
#endif
p_cfg = p_instance->CfgPtr;
p_conn = p_instance->ConnFirstPtr;
while (p_conn != DEF_NULL) { /* For each accepted conn. */
rdy_rd = DEF_BIT_IS_SET(p_conn->SockFlags, HTTPs_FLAG_SOCK_RDY_RD);
rdy_wr = DEF_BIT_IS_SET(p_conn->SockFlags, HTTPs_FLAG_SOCK_RDY_WR);
rdy_err = DEF_BIT_IS_SET(p_conn->SockFlags, HTTPs_FLAG_SOCK_RDY_ERR);
p_conn_next = p_conn->ConnNextPtr; /* Req'd since cur conn can be closed. */
if ((rdy_rd == DEF_YES) || /* If conn sock rdy. */
(rdy_wr == DEF_YES) ||
(rdy_err == DEF_YES)) {
/* ---------------- CONN SOCK PROCESS ----------------- */
switch (p_conn->SockState) {
case HTTPs_SOCK_STATE_NONE: /* No data to rx or tx. */
process = DEF_YES;
break;
case HTTPs_SOCK_STATE_RX: /* Rx data. */
process = HTTPsSock_ConnDataRx(p_instance, p_conn);
break;
case HTTPs_SOCK_STATE_TX: /* Tx data from buf. */
process = HTTPsSock_ConnDataTx(p_instance, p_conn);
break;
case HTTPs_SOCK_STATE_ERR: /* Fatal err. */
case HTTPs_SOCK_STATE_CLOSE: /* Transaction completed. */
default:
HTTPsConn_Close(p_instance, p_conn);
process = DEF_NO;
break;
}
/* ------------ UPDATE CONN & PREPARE DATA ------------ */
if (process == DEF_YES) {
switch (p_conn->State) {
case HTTPs_CONN_STATE_REQ_INIT: /* Receive and parse request. */
case HTTPs_CONN_STATE_REQ_PARSE_METHOD:
case HTTPs_CONN_STATE_REQ_PARSE_URI:
case HTTPs_CONN_STATE_REQ_PARSE_QUERY_STRING:
case HTTPs_CONN_STATE_REQ_PARSE_PROTOCOL_VERSION:
case HTTPs_CONN_STATE_REQ_PARSE_HDR:
case HTTPs_CONN_STATE_REQ_LINE_HDR_HOOK:
HTTPsReq_Handle(p_instance, p_conn);
break;
case HTTPs_CONN_STATE_REQ_BODY_INIT: /* Process request body. */
case HTTPs_CONN_STATE_REQ_BODY_DATA:
case HTTPs_CONN_STATE_REQ_BODY_FLUSH_DATA:
case HTTPs_CONN_STATE_REQ_BODY_FORM_APP_PARSE:
case HTTPs_CONN_STATE_REQ_BODY_FORM_MULTIPART_INIT:
case HTTPs_CONN_STATE_REQ_BODY_FORM_MULTIPART_PARSE:
case HTTPs_CONN_STATE_REQ_BODY_FORM_MULTIPART_FILE_OPEN:
case HTTPs_CONN_STATE_REQ_BODY_FORM_MULTIPART_FILE_WR:
HTTPsReq_Body(p_instance, p_conn);
break;
/* Prepare response. */
case HTTPs_CONN_STATE_REQ_READY_SIGNAL:
case HTTPs_CONN_STATE_REQ_READY_POLL:
done = HTTPsReq_RdySignal(p_instance, p_conn);
if (done == DEF_YES) {
p_conn->State = HTTPs_CONN_STATE_RESP_PREPARE;
}
break;
case HTTPs_CONN_STATE_RESP_PREPARE:
done = HTTPsResp_Prepare(p_instance, p_conn);
if (done == DEF_YES) {
p_conn->State = HTTPs_CONN_STATE_RESP_INIT;
}
break;
case HTTPs_CONN_STATE_RESP_INIT: /* Build and transmit response. */
case HTTPs_CONN_STATE_RESP_TOKEN:
case HTTPs_CONN_STATE_RESP_STATUS_LINE:
case HTTPs_CONN_STATE_RESP_HDR:
case HTTPs_CONN_STATE_RESP_HDR_CONTENT_TYPE:
case HTTPs_CONN_STATE_RESP_HDR_FILE_TRANSFER:
case HTTPs_CONN_STATE_RESP_HDR_LOCATION:
case HTTPs_CONN_STATE_RESP_HDR_CONN:
case HTTPs_CONN_STATE_RESP_HDR_LIST:
case HTTPs_CONN_STATE_RESP_HDR_TX:
case HTTPs_CONN_STATE_RESP_HDR_END:
case HTTPs_CONN_STATE_RESP_FILE_STD:
case HTTPs_CONN_STATE_RESP_DATA_CHUNCKED:
case HTTPs_CONN_STATE_RESP_DATA_CHUNCKED_TX_TOKEN:
case HTTPs_CONN_STATE_RESP_DATA_CHUNCKED_TX_LAST_CHUNK:
case HTTPs_CONN_STATE_RESP_DATA_CHUNCKED_HOOK:
case HTTPs_CONN_STATE_RESP_DATA_CHUNCKED_FINALIZE:
case HTTPs_CONN_STATE_RESP_COMPLETED:
done = HTTPsResp_Handle(p_instance, p_conn);
if (done == DEF_YES) {
p_conn->State = HTTPs_CONN_STATE_COMPLETED;
}
break;
case HTTPs_CONN_STATE_COMPLETED: /* Transaction completed. */
#if (HTTPs_CFG_PERSISTENT_CONN_EN == DEF_ENABLED)
persistent = DEF_BIT_IS_SET(p_conn->Flags, HTTPs_FLAG_CONN_PERSISTENT);
if ((p_cfg->ConnPersistentEn == DEF_ENABLED) &&
(persistent == DEF_YES) ) {
HTTPsMem_ConnClr(p_instance, p_conn);
p_conn->SockState = HTTPs_SOCK_STATE_RX;
p_conn->State = HTTPs_CONN_STATE_REQ_INIT;
} else {
p_conn->SockState = HTTPs_SOCK_STATE_CLOSE;
}
#else
p_conn->SockState = HTTPs_SOCK_STATE_CLOSE;
#endif
hook_def = HTTPs_HOOK_DEFINED(p_cfg->HooksPtr, OnTransCompleteHook);
if (hook_def == DEF_YES) {
p_cfg->HooksPtr->OnTransCompleteHook(p_instance, p_conn, p_cfg->Hooks_CfgPtr);
}
break;
case HTTPs_CONN_STATE_ERR_INTERNAL:
HTTPsConn_ErrInternal(p_instance, p_conn);
p_conn->SockState = HTTPs_SOCK_STATE_CLOSE;
break;
case HTTPs_CONN_STATE_UNKNOWN:
p_conn->State = HTTPs_CONN_STATE_ERR_FATAL;
p_conn->ErrCode = HTTPs_ERR_STATE_UNKNOWN;
break;
case HTTPs_CONN_STATE_ERR_FATAL: /* Fatal err. */
default:
p_conn->SockState = HTTPs_SOCK_STATE_CLOSE;
break;
}
}
}
p_conn = p_conn_next; /* Move to next accepted conn. */
}
}
static CPU_BOOLEAN BSP_CPU_Init (void)
{
CPU_INT16U reg_to;
CPU_INT32U reg_val;
CPU_SR_ALLOC();
BSP_REG_FLASHCFG = (CPU_INT32U)BSP_MSK_FLASHCFG_CLK_6; /* Set 6 cycles to acces the Flash memory (Safe setting)*/
/* ----------- MAIN OSCILLATOR INITIALIZATION --------- */
DEF_BIT_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCRANGE); /* Set the main oscillator range */
reg_to = BSP_VAL_MAX_TO;
DEF_BIT_SET(BSP_REG_SCS, BSP_BIT_SCS_OSCEN); /* Enable the Main Oscillator */
/* Wait until the main oscillator is enabled. */
while (DEF_BIT_IS_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCSTAT) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) { /* Configuration fail */
return (DEF_FAIL);
}
BSP_REG_PCLKSEL0 = DEF_BIT_NONE; /* All peripheral clock runs at CPU_Clk / 4 = 25 Mhz. */
BSP_REG_PCLKSEL1 = DEF_BIT_NONE;
/* ------------------ PLL0 CONFIGURATION -------------- */
reg_val = (((25u - 1u) << 0u) & BSP_MSK_PLLCFG0_MSEL) /* PLL0 values M = 25 & N = 2 (see note #6) */
| ((( 2u - 1u) << 16u) & BSP_MSK_PLLCFG0_NSEL);
/* 1. Disconnect PLL0 with one feed sequence if PLL ... */
/* ... already connected. */
if (DEF_BIT_IS_SET(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLLC0_STAT)) {
DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);
BSP_PLL_FEED_SEQ(0u);
}
DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE); /* 2. Disable PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
BSP_REG_CCLKCFG = (1u - 1u); /* 3. Change the CPU clock divider setting to speed ... */
/* ... operation without PLL0 */
BSP_REG_CLKSRCSEL = BSP_BIT_CLKSRCSEL_MAIN; /* 4. Select the main osc. as the PLL0 clock source */
BSP_REG_PLLCFG(0u) = reg_val; /* 5. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(0u) /* ... one one feed sequence */
DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE); /* 6. Enable PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
BSP_REG_CCLKCFG = (3u - 1u); /* 7. Change the CPU clock divider setting for ... */
/* ... operation with PLL0 */
reg_to = BSP_VAL_MAX_TO; /* 8. Wait for PLL0 to achieve lock by monitoring ... */
/* ... the PLOCK0 bit in the PLL0STAT */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLOCK0) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) {
return (DEF_FAIL);
}
DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC); /* 9. Connect PLL0 with one feed sequence. */
BSP_PLL_FEED_SEQ(0u);
/* ------------------ PLL1 CONFIGURATION -------------- */
reg_val = (((4u - 1u) << 0u) & BSP_MSK_PLLCFG1_MSEL) /* PLL1 values M = 4; P = 2 coded as '01' (see note #6) */
| (((0x01u ) << 5u) & BSP_MSK_PLLCFG1_NSEL);
DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC); /* 1. Disconnect PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE); /* 2. Disable PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
BSP_REG_PLLCFG(1u) = reg_val; /* 3. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(1u); /* ... one one feed sequence */
DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE); /* 4. Enable PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
reg_to = BSP_VAL_MAX_TO; /* 5. Wait for PLL1 to achieve lock by monitoring ... */
/* ... the PLOCK1 bit in the PLL1STAT */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(1u), BSP_BIT_PLLSTAT_PLOCK1) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) {
return (DEF_FAIL);
}
DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC); /* 6. Connect PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_5 /* Set 5 cycles to access the Flash memory. */
| BSP_BIT_FLASHCFG_FETCHCFG_ALL
| BSP_BIT_FLASHCFG_DATACFG_ALL
| BSP_BIT_FLASHCFG_ACCEL_EN
| BSP_BIT_FLASHCFG_PREFETCH_ALL;
return (DEF_OK);
}
void BSP_GPIO_Cfg (CPU_INT08U gpio_port,
CPU_INT32U gpio_pins,
CPU_INT16U gpio_opt)
{
BSP_GPIO_FAST_REG *p_gpio_fast_reg;
CPU_REG32 *p_gpio_pinsel;
CPU_REG32 *p_gpio_pinmode;
CPU_REG32 *p_gpio_pinmode_od;
CPU_INT32U pinsel_opt;
CPU_INT32U pinmode_opt;
CPU_INT32U pin_nbr;
switch (gpio_port) {
case BSP_GPIO_PORT0_FAST:
p_gpio_fast_reg = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT0_FAST_BASE_ADDR);
p_gpio_pinsel = (CPU_REG32 *)(BSP_GPIO_REG_PINSEL_BASE_ADDR + 0x00);
p_gpio_pinmode = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x00);
p_gpio_pinmode_od = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_OD0_BASE_ADDR);
break;
case BSP_GPIO_PORT1_FAST:
p_gpio_fast_reg = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT1_FAST_BASE_ADDR);
p_gpio_pinsel = (CPU_REG32 *)(BSP_GPIO_REG_PINSEL_BASE_ADDR + 0x08);
p_gpio_pinmode = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x08);
p_gpio_pinmode_od = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_OD1_BASE_ADDR);
break;
case BSP_GPIO_PORT2_FAST:
p_gpio_fast_reg = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT2_FAST_BASE_ADDR);
p_gpio_pinsel = (CPU_REG32 *)(BSP_GPIO_REG_PINSEL_BASE_ADDR + 0x10);
p_gpio_pinmode = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x10);
p_gpio_pinmode_od = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_OD2_BASE_ADDR);
break;
case BSP_GPIO_PORT3_FAST:
p_gpio_fast_reg = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT3_FAST_BASE_ADDR);
p_gpio_pinsel = (CPU_REG32 *)(BSP_GPIO_REG_PINSEL_BASE_ADDR + 0x18);
p_gpio_pinmode = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x18);
p_gpio_pinmode_od = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_OD3_BASE_ADDR);
break;
case BSP_GPIO_PORT4_FAST:
p_gpio_fast_reg = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT4_FAST_BASE_ADDR);
p_gpio_pinsel = (CPU_REG32 *)(BSP_GPIO_REG_PINSEL_BASE_ADDR + 0x20);
p_gpio_pinmode = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x20);
p_gpio_pinmode_od = (CPU_REG32 *)(BSP_GPIO_REG_PINMODE_OD4_BASE_ADDR);
break;
case BSP_GPIO_PORT0:
case BSP_GPIO_PORT1:
default:
return;
}
/* ------------ I/O DIRECTION CONFIGURATION ----------- */
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_OUT_EN)) {
DEF_BIT_SET(p_gpio_fast_reg->FIODIR, gpio_pins);
}
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_IN_EN)) {
DEF_BIT_CLR(p_gpio_fast_reg->FIODIR, gpio_pins);
}
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_RD_WR_EN)) {
DEF_BIT_CLR(p_gpio_fast_reg->FIOMASK, gpio_pins);
}
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_RD_WR_DIS)) {
DEF_BIT_SET(p_gpio_fast_reg->FIOMASK, gpio_pins);
}
/* ---- I/O MODE/PERIPHERAL FUNCTION CONFIGURATION ---- */
pinsel_opt = BSP_GPIO_OPT_FNCT_INVALID;
pinmode_opt = BSP_GPIO_OPT_MODE_INVALID;
/* Set PINSELxx based on BSP_GPIO_OPT_FNCT_xxx */
if (DEF_BIT_IS_SET_ANY(gpio_opt, BSP_GPIO_OPT_FNCT_ANY)) {
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_1)) {
pinsel_opt = 0x00;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_2)) {
pinsel_opt = 0x01;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_3)) {
pinsel_opt = 0x02;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_4)) {
pinsel_opt = 0x03;
} else {
return;
}
}
/* Set PMODExx based on BSP_GPIO_OPT_MDOE_xxx */
if (DEF_BIT_IS_SET_ANY(gpio_opt, BSP_GPIO_OPT_MODE_ANY)) {
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_PULLUP)) {
pinmode_opt = 0x00;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_REPEATER)) {
pinmode_opt = 0x01;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_NONE)) {
pinmode_opt = 0x02;
} else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_PULLDOWN)) {
pinmode_opt = 0x03;
}
}
if ((pinsel_opt != BSP_GPIO_OPT_FNCT_INVALID) ||
(pinmode_opt != BSP_GPIO_OPT_MODE_INVALID)) {
for (pin_nbr = 0; pin_nbr < 32; pin_nbr++) {
if (DEF_BIT_IS_SET(gpio_pins, DEF_BIT(pin_nbr))) {
if (pinsel_opt != BSP_GPIO_OPT_FNCT_INVALID) {
if (pin_nbr < 16) {
DEF_BIT_CLR(*p_gpio_pinsel, DEF_BIT_FIELD(2, pin_nbr * 2));
DEF_BIT_SET(*p_gpio_pinsel, DEF_BIT_MASK(pinsel_opt, pin_nbr * 2));
} else {
DEF_BIT_CLR(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinsel + 0x04)), DEF_BIT_FIELD(2, (pin_nbr - 16) * 2));
DEF_BIT_SET(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinsel + 0x04)), DEF_BIT_MASK(pinsel_opt, (pin_nbr - 16) * 2));
}
}
if (DEF_BIT_IS_SET(gpio_pins, DEF_BIT(pin_nbr))) {
if (pinmode_opt != BSP_GPIO_OPT_MODE_INVALID) {
if (pin_nbr < 16) {
DEF_BIT_CLR(*p_gpio_pinmode, DEF_BIT_FIELD(2, pin_nbr * 2));
DEF_BIT_SET(*p_gpio_pinmode, DEF_BIT_MASK(pinmode_opt, pin_nbr * 2));
} else {
DEF_BIT_CLR(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinmode + 0x04)), DEF_BIT_FIELD(2, (pin_nbr - 16) * 2));
DEF_BIT_SET(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinmode + 0x04)), DEF_BIT_MASK(pinmode_opt, (pin_nbr - 16) * 2));
}
}
}
}
}
}
if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_OPEN_DRAIN)) {
*p_gpio_pinmode_od = gpio_pins;
}
}
void OSMonOp (OS_MON *p_mon,
OS_TICK timeout,
void *p_arg,
OS_MON_ON_ENTER_PTR p_on_enter,
OS_MON_ON_EVAL_PTR p_on_eval,
OS_OPT opt,
OS_ERR *p_err)
{
CPU_INT32U op_res;
CPU_INT32U mon_res;
OS_PEND_LIST *p_pend_list;
OS_TCB *p_tcb;
OS_TCB *p_tcb_next;
void *p_eval_data;
CPU_BOOLEAN sched;
CPU_SR_ALLOC();
#ifdef OS_SAFETY_CRITICAL
if (p_err == DEF_NULL) {
OS_SAFETY_CRITICAL_EXCEPTION();
return;
}
#endif
#if (OS_CFG_INVALID_OS_CALLS_CHK_EN == DEF_ENABLED) /* Is the kernel running? */
if (OSRunning != OS_STATE_OS_RUNNING) {
*p_err = OS_ERR_OS_NOT_RUNNING;
return;
}
#endif
#if (OS_CFG_ARG_CHK_EN == DEF_ENABLED)
if (p_mon == DEF_NULL) { /* Validate 'p_mon' */
*p_err = OS_ERR_OBJ_PTR_NULL;
return;
}
#endif
sched = DEF_NO;
CPU_CRITICAL_ENTER();
if (p_on_enter != DEF_NULL) {
op_res = (*p_on_enter)(p_mon, p_arg);
} else {
op_res = OS_MON_RES_BLOCK | OS_MON_RES_STOP_EVAL;
}
if (DEF_BIT_IS_SET(op_res, OS_MON_RES_BLOCK) == DEF_YES) {
OS_Pend((OS_PEND_OBJ *)(p_mon), /* Block task pending on Condition Variable */
OS_TASK_PEND_ON_COND_VAR,
timeout);
sched = DEF_YES;
}
OSTCBCurPtr->MonData.p_eval_data = p_arg;
OSTCBCurPtr->MonData.p_on_eval = p_on_eval;
if (DEF_BIT_IS_CLR(op_res, OS_MON_RES_STOP_EVAL) == DEF_YES) {
p_pend_list = &p_mon->PendList;
if (p_pend_list->HeadPtr != DEF_NULL) {
p_tcb = p_pend_list->HeadPtr;
while (p_tcb != DEF_NULL) {
p_tcb_next = p_tcb->PendNextPtr;
p_on_eval = p_tcb->MonData.p_on_eval;
p_eval_data = p_tcb->MonData.p_eval_data;
if (p_on_eval != DEF_NULL) {
mon_res = (*p_on_eval)(p_mon, p_eval_data, p_arg);
} else {
mon_res = OS_MON_RES_STOP_EVAL;
}
if (DEF_BIT_IS_CLR(mon_res, OS_MON_RES_BLOCK) == DEF_YES) {
OS_Post((OS_PEND_OBJ *)(p_mon), p_tcb, DEF_NULL, 0u, 0u);
if (DEF_BIT_IS_CLR(opt, OS_OPT_POST_NO_SCHED) == DEF_YES) {
sched = DEF_YES;
}
}
if (DEF_BIT_IS_SET(mon_res, OS_MON_RES_STOP_EVAL) == DEF_YES) {
break;
}
p_tcb = p_tcb_next;
}
}
}
CPU_CRITICAL_EXIT();
if (sched == DEF_YES) {
OSSched(); /* Find the next highest priority task ready to run */
}
if (DEF_BIT_IS_SET(op_res, OS_MON_RES_BLOCK) == DEF_YES) {
CPU_CRITICAL_ENTER();
switch (OSTCBCurPtr->PendStatus) {
case OS_STATUS_PEND_OK: /* We got the monitor */
*p_err = OS_ERR_NONE;
break;
case OS_STATUS_PEND_ABORT: /* Indicate that we aborted */
*p_err = OS_ERR_PEND_ABORT;
break;
case OS_STATUS_PEND_TIMEOUT: /* Indicate that we didn't get monitor within timeout */
*p_err = OS_ERR_TIMEOUT;
break;
case OS_STATUS_PEND_DEL: /* Indicate that object pended on has been deleted */
*p_err = OS_ERR_OBJ_DEL;
break;
default:
*p_err = OS_ERR_STATUS_INVALID;
}
CPU_CRITICAL_EXIT();
} else {
*p_err = OS_ERR_NONE;
}
}
