void disp_onConfig_bls(DISP_AAL_PARAM *param)
{
unsigned long prevSetting = DISP_REG_GET(DISP_REG_BLS_BLS_SETTING);
unsigned long regVal = 0;
DISP_DBG("disp_onConfig_bls!\n");
DISP_DBG("pwm duty = %lu\n", param->pwmDuty);
if (param->pwmDuty == 0)
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, 0);
else if (param->pwmDuty > gMaxLevel)
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, gMaxLevel);
else
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, param->pwmDuty);
DISP_DBG("bls setting = %lu\n", param->setting);
#if defined(DDP_GAMMA_SUPPORT)
if (param->setting & ENUM_FUNC_GAMMA)
regVal |= 0x7;
else
#endif
regVal &= ~0x7;
if (param->setting & ENUM_FUNC_BLS)
regVal |= 0x10100;
else
regVal &= ~0x10100;
DISP_REG_SET(DISP_REG_BLS_BLS_SETTING, regVal | 0x100000);
if (param->setting & ENUM_FUNC_BLS)
{
DISP_DBG("distion threshold = %lu\n", param->maxClrDistThd);
DISP_DBG("predistion threshold = %lu\n", param->preDistThd);
// TODO: BLS porting
}
if (prevSetting & 0x10100)
{
// TODO: BLS porting
}
else if (param->setting & ENUM_FUNC_BLS)
{
disp_set_aal_alarm(1);
}
if (aal_debug_flag == 0)
{
DISP_REG_SET(DISP_REG_BLS_EN, 0x00010001);
}
else
{
DISP_REG_SET(DISP_REG_BLS_EN, 0x00010000);
}
}
void ovl_get_info(int idx, void *data)
{
int i = 0;
OVL_BASIC_STRUCT *pdata = (OVL_BASIC_STRUCT *)data;
unsigned int idx_offset = 0;
unsigned int layer_off = 0;
unsigned int src_on = DISP_REG_GET(DISP_REG_OVL_SRC_CON + idx_offset);
OVL_BASIC_STRUCT *p = NULL;
memset(pdata, 0, sizeof(OVL_BASIC_STRUCT)*OVL_LAYER_NUM);
idx_offset = 0;
src_on = DISP_REG_GET(DISP_REG_OVL_SRC_CON + idx_offset);
for (i = 0; i < OVL_LAYER_NUM_PER_OVL; i++) {
layer_off = (i%4)*OVL_LAYER_OFFSET + idx_offset;
p = &pdata[i];
p->layer = i;
p->layer_en = src_on & (0x1<<i);
if (p->layer_en) {
p->fmt = (DISP_REG_GET(layer_off+DISP_REG_OVL_L0_CON)>>12)&0xf;
p->addr = DISP_REG_GET(layer_off+DISP_REG_OVL_L0_ADDR);
p->src_w = DISP_REG_GET(layer_off+DISP_REG_OVL_L0_SRC_SIZE)&0xfff;
p->src_h = (DISP_REG_GET(layer_off+DISP_REG_OVL_L0_SRC_SIZE)>>16)&0xfff;
p->src_pitch = DISP_REG_GET(layer_off+DISP_REG_OVL_L0_PITCH)&0xffff;
p->bpp = ddp_get_bpp(DISP_MODULE_OVL, (DISP_REG_GET(layer_off+DISP_REG_OVL_L0_CON)>>12)&0xf);
}
DISP_DBG("ovl_get_info:layer%d,en %d,w %d,h %d, bpp %d,addr %lx\n",
i, p->layer_en, p->src_w, p->src_h, p->bpp, p->addr);
}
void disp_bls_update_gamma_lut(void)
{
int index, i;
unsigned long regValue;
unsigned long CurVal, Count;
#ifndef NEW_GAMMA_ARRAY_ARRANGEMENT
// make it build fail for EPC rule after MP
DISP_MSG("disp_bls_update_gamma_lut!\n");
#endif
DISP_MSG("disp_bls_update_gamma_lut!\n");
// init gamma table
for(index = 0; index < 3; index++)
{
for(Count = 0; Count < 257 ; Count++)
{
g_gamma_lut.entry[index][Count] = g_gamma_index.entry[index][Count];
}
}
// disable BLS_EN first
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000003);
regValue = DISP_REG_GET(DISP_REG_BLS_EN);
DISP_REG_SET(DISP_REG_BLS_EN, regValue & 0x00010000);
DISP_MSG("ready to modify gamma lut, set BLS_EN=%x\n", DISP_REG_GET(DISP_REG_BLS_EN));
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000000);
DISP_REG_SET(DISP_REG_BLS_LUT_UPDATE, 0x1);
for (i = 0; i < 256 ; i++)
{
CurVal = (((g_gamma_lut.entry[0][i]&0x3FF)<<20) | ((g_gamma_lut.entry[1][i]&0x3FF)<<10) | (g_gamma_lut.entry[2][i]&0x3FF));
DISP_REG_SET(DISP_REG_BLS_GAMMA_LUT(i), CurVal);
DISP_DBG("[%d] GAMMA LUT = 0x%x, (%lu, %lu, %lu)\n", i, DISP_REG_GET(DISP_REG_BLS_GAMMA_LUT(i)),
g_gamma_lut.entry[0][i], g_gamma_lut.entry[1][i], g_gamma_lut.entry[2][i]);
}
/* Set Gamma Last point*/
DISP_REG_SET(DISP_REG_BLS_GAMMA_SETTING, 0x00000001);
// set gamma last index
CurVal = (((g_gamma_lut.entry[0][256]&0x3FF)<<20) | ((g_gamma_lut.entry[1][256]&0x3FF)<<10) | (g_gamma_lut.entry[2][256]&0x3FF));
DISP_REG_SET(DISP_REG_BLS_GAMMA_BOUNDARY, CurVal);
DISP_REG_SET(DISP_REG_BLS_LUT_UPDATE, 0);
//DISP_REG_SET(DISP_REG_BLS_EN, regValue);
//set BLS_EN to oringinal value
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000003);
DISP_REG_SET(DISP_REG_BLS_EN, regValue);
DISP_MSG("end modifying gamma lut, set BLS_EN=%x\n", DISP_REG_GET(DISP_REG_BLS_EN));
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x00000000);
}
void disp_bls_init(unsigned int srcWidth, unsigned int srcHeight)
{
DDP_DRV_DBG("disp_bls_init : srcWidth = %d, srcHeight = %d\n", srcWidth, srcHeight);
struct cust_mt65xx_led *cust_led_list = get_cust_led_list();
struct cust_mt65xx_led *cust = NULL;
struct PWM_config *config_data = NULL;
if(cust_led_list)
{
cust = &cust_led_list[MT65XX_LED_TYPE_LCD];
if((strcmp(cust->name,"lcd-backlight") == 0) && (cust->mode == MT65XX_LED_MODE_CUST_BLS_PWM))
{
config_data = &cust->config_data;
if (config_data->clock_source >= 0 && config_data->clock_source <= 1)
{
unsigned int regVal = DISP_REG_GET(0xF0000000);
if(config_data->clock_source == 0)
clkmux_sel(MT_CLKMUX_PWM_MM_MUX_SEL, MT_CG_SYS_26M, "DISP_PWM");
else
clkmux_sel(MT_CLKMUX_PWM_MM_MUX_SEL, MT_CG_UPLL_D12, "DISP_PWM");
DISP_DBG("disp_bls_init : 0xF0000000: 0x%x => 0x%x\n", regVal, DISP_REG_GET(0xF0000000));
}
}
}
// TODO: fix register setting
DISP_REG_SET(DISP_REG_BLS_SRC_SIZE, (srcHeight << 16) | srcWidth);
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, DISP_REG_GET(DISP_REG_BLS_PWM_DUTY));
DISP_REG_SET(DISP_REG_BLS_PWM_CON, 0x0);
DISP_REG_SET(DISP_REG_BLS_INTEN, 0xF);
disp_bls_update_gamma_lut();
//disp_bls_update_pwm_lut(); // not used in 6572
#if 0 // TODO: fix Dither setting
// Dithering
DISP_REG_SET(DISP_REG_BLS_DITHER(0), 0x00000001);
DISP_REG_SET(DISP_REG_BLS_DITHER(6), 0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(13), 0x00000222);
DISP_REG_SET(DISP_REG_BLS_DITHER(14), 0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(15), 0x22220001);
DISP_REG_SET(DISP_REG_BLS_DITHER(16), 0x22222222);
DISP_REG_SET(DISP_REG_BLS_DITHER(17), 0x00000000);
#endif
DISP_REG_SET(DISP_REG_BLS_EN, 0x00010001); // enable BLS_EN
disp_bls_config_full(srcWidth, srcHeight);
#if 0
disp_dump_reg(DISP_MODULE_BLS);
#endif
}
static void process_dbg_cmd(char *cmd)
{
char *tok;
DISP_DBG("cmd: %s\n", cmd);
memset(dbg_buf, 0, sizeof(dbg_buf));
while ((tok = strsep(&cmd, " ")) != NULL)
{
process_dbg_opt(tok);
}
}
void rdma_get_info(int idx, RDMA_BASIC_STRUCT * info)
{
RDMA_BASIC_STRUCT *p = info;
p->addr = DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR);
p->src_w = DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0)&0xfff;
p->src_h = DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1)&0xfffff,
p->bpp = ddp_get_bpp(DISP_MODULE_RDMA, (DISP_REG_GET(DISP_REG_RDMA_MEM_CON)>>4)&0x3f);
DISP_DBG("rdma_get_info:w %d,h %d, bpp %d,addr %lx\n",
p->src_w, p->src_h, p->bpp, p->addr);
return ;
}
void disp_bls_update_gamma_lut(void)
{
#if defined(DDP_GAMMA_SUPPORT)
int index, i;
unsigned long regValue;
unsigned long CurVal, Count;
DISP_MSG("disp_bls_update_gamma_lut!\n");
if (DISP_REG_GET(DISP_REG_BLS_EN) & 0x1)
{
DISP_ERR("try to update gamma lut while BLS is active\n");
return;
}
// init gamma table
for(index = 0; index < 3; index++)
{
for(Count = 0; Count < 257 ; Count++)
{
g_gamma_lut.entry[index][Count] = g_gamma_index.entry[index][Count];
}
}
DISP_REG_SET(DISP_REG_BLS_LUT_UPDATE, 0x1);
for (i = 0; i < 256 ; i++)
{
CurVal = (((g_gamma_lut.entry[0][i]&0x3FF)<<20) | ((g_gamma_lut.entry[1][i]&0x3FF)<<10) | (g_gamma_lut.entry[2][i]&0x3FF));
DISP_REG_SET(DISP_REG_BLS_GAMMA_LUT(i), CurVal);
DISP_DBG("[%d] GAMMA LUT = 0x%x, (%lu, %lu, %lu)\n", i, DISP_REG_GET(DISP_REG_BLS_GAMMA_LUT(i)),
g_gamma_lut.entry[0][i], g_gamma_lut.entry[1][i], g_gamma_lut.entry[2][i]);
}
/* Set Gamma Last point*/
DISP_REG_SET(DISP_REG_BLS_GAMMA_SETTING, 0x00000001);
// set gamma last index
CurVal = (((g_gamma_lut.entry[0][256]&0x3FF)<<20) | ((g_gamma_lut.entry[1][256]&0x3FF)<<10) | (g_gamma_lut.entry[2][256]&0x3FF));
DISP_REG_SET(DISP_REG_BLS_GAMMA_BOUNDARY, CurVal);
DISP_REG_SET(DISP_REG_BLS_LUT_UPDATE, 0);
#endif
}
void disp_bls_update_pwm_lut(void)
{
int i;
unsigned int regValue;
DISP_MSG("disp_bls_update_pwm_lut!\n");
regValue = DISP_REG_GET(DISP_REG_BLS_EN);
if (regValue & 0x1) {
DISP_ERR("update PWM LUT while BLS func enabled!\n");
disp_dump_reg(DISP_MODULE_BLS);
}
//DISP_REG_SET(DISP_REG_BLS_EN, (regValue & 0x00010000));
for (i = 0; i < PWM_LUT_ENTRY; i++)
{
DISP_REG_SET(DISP_REG_BLS_LUMINANCE(i), g_pwm_lut.entry[i]);
DISP_DBG("[%d] PWM LUT = 0x%x (%lu)\n", i, DISP_REG_GET(DISP_REG_BLS_LUMINANCE(i)), g_pwm_lut.entry[i]);
}
DISP_REG_SET(DISP_REG_BLS_LUMINANCE_255, g_pwm_lut.entry[PWM_LUT_ENTRY-1]);
//DISP_REG_SET(DISP_REG_BLS_EN, regValue);
}
int OVLLayerConfig(unsigned int layer,
unsigned int source,
DpColorFormat format,
unsigned int addr,
unsigned int src_x, // ROI x offset
unsigned int src_y, // ROI y offset
unsigned int src_pitch,
unsigned int dst_x, // ROI x offset
unsigned int dst_y, // ROI y offset
unsigned int dst_w, // ROT width
unsigned int dst_h, // ROI height
bool keyEn,
unsigned int key, // color key
bool aen, // alpha enable
unsigned char alpha) {
unsigned bpp;
unsigned input_color_space;
unsigned matrix_transform;
unsigned mode = (TABLE_NO + 1);//0xdeaddead; // yuv to rgb conversion required
unsigned int rgb_swap = 0;
unsigned int address, start, end;
int width;
enum OVL_INPUT_FORMAT fmt;
ASSERT((dst_w <= OVL_MAX_WIDTH) && (dst_h <= OVL_MAX_HEIGHT));
fmt = ovl_fmt_convert(format);
if((layer==3) && (isAEEEnabled==1) && (addr!=dal_fb_pa))
{
printk("[DDP], config AEE layer! addr=0x%x \n", addr);
}
if(fmt==OVL_INPUT_FORMAT_ABGR8888 ||
fmt==OVL_INPUT_FORMAT_PABGR8888 ||
fmt==OVL_INPUT_FORMAT_xBGR8888 ||
fmt==OVL_INPUT_FORMAT_BGR888 ||
fmt==OVL_INPUT_FORMAT_BGR565 )
{
rgb_swap = 1;
fmt -= OVL_COLOR_BASE;
}
else
{
rgb_swap = 0;
}
switch (fmt) {
case OVL_INPUT_FORMAT_ARGB8888:
case OVL_INPUT_FORMAT_PARGB8888:
case OVL_INPUT_FORMAT_xRGB8888:
bpp = 4;
break;
case OVL_INPUT_FORMAT_RGB888:
case OVL_INPUT_FORMAT_YUV444:
bpp = 3;
break;
case OVL_INPUT_FORMAT_RGB565:
case OVL_INPUT_FORMAT_YUYV:
case OVL_INPUT_FORMAT_UYVY:
case OVL_INPUT_FORMAT_YVYU:
case OVL_INPUT_FORMAT_VYUY:
bpp = 2;
break;
default:
printk("DDP error, OVLLayerConfig unknown fmt , fmt=%d\n", fmt);
ASSERT(0); // invalid input format
}
if((source == OVL_LAYER_SOURCE_SCL || source == OVL_LAYER_SOURCE_PQ) &&
(fmt != OVL_INPUT_FORMAT_YUV444)) {
printk("error: direct link to OVL only support YUV444! \n" );
ASSERT(0); // direct link support YUV444 only
}
if((source == OVL_LAYER_SOURCE_MEM && addr == 0))
{
printk("error: source from memory, but addr is 0! \n");
ASSERT(0); // direct link support YUV444 only
}
switch (fmt) {
case OVL_INPUT_FORMAT_ARGB8888:
case OVL_INPUT_FORMAT_PARGB8888:
case OVL_INPUT_FORMAT_xRGB8888:
case OVL_INPUT_FORMAT_RGB888:
case OVL_INPUT_FORMAT_RGB565:
input_color_space = OVL_COLOR_SPACE_RGB;
break;
case OVL_INPUT_FORMAT_YUV444:
case OVL_INPUT_FORMAT_YUYV:
case OVL_INPUT_FORMAT_UYVY:
case OVL_INPUT_FORMAT_YVYU:
case OVL_INPUT_FORMAT_VYUY:
input_color_space = OVL_COLOR_SPACE_YUV;
break;
default:
printk("DDP error, OVLLayerConfig unknown fmt , fmt=%d\n", fmt);
ASSERT(0); // invalid input format
}
switch (fmt) {
case OVL_INPUT_FORMAT_ARGB8888:
case OVL_INPUT_FORMAT_PARGB8888:
case OVL_INPUT_FORMAT_xRGB8888:
case OVL_INPUT_FORMAT_RGB888:
case OVL_INPUT_FORMAT_RGB565:
matrix_transform = 0;
break;
case OVL_INPUT_FORMAT_YUV444:
case OVL_INPUT_FORMAT_YUYV:
case OVL_INPUT_FORMAT_UYVY:
case OVL_INPUT_FORMAT_YVYU:
case OVL_INPUT_FORMAT_VYUY:
matrix_transform = 0x6;
break;
default:
ASSERT(0); // invalid input format
}
/*
if (OVL_COLOR_SPACE_YUV == input_color_space) {
mode = YUV2RGB_601_0_0;
}
*/
//--------------------------------------------------------
// calculate OVL address alignment for width boundary burst
// 64 byte align:
// start address(first byte)[6:4] <= 3'd4
// end address(last byte)[6:4] >= 0x3'd4
// 128 byte align:
// start address(first byte)[6:4] = 3'b0
// end address(last byte)[6:4] = 3'd7
//--------------------------------------------------------
address = addr+src_x*bpp+src_y*src_pitch; // First byte of first pixel
width = dst_w;
start = address;
end = start + bpp * width - 1; // Last byte of last pixel of first lline
#if 0
if ((width != 0) && (((start&0x70) > 0x40) || ((end&0x70) < 0x40))) {
for (i = 0; start < end;) {
i += bpp;
start += bpp;
if ((start&0x70) <= 0x40) {
break;
}
}
width -= i/bpp;
end = start + width * bpp - 1; // Last byte of last pixel
for (i = 0; end > start;) {
i += bpp;
end -= bpp;
if ((end&0x70) >= 0x40) {
break;
}
}
width -= i/bpp;
// Reset hw start address and layer ROI width
address = start;
if (width <= 0) {
width = dst_w;
}
printk("OVL align 64byte:ROI(%d,%d %d,%d), (%d,%d), 0x%08x-->0x%08x, %d-->%d\n", src_x, src_y, dst_w, dst_h, dst_x, dst_w, addr, address, dst_w, width);
}
#else
if (src_pitch && ( (src_pitch&0x7f) != 0 || (start&0x70) >= 0x50 || (end&0x70) < 0x30 )) {
DISP_DBG("[DDP] warning: hw request(pitch:0x%x,star:0x%x,end:0x%x),fmt=%d\n", src_pitch, start, end, DP_COLOR_GET_UNIQUE_ID(format));
}
#endif
switch(layer) {
case 0:
if((source==OVL_LAYER_SOURCE_MEM) && (addr!=1))
{
DISP_REG_SET(DISP_REG_OVL_RDMA0_CTRL, 0x1);
}
else
{
DISP_REG_SET(DISP_REG_OVL_RDMA0_CTRL, 0);
}
DISP_REG_SET_FIELD(L0_CON_FLD_LAYER_SRC, DISP_REG_OVL_L0_CON, source);
DISP_REG_SET_FIELD(L0_CON_FLD_CLRFMT, DISP_REG_OVL_L0_CON, fmt);
DISP_REG_SET_FIELD(L0_CON_FLD_C_CF_SEL, DISP_REG_OVL_L0_CON, matrix_transform);
DISP_REG_SET_FIELD(L0_CON_FLD_ALPHA_EN, DISP_REG_OVL_L0_CON, aen);
DISP_REG_SET_FIELD(L0_CON_FLD_ALPHA, DISP_REG_OVL_L0_CON, alpha);
DISP_REG_SET_FIELD(L0_CON_FLD_SRCKEY_EN, DISP_REG_OVL_L0_CON, keyEn);
DISP_REG_SET_FIELD(L0_CON_FLD_RGB_SWAP, DISP_REG_OVL_L0_CON, rgb_swap);
DISP_REG_SET(DISP_REG_OVL_L0_SRC_SIZE, dst_h<<16 | width);
DISP_REG_SET(DISP_REG_OVL_L0_OFFSET, dst_y<<16 | dst_x);
DISP_REG_SET(DISP_REG_OVL_L0_ADDR, address);
DISP_REG_SET_FIELD(L0_PITCH_FLD_L0_SRC_PITCH, DISP_REG_OVL_L0_PITCH, src_pitch);
DISP_REG_SET(DISP_REG_OVL_L0_SRCKEY, key);
if (TABLE_NO > mode) { // set up L0 YUV to RGB conversion matrix registers
DISP_REG_SET_FIELD(L0_Y2R_PARA_R0_FLD_C_CF_RMY, DISP_REG_OVL_L0_Y2R_PARA_R0, coef[mode][0][0]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_R0_FLD_C_CF_RMU, DISP_REG_OVL_L0_Y2R_PARA_R0, coef[mode][0][1]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_R1_FLD_C_CF_RMV, DISP_REG_OVL_L0_Y2R_PARA_R1, coef[mode][0][2]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_G0_FLD_C_CF_GMY, DISP_REG_OVL_L0_Y2R_PARA_G0, coef[mode][1][0]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_G0_FLD_C_CF_GMU, DISP_REG_OVL_L0_Y2R_PARA_G0, coef[mode][1][1]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_G1_FLD_C_CF_GMV, DISP_REG_OVL_L0_Y2R_PARA_G1, coef[mode][1][2]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_B0_FLD_C_CF_BMY, DISP_REG_OVL_L0_Y2R_PARA_B0, coef[mode][2][0]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_B0_FLD_C_CF_BMU, DISP_REG_OVL_L0_Y2R_PARA_B0, coef[mode][2][1]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_B1_FLD_C_CF_BMV, DISP_REG_OVL_L0_Y2R_PARA_B1, coef[mode][2][2]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_YUV_A_0_FLD_C_CF_YA, DISP_REG_OVL_L0_Y2R_PARA_YUV_A_0, coef[mode][3][0]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_YUV_A_0_FLD_C_CF_UA, DISP_REG_OVL_L0_Y2R_PARA_YUV_A_0, coef[mode][3][1]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_YUV_A_1_FLD_C_CF_VA, DISP_REG_OVL_L0_Y2R_PARA_YUV_A_1, coef[mode][3][2]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_RGB_A_0_FLD_C_CF_RA, DISP_REG_OVL_L0_Y2R_PARA_RGB_A_0, coef[mode][4][0]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_RGB_A_0_FLD_C_CF_GA, DISP_REG_OVL_L0_Y2R_PARA_RGB_A_0, coef[mode][4][1]);
DISP_REG_SET_FIELD(L0_Y2R_PARA_RGB_A_1_FLD_C_CF_BA, DISP_REG_OVL_L0_Y2R_PARA_RGB_A_1, coef[mode][4][2]);
DISP_REG_SET_FIELD(L0_CON_FLD_EXT_MTX_EN, DISP_REG_OVL_L0_CON, 1);
}
else
{
DISP_REG_SET_FIELD(L0_CON_FLD_EXT_MTX_EN, DISP_REG_OVL_L0_CON, 0);
}
break;
case 1:
if((source==OVL_LAYER_SOURCE_MEM) && (addr!=1))
{
DISP_REG_SET(DISP_REG_OVL_RDMA1_CTRL, 0x1);
}
else
{
DISP_REG_SET(DISP_REG_OVL_RDMA1_CTRL, 0);
}
DISP_REG_SET_FIELD(L1_CON_FLD_LAYER_SRC, DISP_REG_OVL_L1_CON, source);
DISP_REG_SET_FIELD(L1_CON_FLD_CLRFMT, DISP_REG_OVL_L1_CON, fmt);
DISP_REG_SET_FIELD(L1_CON_FLD_C_CF_SEL, DISP_REG_OVL_L1_CON, matrix_transform);
DISP_REG_SET_FIELD(L1_CON_FLD_ALPHA_EN, DISP_REG_OVL_L1_CON, aen);
DISP_REG_SET_FIELD(L1_CON_FLD_ALPHA, DISP_REG_OVL_L1_CON, alpha);
DISP_REG_SET_FIELD(L1_CON_FLD_SRCKEY_EN, DISP_REG_OVL_L1_CON, keyEn);
DISP_REG_SET_FIELD(L1_CON_FLD_RGB_SWAP, DISP_REG_OVL_L1_CON, rgb_swap);
DISP_REG_SET(DISP_REG_OVL_L1_SRC_SIZE, dst_h<<16 | width);
DISP_REG_SET(DISP_REG_OVL_L1_OFFSET, dst_y<<16 | dst_x);
DISP_REG_SET(DISP_REG_OVL_L1_ADDR, address);
DISP_REG_SET_FIELD(L1_PITCH_FLD_L1_SRC_PITCH, DISP_REG_OVL_L1_PITCH, src_pitch);
DISP_REG_SET(DISP_REG_OVL_L1_SRCKEY, key);
if (TABLE_NO > mode) { // set up L0 YUV to RGB conversion matrix registers
DISP_REG_SET_FIELD(L1_Y2R_PARA_R0_FLD_C_CF_RMY, DISP_REG_OVL_L1_Y2R_PARA_R0, coef[mode][0][0]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_R0_FLD_C_CF_RMU, DISP_REG_OVL_L1_Y2R_PARA_R0, coef[mode][0][1]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_R1_FLD_C_CF_RMV, DISP_REG_OVL_L1_Y2R_PARA_R1, coef[mode][0][2]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_G0_FLD_C_CF_GMY, DISP_REG_OVL_L1_Y2R_PARA_G0, coef[mode][1][0]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_G0_FLD_C_CF_GMU, DISP_REG_OVL_L1_Y2R_PARA_G0, coef[mode][1][1]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_G1_FLD_C_CF_GMV, DISP_REG_OVL_L1_Y2R_PARA_G1, coef[mode][1][2]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_B0_FLD_C_CF_BMY, DISP_REG_OVL_L1_Y2R_PARA_B0, coef[mode][2][0]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_B0_FLD_C_CF_BMU, DISP_REG_OVL_L1_Y2R_PARA_B0, coef[mode][2][1]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_B1_FLD_C_CF_BMV, DISP_REG_OVL_L1_Y2R_PARA_B1, coef[mode][2][2]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_YUV_A_0_FLD_C_CF_YA, DISP_REG_OVL_L1_Y2R_PARA_YUV_A_0, coef[mode][3][0]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_YUV_A_0_FLD_C_CF_UA, DISP_REG_OVL_L1_Y2R_PARA_YUV_A_0, coef[mode][3][1]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_YUV_A_1_FLD_C_CF_VA, DISP_REG_OVL_L1_Y2R_PARA_YUV_A_1, coef[mode][3][2]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_RGB_A_0_FLD_C_CF_RA, DISP_REG_OVL_L1_Y2R_PARA_RGB_A_0, coef[mode][4][0]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_RGB_A_0_FLD_C_CF_GA, DISP_REG_OVL_L1_Y2R_PARA_RGB_A_0, coef[mode][4][1]);
DISP_REG_SET_FIELD(L1_Y2R_PARA_RGB_A_1_FLD_C_CF_BA, DISP_REG_OVL_L1_Y2R_PARA_RGB_A_1, coef[mode][4][2]);
DISP_REG_SET_FIELD(L1_CON_FLD_EXT_MTX_EN, DISP_REG_OVL_L1_CON, 1);
}
else
{
DISP_REG_SET_FIELD(L1_CON_FLD_EXT_MTX_EN, DISP_REG_OVL_L1_CON, 0);
}
break;
case 2:
if((source==OVL_LAYER_SOURCE_MEM) && (addr!=1))
{
DISP_REG_SET(DISP_REG_OVL_RDMA2_CTRL, 0x1);
}
else
{
DISP_REG_SET(DISP_REG_OVL_RDMA2_CTRL, 0);
}
DISP_REG_SET_FIELD(L2_CON_FLD_LAYER_SRC, DISP_REG_OVL_L2_CON, source);
DISP_REG_SET_FIELD(L2_CON_FLD_CLRFMT, DISP_REG_OVL_L2_CON, fmt);
DISP_REG_SET_FIELD(L2_CON_FLD_C_CF_SEL, DISP_REG_OVL_L2_CON, matrix_transform);
DISP_REG_SET_FIELD(L2_CON_FLD_ALPHA_EN, DISP_REG_OVL_L2_CON, aen);
DISP_REG_SET_FIELD(L2_CON_FLD_ALPHA, DISP_REG_OVL_L2_CON, alpha);
DISP_REG_SET_FIELD(L2_CON_FLD_SRCKEY_EN, DISP_REG_OVL_L2_CON, keyEn);
DISP_REG_SET_FIELD(L2_CON_FLD_RGB_SWAP, DISP_REG_OVL_L2_CON, rgb_swap);
DISP_REG_SET(DISP_REG_OVL_L2_SRC_SIZE, dst_h<<16 | width);
DISP_REG_SET(DISP_REG_OVL_L2_OFFSET, dst_y<<16 | dst_x);
DISP_REG_SET(DISP_REG_OVL_L2_ADDR, address);
DISP_REG_SET_FIELD(L2_PITCH_FLD_L2_SRC_PITCH, DISP_REG_OVL_L2_PITCH, src_pitch);
DISP_REG_SET(DISP_REG_OVL_L2_SRCKEY, key);
if (TABLE_NO > mode) { // set up L0 YUV to RGB conversion matrix registers
DISP_REG_SET_FIELD(L2_Y2R_PARA_R0_FLD_C_CF_RMY, DISP_REG_OVL_L2_Y2R_PARA_R0, coef[mode][0][0]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_R0_FLD_C_CF_RMU, DISP_REG_OVL_L2_Y2R_PARA_R0, coef[mode][0][1]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_R1_FLD_C_CF_RMV, DISP_REG_OVL_L2_Y2R_PARA_R1, coef[mode][0][2]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_G0_FLD_C_CF_GMY, DISP_REG_OVL_L2_Y2R_PARA_G0, coef[mode][1][0]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_G0_FLD_C_CF_GMU, DISP_REG_OVL_L2_Y2R_PARA_G0, coef[mode][1][1]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_G1_FLD_C_CF_GMV, DISP_REG_OVL_L2_Y2R_PARA_G1, coef[mode][1][2]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_B0_FLD_C_CF_BMY, DISP_REG_OVL_L2_Y2R_PARA_B0, coef[mode][2][0]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_B0_FLD_C_CF_BMU, DISP_REG_OVL_L2_Y2R_PARA_B0, coef[mode][2][1]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_B1_FLD_C_CF_BMV, DISP_REG_OVL_L2_Y2R_PARA_B1, coef[mode][2][2]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_YUV_A_0_FLD_C_CF_YA, DISP_REG_OVL_L2_Y2R_PARA_YUV_A_0, coef[mode][3][0]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_YUV_A_0_FLD_C_CF_UA, DISP_REG_OVL_L2_Y2R_PARA_YUV_A_0, coef[mode][3][1]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_YUV_A_1_FLD_C_CF_VA, DISP_REG_OVL_L2_Y2R_PARA_YUV_A_1, coef[mode][3][2]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_RGB_A_0_FLD_C_CF_RA, DISP_REG_OVL_L2_Y2R_PARA_RGB_A_0, coef[mode][4][0]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_RGB_A_0_FLD_C_CF_GA, DISP_REG_OVL_L2_Y2R_PARA_RGB_A_0, coef[mode][4][1]);
DISP_REG_SET_FIELD(L2_Y2R_PARA_RGB_A_1_FLD_C_CF_BA, DISP_REG_OVL_L2_Y2R_PARA_RGB_A_1, coef[mode][4][2]);
DISP_REG_SET_FIELD(L2_CON_FLD_EXT_MTX_EN, DISP_REG_OVL_L2_CON, 1);
}
else
{
DISP_REG_SET_FIELD(L2_CON_FLD_EXT_MTX_EN, DISP_REG_OVL_L2_CON, 0);
}
break;
case 3:
if((source==OVL_LAYER_SOURCE_MEM) && (addr!=1))
{
DISP_REG_SET(DISP_REG_OVL_RDMA3_CTRL, 0x1);
}
else
{
DISP_REG_SET(DISP_REG_OVL_RDMA3_CTRL, 0);
}
DISP_REG_SET_FIELD(L3_CON_FLD_LAYER_SRC, DISP_REG_OVL_L3_CON, source);
DISP_REG_SET_FIELD(L3_CON_FLD_CLRFMT, DISP_REG_OVL_L3_CON, fmt);
DISP_REG_SET_FIELD(L3_CON_FLD_C_CF_SEL, DISP_REG_OVL_L3_CON, matrix_transform);
DISP_REG_SET_FIELD(L3_CON_FLD_ALPHA_EN, DISP_REG_OVL_L3_CON, aen);
DISP_REG_SET_FIELD(L3_CON_FLD_ALPHA, DISP_REG_OVL_L3_CON, alpha);
DISP_REG_SET_FIELD(L3_CON_FLD_SRCKEY_EN, DISP_REG_OVL_L3_CON, keyEn);
DISP_REG_SET_FIELD(L3_CON_FLD_RGB_SWAP, DISP_REG_OVL_L3_CON, rgb_swap);
DISP_REG_SET(DISP_REG_OVL_L3_SRC_SIZE, dst_h<<16 | width);
DISP_REG_SET(DISP_REG_OVL_L3_OFFSET, dst_y<<16 | dst_x);
DISP_REG_SET(DISP_REG_OVL_L3_ADDR, address);
DISP_REG_SET_FIELD(L3_PITCH_FLD_L3_SRC_PITCH, DISP_REG_OVL_L3_PITCH, src_pitch);
DISP_REG_SET(DISP_REG_OVL_L3_SRCKEY, key);
if (TABLE_NO > mode) { // set up L0 YUV to RGB conversion matrix registers
DISP_REG_SET_FIELD(L3_Y2R_PARA_R0_FLD_C_CF_RMY, DISP_REG_OVL_L3_Y2R_PARA_R0, coef[mode][0][0]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_R0_FLD_C_CF_RMU, DISP_REG_OVL_L3_Y2R_PARA_R0, coef[mode][0][1]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_R1_FLD_C_CF_RMV, DISP_REG_OVL_L3_Y2R_PARA_R1, coef[mode][0][2]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_G0_FLD_C_CF_GMY, DISP_REG_OVL_L3_Y2R_PARA_G0, coef[mode][1][0]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_G0_FLD_C_CF_GMU, DISP_REG_OVL_L3_Y2R_PARA_G0, coef[mode][1][1]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_G1_FLD_C_CF_GMV, DISP_REG_OVL_L3_Y2R_PARA_G1, coef[mode][1][2]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_B0_FLD_C_CF_BMY, DISP_REG_OVL_L3_Y2R_PARA_B0, coef[mode][2][0]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_B0_FLD_C_CF_BMU, DISP_REG_OVL_L3_Y2R_PARA_B0, coef[mode][2][1]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_B1_FLD_C_CF_BMV, DISP_REG_OVL_L3_Y2R_PARA_B1, coef[mode][2][2]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_YUV_A_0_FLD_C_CF_YA, DISP_REG_OVL_L3_Y2R_PARA_YUV_A_0, coef[mode][3][0]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_YUV_A_0_FLD_C_CF_UA, DISP_REG_OVL_L3_Y2R_PARA_YUV_A_0, coef[mode][3][1]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_YUV_A_1_FLD_C_CF_VA, DISP_REG_OVL_L3_Y2R_PARA_YUV_A_1, coef[mode][3][2]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_RGB_A_0_FLD_C_CF_RA, DISP_REG_OVL_L3_Y2R_PARA_RGB_A_0, coef[mode][4][0]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_RGB_A_0_FLD_C_CF_GA, DISP_REG_OVL_L3_Y2R_PARA_RGB_A_0, coef[mode][4][1]);
DISP_REG_SET_FIELD(L3_Y2R_PARA_RGB_A_1_FLD_C_CF_BA, DISP_REG_OVL_L3_Y2R_PARA_RGB_A_1, coef[mode][4][2]);
DISP_REG_SET_FIELD(L3_CON_FLD_EXT_MTX_EN, DISP_REG_OVL_L3_CON, 1);
}
else
{
DISP_REG_SET_FIELD(L3_CON_FLD_EXT_MTX_EN, DISP_REG_OVL_L3_CON, 0);
}
break;
default:
printk("DDP error, OVLLayerConfig layer=%d\n", layer);
ASSERT(0); // invalid layer index
}
if(0)//if(w==1080)
{
// printk("[DDP]set 1080p ultra \n");
DISP_REG_SET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING, 0x00f00040);
DISP_REG_SET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING, 0x00f00040);
DISP_REG_SET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING, 0x00f00040);
DISP_REG_SET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING, 0x00f00040);
}
return 0;
}
static void process_dbg_opt(const char *opt)
{
char *buf = dbg_buf + strlen(dbg_buf);
if (0 == strncmp(opt, "regr:", 5))
{
char *p = (char *)opt + 5;
unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
if (addr)
{
unsigned int regVal = DISP_REG_GET(addr);
DISP_MSG("regr: 0x%08X = 0x%08X\n", addr, regVal);
sprintf(buf, "regr: 0x%08X = 0x%08X\n", addr, regVal);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "regw:", 5))
{
char *p = (char *)opt + 5;
unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
unsigned int val = (unsigned int) simple_strtoul(p + 1, &p, 16);
if (addr)
{
unsigned int regVal;
DISP_REG_SET(addr, val);
regVal = DISP_REG_GET(addr);
DISP_DBG("regw: 0x%08X, 0x%08X = 0x%08X\n", addr, val, regVal);
sprintf(buf, "regw: 0x%08X, 0x%08X = 0x%08X\n", addr, val, regVal);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "dbg_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
dbg_log = 1;
else
dbg_log = 0;
sprintf(buf, "dbg_log: %d\n", dbg_log);
}
else if (0 == strncmp(opt, "irq_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
irq_log = 1;
else
irq_log = 0;
sprintf(buf, "irq_log: %d\n", irq_log);
}
else if (0 == strncmp(opt, "backlight:", 10))
{
char *p = (char *)opt + 10;
unsigned int level = (unsigned int) simple_strtoul(p, &p, 10);
if (level)
{
disp_bls_set_backlight(level);
sprintf(buf, "backlight: %d\n", level);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "dump_reg:", 9))
{
char *p = (char *)opt + 9;
unsigned int module = (unsigned int) simple_strtoul(p, &p, 10);
DISP_MSG("process_dbg_opt, module=%d \n", module);
if (module<DISP_MODULE_MAX)
{
disp_dump_reg(module);
sprintf(buf, "dump_reg: %d\n", module);
} else {
DISP_MSG("process_dbg_opt2, module=%d \n", module);
goto Error;
}
}
else if (0 == strncmp(opt, "dump_aal:", 9))
{
char *p = (char *)opt + 9;
unsigned int arg = (unsigned int) simple_strtoul(p, &p, 10);
if (arg == 0)
{
int i;
unsigned int hist[LUMA_HIST_BIN];
disp_get_hist(hist);
for (i = 0; i < LUMA_HIST_BIN; i++)
{
DISP_DBG("LUMA_HIST_%02d: %d\n", i, hist[i]);
sprintf(dbg_buf + strlen(dbg_buf), "LUMA_HIST_%2d: %d\n", i, hist[i]);
}
}
else if (arg == 1)
{
int i;
DISP_AAL_PARAM param;
GetUpdateMutex();
memcpy(¶m, get_aal_config(), sizeof(DISP_AAL_PARAM));
ReleaseUpdateMutex();
DISP_DBG("pwmDuty: %lu\n", param.pwmDuty);
sprintf(dbg_buf + strlen(dbg_buf), "pwmDuty: %lu\n", param.pwmDuty);
for (i = 0; i < LUMA_CURVE_POINT; i++)
{
DISP_DBG("lumaCurve[%02d]: %lu\n", i, param.lumaCurve[i]);
sprintf(dbg_buf + strlen(dbg_buf), "lumaCurve[%02d]: %lu\n", i, param.lumaCurve[i]);
}
}
}
else if (0 == strncmp(opt, "debug:", 6))
{
char *p = (char *)opt + 6;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if(enable==1)
{
printk("[DDP] debug=1, trigger AEE\n");
aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT");
}
else if(enable==2)
{
ddp_mem_test();
}
else if(enable==3)
{
ddp_mem_test2();
}
}
else if (0 == strncmp(opt, "mmp", 3))
{
init_ddp_mmp_events();
}
else if (0 == strncmp(opt, "dpfd_ut1:", 9))
{
char *p = (char *)opt + 9;
unsigned int channel = (unsigned int) simple_strtoul(p, &p, 10);
ddpk_testfunc_1(channel);
}
else if (0 == strncmp(opt, "dpfd_ut2:", 9))
{
char *p = (char *)opt + 9;
unsigned int channel = (unsigned int) simple_strtoul(p, &p, 10);
ddpk_testfunc_2(channel);
}
else if (0 == strncmp(opt, "dpfd:log", 8))
{
}
else if (0 == strncmp(opt, "pqon", 4))
{
pq_debug_flag=0;
sprintf(buf, "Turn on PQ %d\n", pq_debug_flag);
}
else if (0 == strncmp(opt, "pqoff", 5))
{
pq_debug_flag=1;
sprintf(buf, "Turn off PQ %d\n", pq_debug_flag);
}
else if (0 == strncmp(opt, "pqdemo", 6))
{
pq_debug_flag=2;
sprintf(buf, "Turn on PQ (demo) %d\n", pq_debug_flag);
}
else if (0 == strncmp(opt, "pqstop", 6))
{
pq_debug_flag=3;
sprintf(buf, "Stop mutex update %d\n", pq_debug_flag);
}
else if (0 == strncmp(opt, "aalon", 5))
{
aal_debug_flag=0;
sprintf(buf, "resume aal update %d\n", aal_debug_flag);
}
else if (0 == strncmp(opt, "aaloff", 6))
{
aal_debug_flag=1;
sprintf(buf, "suspend aal update %d\n", aal_debug_flag);
}
else if (0 == strncmp(opt, "color_win:", 10))
{
char *p = (char *)opt + 10;
unsigned int sat_upper, sat_lower, hue_upper, hue_lower;
sat_upper = (unsigned int) simple_strtoul(p, &p, 10);
p++;
sat_lower = (unsigned int) simple_strtoul(p, &p, 10);
p++;
hue_upper = (unsigned int) simple_strtoul(p, &p, 10);
p++;
hue_lower = (unsigned int) simple_strtoul(p, &p, 10);
DISP_MSG("Set color_win: %u, %u, %u, %u\n", sat_upper, sat_lower, hue_upper, hue_lower);
disp_color_set_window(sat_upper, sat_lower, hue_upper, hue_lower);
}
else
{
goto Error;
}
return;
Error:
DISP_ERR("parse command error!\n%s\n\n%s", opt, STR_HELP);
}
static void process_dbg_opt(const char *opt)
{
char *buf = dbg_buf + strlen(dbg_buf);
if (0 == strncmp(opt, "regr:", 5))
{
char *p = (char *)opt + 5;
unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
if (addr)
{
unsigned int regVal = DISP_REG_GET(addr);
DISP_MSG("regr: 0x%08X = 0x%08X\n", addr, regVal);
sprintf(buf, "regr: 0x%08X = 0x%08X\n", addr, regVal);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "regw:", 5))
{
char *p = (char *)opt + 5;
unsigned int addr = (unsigned int) simple_strtoul(p, &p, 16);
unsigned int val = (unsigned int) simple_strtoul(p + 1, &p, 16);
if (addr)
{
unsigned int regVal;
DISP_REG_SET(addr, val);
regVal = DISP_REG_GET(addr);
DISP_DBG("regw: 0x%08X, 0x%08X = 0x%08X\n", addr, val, regVal);
sprintf(buf, "regw: 0x%08X, 0x%08X = 0x%08X\n", addr, val, regVal);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "dbg_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
dbg_log = 1;
else
dbg_log = 0;
sprintf(buf, "dbg_log: %d\n", dbg_log);
}
else if (0 == strncmp(opt, "irq_log:", 8))
{
char *p = (char *)opt + 8;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
irq_log = 1;
else
irq_log = 0;
sprintf(buf, "irq_log: %d\n", irq_log);
}
else if (0 == strncmp(opt, "irq_err_log:", 12))
{
char *p = (char *)opt + 12;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if (enable)
irq_err_log = 1;
else
irq_err_log = 0;
sprintf(buf, "irq_err_log: %d\n", irq_err_log);
}
else if (0 == strncmp(opt, "backlight:", 10))
{
char *p = (char *)opt + 10;
unsigned int level = (unsigned int) simple_strtoul(p, &p, 10);
if (level)
{
disp_bls_set_backlight(level);
sprintf(buf, "backlight: %d\n", level);
} else {
goto Error;
}
}
else if (0 == strncmp(opt, "dump_reg:", 9))
{
char *p = (char *)opt + 9;
unsigned int module = (unsigned int) simple_strtoul(p, &p, 10);
DISP_MSG("process_dbg_opt, module=%d \n", module);
if (module<DISP_MODULE_MAX)
{
disp_dump_reg(module);
sprintf(buf, "dump_reg: %d\n", module);
} else {
DISP_MSG("process_dbg_opt2, module=%d \n", module);
goto Error;
}
}
else if (0 == strncmp(opt, "dump_aal:", 9))
{
char *p = (char *)opt + 9;
unsigned int arg = (unsigned int) simple_strtoul(p, &p, 10);
if (arg == 0)
{
int i;
unsigned int hist[LUMA_HIST_BIN];
disp_get_hist(hist);
for (i = 0; i < LUMA_HIST_BIN; i++)
{
DISP_DBG("LUMA_HIST_%02d: %d\n", i, hist[i]);
sprintf(dbg_buf + strlen(dbg_buf), "LUMA_HIST_%2d: %d\n", i, hist[i]);
}
}
else if (arg == 1)
{
int i;
DISP_AAL_PARAM param;
GetUpdateMutex();
memcpy(¶m, get_aal_config(), sizeof(DISP_AAL_PARAM));
ReleaseUpdateMutex();
DISP_DBG("pwmDuty: %lu\n", param.pwmDuty);
sprintf(dbg_buf + strlen(dbg_buf), "pwmDuty: %lu\n", param.pwmDuty);
for (i = 0; i < LUMA_CURVE_POINT; i++)
{
DISP_DBG("lumaCurve[%02d]: %lu\n", i, param.lumaCurve[i]);
sprintf(dbg_buf + strlen(dbg_buf), "lumaCurve[%02d]: %lu\n", i, param.lumaCurve[i]);
}
}
}
else if (0 == strncmp(opt, "debug:", 6))
{
char *p = (char *)opt + 6;
unsigned int enable = (unsigned int) simple_strtoul(p, &p, 10);
if(enable==1)
{
printk("[DDP] debug=1, trigger AEE\n");
aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT");
}
else if(enable==2)
{
ddp_mem_test();
}
else if(enable==3)
{
ddp_mem_test2();
}
else if(enable==4)
{
DDP_IRQ_ERR("test 4");
}
else if(enable==5)
{
DISP_MSG("SMI_LARB_MON_REQ0=0x%x, SMI_LARB_MON_REQ1=0x%x, SMI_0=0x%x, SMI_600=0x%x, SMI_604=0x%x, SMI_610=0x%x, SMI_614=0x%x, \
color_h_cnt=%d, color_line_cnt=%d, ovl_add_con=0x%x, ovl_ctrl_flow=0x%x \n",
*(volatile unsigned int*)0xf4010450,
*(volatile unsigned int*)0xf4010454,
*(volatile unsigned int*)0xf4010000,
*(volatile unsigned int*)0xf4010600,
*(volatile unsigned int*)0xf4010604,
*(volatile unsigned int*)0xf4010610,
*(volatile unsigned int*)0xf4010614,
*(volatile unsigned int*)0xf400b404,
*(volatile unsigned int*)0xf400b408,
DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG),
DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG));
sprintf(dbg_buf + strlen(dbg_buf), "SMI_LARB_MON_REQ0=0x%x, SMI_LARB_MON_REQ1=0x%x, SMI_0=0x%x, SMI_600=0x%x, SMI_604=0x%x, SMI_610=0x%x, SMI_614=0x%x,"
"color_h_cnt=%d, color_line_cnt=%d, ovl_add_con=0x%x, ovl_ctrl_flow=0x%x \n",
*(volatile unsigned int*)0xf4010450,
*(volatile unsigned int*)0xf4010454,
*(volatile unsigned int*)0xf4010000,
*(volatile unsigned int*)0xf4010600,
*(volatile unsigned int*)0xf4010604,
*(volatile unsigned int*)0xf4010610,
*(volatile unsigned int*)0xf4010614,
*(volatile unsigned int*)0xf400b404,
*(volatile unsigned int*)0xf400b408,
DISP_REG_GET(DISP_REG_OVL_ADDCON_DBG),
DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG));
}
