void disp_dither_init(disp_dither_id_t id, int width, int height, unsigned int dither_bpp, void *cmdq) { unsigned long reg_base = DISPSYS_DITHER_BASE; unsigned int enable; DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 5), 0x00000000, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 6), 0x00003004, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 7), 0x00000000, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 8), 0x00000000, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 9), 0x00000000, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 10), 0x00000000, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 11), 0x00000000, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 12), 0x00000011, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 13), 0x00000000, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 14), 0x00000000, ~0); enable = 0x1; if (dither_bpp == 16) { /* 565 */ DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 15), 0x50500001, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 16), 0x50504040, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 0), 0x00000001, ~0); } else if (dither_bpp == 18) { /* 666 */ DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 15), 0x40400001, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 16), 0x40404040, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 0), 0x00000001, ~0); } else if (dither_bpp == 24) { /* 888 */ DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 15), 0x20200001, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 16), 0x20202020, ~0); DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 0), 0x00000001, ~0); } else if (dither_bpp > 24) { DITHER_DBG("High depth LCM (bpp = %d), no dither\n", dither_bpp); enable = 1; } else { DITHER_DBG("invalid dither bpp = %d\n", dither_bpp); /* Bypass dither */ DISP_REG_MASK(cmdq, DITHER_REG(reg_base, 0), 0x00000000, ~0); enable = 0; } DISP_REG_MASK(cmdq, DISP_REG_DITHER_EN, enable, 0x1); DISP_REG_MASK(cmdq, DISP_REG_DITHER_CFG, enable << 1, 1 << 1); DISP_REG_SET(cmdq, DISP_REG_DITHER_SIZE, (width << 16) | height); }
static int disp_ccorr_write_coef_reg(cmdqRecHandle cmdq, disp_ccorr_id_t id, int lock) { unsigned int ccorr_base = 0; int ret = 0; int is_identity = 0; DISP_CCORR_COEF_T *ccorr; if (id >= DISP_CCORR_TOTAL) { printk(KERN_ERR "[GAMMA] disp_gamma_write_lut_reg: invalid ID = %d\n", id); return -EFAULT; } if (lock) spin_lock(&g_gamma_global_lock); ccorr = g_disp_ccorr_coef[id]; if (ccorr == NULL) { printk(KERN_NOTICE "[GAMMA] disp_ccorr_write_coef_reg: [%d] not initialized\n", id); ret = -EFAULT; goto ccorr_write_coef_unlock; } if ((ccorr->coef[0][0] == 1024) && (ccorr->coef[0][1] == 0) && (ccorr->coef[0][2] == 0) && (ccorr->coef[1][0] == 0) && (ccorr->coef[1][1] == 1024) && (ccorr->coef[1][2] == 0) && (ccorr->coef[2][0] == 0) && (ccorr->coef[2][1] == 0) && (ccorr->coef[2][2] == 1024)) { is_identity = 1; } if (id == DISP_CCORR0) { ccorr_base = DISP_AAL_CCORR(0); DISP_REG_MASK(cmdq, DISP_AAL_CFG, (!is_identity) << 4, 0x1 << 4); } else if (id == DISP_CCORR1) { ccorr_base = DISP_GAMMA_CCORR_0; DISP_REG_MASK(cmdq, DISP_REG_GAMMA_CFG, (!is_identity) << 4, 0x1 << 4); } else { printk(KERN_ERR "[GAMMA] disp_gamma_write_ccorr_reg: invalid ID = %d\n", id); ret = -EFAULT; goto ccorr_write_coef_unlock; } pr_debug("CCORR %d %d\n", (int)id, is_identity); pr_debug("CCORR %d %d %d\n", ccorr->coef[0][0], ccorr->coef[0][1], ccorr->coef[0][2]); pr_debug("CCORR %d %d %d\n", ccorr->coef[1][0], ccorr->coef[1][1], ccorr->coef[1][2]); pr_debug("CCORR %d %d %d\n", ccorr->coef[2][0], ccorr->coef[2][1], ccorr->coef[2][2]); DISP_REG_SET(cmdq, CCORR_REG(ccorr_base, 0), ((ccorr->coef[0][0] << 16) | (ccorr->coef[0][1])) ); DISP_REG_SET(cmdq, CCORR_REG(ccorr_base, 1), ((ccorr->coef[0][2] << 16) | (ccorr->coef[1][0])) ); DISP_REG_SET(cmdq, CCORR_REG(ccorr_base, 2), ((ccorr->coef[1][1] << 16) | (ccorr->coef[1][2])) ); DISP_REG_SET(cmdq, CCORR_REG(ccorr_base, 3), ((ccorr->coef[2][0] << 16) | (ccorr->coef[2][1])) ); DISP_REG_SET(cmdq, CCORR_REG(ccorr_base, 4), (ccorr->coef[2][2] << 16) ); ccorr_write_coef_unlock: if (lock) spin_unlock(&g_gamma_global_lock); return ret; }
static int disp_aal_write_param_to_reg(cmdqRecHandle cmdq, const DISP_AAL_PARAM *param) { int i; const int *gain; gain = param->DREGainFltStatus; DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(0), DRE_REG_2(gain[0], 0, gain[1], 12), ~0); DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(1), DRE_REG_2(gain[2], 0, gain[3], 12), ~0); DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(2), DRE_REG_2(gain[4], 0, gain[5], 11), ~0); DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(3), DRE_REG_3(gain[6], 0, gain[7], 11, gain[8], 21), ~0); DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(4), DRE_REG_3(gain[9], 0, gain[10], 10, gain[11], 20), ~0); DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(5), DRE_REG_3(gain[12], 0, gain[13], 10, gain[14], 20), ~0); DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(6), DRE_REG_3(gain[15], 0, gain[16], 10, gain[17], 20), ~0); DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(7), DRE_REG_3(gain[18], 0, gain[19], 9, gain[20], 18), ~0); DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(8), DRE_REG_3(gain[21], 0, gain[22], 9, gain[23], 18), ~0); DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(9), DRE_REG_3(gain[24], 0, gain[25], 9, gain[26], 18), ~0); DISP_REG_MASK(cmdq, DISP_AAL_DRE_FLT_FORCE(10), DRE_REG_2(gain[27], 0, gain[28], 9), ~0); DISP_REG_MASK(cmdq, DISP_AAL_CABC_00, 1 << 31, 1 << 31); DISP_REG_MASK(cmdq, DISP_AAL_CABC_02, ((1 << 26) | param->cabc_fltgain_force), ((1 << 26) | 0x3ff)); gain = param->cabc_gainlmt; for (i = 0; i <= 10; i++) { DISP_REG_MASK(cmdq, DISP_AAL_CABC_GAINLMT_TBL(i), CABC_GAINLMT(gain[0], gain[1], gain[2]), ~0); gain += 3; } return 0; }