Ejemplos de DMA_CFG_CHPRIORITY en C++ (Cpp)

Ejemplo n.º 1

Archivo: dma_uart.c Proyecto: frankzzcn/M2_SE_RTOS_Project

/* Setup DMA UART RX support, but do not queue descriptors yet */
static void dmaRXSetup(void)
{
	/* Setup UART 0 RX channel for the following configuration:
	   - Peripheral DMA request (UART 0 RX channel)
	   - Single transfer
	   - Low channel priority */
	Chip_DMA_EnableChannel(LPC_DMA, DMAREQ_USART0_RX);
	Chip_DMA_EnableIntChannel(LPC_DMA, DMAREQ_USART0_RX);
	Chip_DMA_SetupChannelConfig(LPC_DMA, DMAREQ_USART0_RX,
								(DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_SNGL | DMA_CFG_CHPRIORITY(3)));
}

Ejemplo n.º 2

Archivo: platform_spi.c Proyecto: HargicStudio/SmartCup_MiCOKit_v2.4.0.0

// Magicoe OSStatus platform_spi_init( const platform_spi_t* spi, const platform_spi_config_t* config )
OSStatus platform_spi_init( platform_spi_driver_t* driver, const platform_spi_t* peripheral, const platform_spi_config_t* config )
{
//  SPI_InitTypeDef   spi_init;
  OSStatus          err = kNoErr;
  platform_mcu_powersave_disable();
	uint32_t t1;	//general var
  require_action_quiet( ( peripheral != NULL ) && ( config != NULL ), exit, err = kParamErr);

  require_action_quiet( ( peripheral->port == LPC_SPI0 ), exit, err = kParamErr);


	driver->isRxDone = driver->isTxDone = 0;
	#ifndef NO_MICO_RTOS
	if (driver->sem_xfer_done == 0)
		mico_rtos_init_semaphore(&driver->sem_xfer_done, 1);
	#endif

   // >>> Init Pin mux
  	t1 = IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF;

	if (peripheral->port == LPC_SPI0)
	{
	  	if (config->speed >= 24000000)
	  		t1 |= 1UL<<9;	// enable fast slew
		g_pIO->PIO[0][11] = IOCON_FUNC1 | t1;/* SPI0_SCK */
		g_pIO->PIO[0][12] = IOCON_FUNC1 | t1;	/* SPI0_MOSI */
		g_pIO->PIO[0][13] = IOCON_FUNC1 | t1;	/* SPI0_MISO */
		// config CS pin as GPIO
		g_pIO->PIO[config->chip_select->port][config->chip_select->pin_number] = IOCON_FUNC0  | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF;
		platform_gpio_output_high(config->chip_select);
		platform_gpio_init(config->chip_select, OUTPUT_PUSH_PULL);
	}
	// <<<

	// >>>
	// initialize SPI peripheral
	{
		uint32_t bv;
		LPC_SPI_T *pSPI = peripheral->port;

		// >>>
		bv = pSPI == LPC_SPI0 ? 1UL << 9 : 1UL<<10;

		g_pASys->ASYNCAPBCLKCTRLSET = bv;	// enable clock to SPI

		g_pASys->ASYNCPRESETCTRLSET = bv;
		g_pASys->ASYNCPRESETCTRLCLR = bv;
		// <<<

		//			predly | postDly| fraDly | xferDly
		pSPI->DLY = 1UL<<0 | 1UL<<4 | 1UL<<8 | 1UL<<12;
        pSPI->DLY = 0;

		t1 = Chip_Clock_GetAsyncSyscon_ClockRate();
		t1 = (t1 + config->speed - 1) / config->speed;
		pSPI->DIV = t1 - 1;	// proper division

		pSPI->TXCTRL = (config->bits - 1) << 24;	// 8 bits per frame

		//   Enable | master | no loopback
		t1 = 1UL<<0 | 1UL<<2 | 0UL<<7;
		// determine SPI mode
		if (config->mode & SPI_CLOCK_IDLE_HIGH) {
			t1 |= 1UL<<5;	// CPOL = 1
			if (t1 & SPI_CLOCK_RISING_EDGE)
				t1 |= 1UL<<4;	// CPHA = 1
		} else {
			if (!(t1 & SPI_CLOCK_RISING_EDGE))
				t1 |= 1UL<<4;
		}
		pSPI->CFG = t1;
	}
	// <<<

	g_pDMA->DMACOMMON[0].ENABLESET = (1UL<<peripheral->dmaRxChnNdx) | (1UL<<peripheral->dmaTxChnNdx);
	g_pDMA->DMACOMMON[0].INTENSET = (1UL<<peripheral->dmaRxChnNdx) | (1UL<<peripheral->dmaTxChnNdx);

	g_pDMA->DMACH[peripheral->dmaRxChnNdx].CFG = DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_SNGL | DMA_CFG_CHPRIORITY(1);
	g_pDMA->DMACH[peripheral->dmaTxChnNdx].CFG = DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_SNGL | DMA_CFG_CHPRIORITY(1);

exit:
  platform_mcu_powersave_enable();
  return err;
}