void gdma1_check_mpu_violation(u32 addr, int wr_vio)
{
printk(KERN_CRIT "GDMA1 checks EMI MPU violation.\n");
printk(KERN_CRIT "addr = 0x%x, %s violation.\n", addr, wr_vio? "Write": "Read");
printk(KERN_CRIT "DMA SRC = 0x%x.\n", readl(DMA_SRC(DMA_BASE_CH(0))));
printk(KERN_CRIT "DMA DST = 0x%x.\n", readl(DMA_DST(DMA_BASE_CH(0))));
printk(KERN_CRIT "DMA COUNT = 0x%x.\n", readl(DMA_LEN1(DMA_BASE_CH(0))));
printk(KERN_CRIT "DMA CON = 0x%x.\n", readl(DMA_CON(DMA_BASE_CH(0))));
}
int buf_pop (circbuf_t * buf, char *dest, unsigned int len)
{
unsigned int i;
char *p = buf->top;
char *end = buf->end;
char *data = buf->data;
char *q = dest;
//u32 dma_con = 0;
if (len == 0)
return 0;
/* Cap to number of bytes in buffer */
if (len > buf->size)
len = buf->size;
#if 0
/* dma setting */
__raw_writel (p, DMA_SRC (USB_FULL_DMA1_BASE)); /* SOURCE */
__raw_writel (dest, DMA_DST (USB_FULL_DMA1_BASE)); /* DESTINATION */
__raw_writel (end - p, DMA_WPPT (USB_FULL_DMA1_BASE)); /* wrapping point */
__raw_writel (data, DMA_WPTO (USB_FULL_DMA1_BASE)); /* wrapping destination */
__raw_writel (len, DMA_COUNT (USB_FULL_DMA1_BASE));
dma_con = DMA_CON_WPEN | DMA_CON_BURST_16BEAT | DMA_CON_SINC
| DMA_CON_DINC | DMA_CON_SIZE_BYTE;
__raw_writel (dma_con, DMA_CON (USB_FULL_DMA1_BASE));
__raw_writel (DMA_START_BIT, DMA_START (USB_FULL_DMA1_BASE));
//printf("USB DMA Start!\n");
while (__raw_readl (DMA_GLBSTA_L) & DMA_GLBSTA_RUN (1));
//printf("USB DMA Complete\n");
__raw_writel (DMA_STOP_BIT, DMA_START (USB_FULL_DMA1_BASE));
__raw_writel (DMA_ACKINT_BIT, DMA_ACKINT (USB_FULL_DMA1_BASE));
p += len;
if (p >= end)
p = data + (p - end);
#else
for (i = 0; i < len; i++)
{
*q = *p;
p++;
if (p == end)
p = data;
q++;
}
#endif
/* Update 'top' pointer */
buf->top = p;
buf->size -= len;
return len;
}
int buf_push (circbuf_t * buf, const char *src, unsigned int len)
{
/* NOTE: this function allows push to overwrite old data. */
unsigned int i;
//u32 dma_con = 0;
char *p = buf->tail;
char *end = buf->end;
char *data = buf->data;
char *q = (char *)src;
#if 0
/* dma setting */
__raw_writel (src, DMA_SRC (USB_FULL_DMA0_BASE)); /* source */
__raw_writel (p, DMA_DST (USB_FULL_DMA0_BASE)); /* destination */
__raw_writel (end - p, DMA_WPPT (USB_FULL_DMA0_BASE)); /* wrapping point */
__raw_writel (data, DMA_WPTO (USB_FULL_DMA0_BASE)); /* wrapping destination */
__raw_writel (len, DMA_COUNT (USB_FULL_DMA0_BASE));
dma_con =
DMA_CON_WPEN | DMA_CON_WPSD | DMA_CON_BURST_16BEAT | DMA_CON_SINC |
DMA_CON_DINC | DMA_CON_SIZE_BYTE;
__raw_writel (dma_con, DMA_CON (USB_FULL_DMA0_BASE));
__raw_writel (DMA_START_BIT, DMA_START (USB_FULL_DMA0_BASE));
//printf("USB DMA Start!\n");
while (__raw_readl (DMA_GLBSTA_L) & DMA_GLBSTA_RUN (0));
//printf("USB DMA Complete\n");
__raw_writel (DMA_STOP_BIT, DMA_START (USB_FULL_DMA0_BASE));
__raw_writel (DMA_ACKINT_BIT, DMA_ACKINT (USB_FULL_DMA0_BASE));
p += len;
if (p >= end)
{
p = data + (p - end);
}
#else
for (i = 0; i < len; i++)
{
*p = *q;
p++;
if (p == end)
p = data;
q++;
}
#endif
buf->size += len;
/* Update 'tail' pointer */
buf->tail = p;
return len;
}
int mt65xx_config_gdma(int channel, struct mt65xx_gdma_conf *config, DMA_CONF_FLAG flag)
{
unsigned int dma_con = 0x0, limiter = 0;
if ((channel < GDMA_START) || (channel >= (GDMA_START + NR_GDMA_CHANNEL))) {
return -DMA_ERR_INVALID_CH;
}
if (dma_ctrl[channel].in_use == 0) {
return -DMA_ERR_CH_FREE;
}
if (!config) {
return -DMA_ERR_INV_CONFIG;
}
// if (!(config->sinc) && ((config->src) % 8)) {
// printk("GDMA fixed address mode requires 8-bytes aligned address\n");
if (!config->sinc)
{
printk("GMDA fixed adress mode doesn't support\n");
return -DMA_ERR_INV_CONFIG;
}
// if (!(config->dinc) && ((config->dst) % 8)) {
// printk("GDMA fixed address mode requires 8-bytes aligned address\n");
if (!config->dinc)
{
printk("GMDA fixed adress mode doesn't support\n");
return -DMA_ERR_INV_CONFIG;
}
switch (flag) {
case ALL:
writel(config->src, DMA_SRC(DMA_BASE_CH(channel)));
writel(config->dst, DMA_DST(DMA_BASE_CH(channel)));
writel((config->wplen) & DMA_GDMA_LEN_MAX_MASK, DMA_LEN2(DMA_BASE_CH(channel)));
writel(config->wpto, DMA_JUMP_ADDR(DMA_BASE_CH(channel)));
writel((config->count) & DMA_GDMA_LEN_MAX_MASK, DMA_LEN1(DMA_BASE_CH(channel)));
/*setup coherence bus*/
if (config->cohen){
writel((DMA_READ_COHER_BIT|readl(DMA_AXIATTR(DMA_BASE_CH(channel)))), DMA_AXIATTR(DMA_BASE_CH(channel)));
writel((DMA_WRITE_COHER_BIT|readl(DMA_AXIATTR(DMA_BASE_CH(channel)))), DMA_AXIATTR(DMA_BASE_CH(channel)));
}
/*setup security channel */
if (config->sec){
printk("1:GMDA GSEC:%x, ChSEC:%x\n",readl(DMA_GLOBAL_GSEC_EN),readl(DMA_GDMA_SEC_EN(channel)));
writel((DMA_GSEC_EN_BIT|readl(DMA_GLOBAL_GSEC_EN)), DMA_GLOBAL_GSEC_EN);
writel((DMA_SEC_EN_BIT|readl(DMA_GDMA_SEC_EN(channel))), DMA_GDMA_SEC_EN(channel));
printk("2:GMDA GSEC:%x, ChSEC:%x\n",readl(DMA_GLOBAL_GSEC_EN),readl(DMA_GDMA_SEC_EN(channel)));
}
else
{
printk("1:GMDA GSEC:%x, ChSEC:%x\n",readl(DMA_GLOBAL_GSEC_EN),readl(DMA_GDMA_SEC_EN(channel)));
writel(((~DMA_GSEC_EN_BIT)&readl(DMA_GLOBAL_GSEC_EN)), DMA_GLOBAL_GSEC_EN);
printk("2:GMDA GSEC:%x, ChSEC:%x\n",readl(DMA_GLOBAL_GSEC_EN),readl(DMA_GDMA_SEC_EN(channel)));
}
if (config->wpen) {
dma_con |= DMA_CON_WPEN;
}
if (config->wpsd) {
dma_con |= DMA_CON_WPSD;
}
if (config->iten) {
writel(DMA_INT_EN_BIT, DMA_INT_EN(DMA_BASE_CH(channel)));
}else {
writel(DMA_INT_EN_CLR_BIT, DMA_INT_EN(DMA_BASE_CH(channel)));
}
if (config->dinc && config->sinc) {
dma_con |= (config->burst & DMA_CON_BURST_MASK);
}else {
if (!(config->dinc)) {
dma_con |= DMA_CON_DFIX;
dma_con |= DMA_CON_WSIZE_1BYTE;
}
if (!(config->sinc)) {
dma_con |= DMA_CON_SFIX;
dma_con |= DMA_CON_RSIZE_1BYTE;
}
// fixed src/dst mode only supports burst type SINGLE
dma_con |= DMA_CON_BURST_SINGLE;
}
if (config->limiter) {
limiter = (config->limiter) & DMA_CON_SLOW_MAX_MASK;
dma_con |= limiter << DMA_CON_SLOW_OFFSET;
dma_con |= DMA_CON_SLOW_EN;
}
writel(dma_con, DMA_CON(DMA_BASE_CH(channel)));
break;
case SRC:
writel(config->src, DMA_SRC(DMA_BASE_CH(channel)));
break;
case DST:
writel(config->dst, DMA_DST(DMA_BASE_CH(channel)));
break;
case SRC_AND_DST:
writel(config->src, DMA_SRC(DMA_BASE_CH(channel)));
writel(config->dst, DMA_DST(DMA_BASE_CH(channel)));
break;
default:
break;
}
/* use the data synchronization barrier to ensure that all writes are completed */
dsb();
return 0;
}
