void AudioInputI2SQuad::begin(void)
{
dma.begin(true); // Allocate the DMA channel first
// TODO: should we set & clear the I2S_RCSR_SR bit here?
AudioOutputI2SQuad::config_i2s();
CORE_PIN13_CONFIG = PORT_PCR_MUX(4); // pin 13, PTC5, I2S0_RXD0
CORE_PIN30_CONFIG = PORT_PCR_MUX(4); // pin 30, PTC11, I2S0_RXD1
#if defined(KINETISK)
dma.TCD->SADDR = &I2S0_RDR0;
dma.TCD->SOFF = 4;
dma.TCD->ATTR = DMA_TCD_ATTR_SSIZE(1) | DMA_TCD_ATTR_SMOD(3) | DMA_TCD_ATTR_DSIZE(1);
dma.TCD->NBYTES_MLNO = 4;
dma.TCD->SLAST = 0;
dma.TCD->DADDR = i2s_rx_buffer;
dma.TCD->DOFF = 2;
dma.TCD->CITER_ELINKNO = sizeof(i2s_rx_buffer) / 4;
dma.TCD->DLASTSGA = -sizeof(i2s_rx_buffer);
dma.TCD->BITER_ELINKNO = sizeof(i2s_rx_buffer) / 4;
dma.TCD->CSR = DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_INTMAJOR;
#endif
dma.triggerAtHardwareEvent(DMAMUX_SOURCE_I2S0_RX);
update_responsibility = update_setup();
dma.enable();
I2S0_RCSR |= I2S_RCSR_RE | I2S_RCSR_BCE | I2S_RCSR_FRDE | I2S_RCSR_FR;
I2S0_TCSR |= I2S_TCSR_TE | I2S_TCSR_BCE; // TX clock enable, because sync'd to TX
dma.attachInterrupt(isr);
}
// Setup connection to other side
// - Only supports a single slave and master
// - If USB has been initiallized at this point, this side is the master
// - If both sides assert master, flash error leds
void Connect_setup( uint8_t master )
{
// Indication that UARTs are not ready
uarts_configured = 0;
// Register Connect CLI dictionary
CLI_registerDictionary( uartConnectCLIDict, uartConnectCLIDictName );
// Check if master
Connect_master = master;
if ( Connect_master )
Connect_id = 0; // 0x00 is always the master Id
// UART0 setup
// UART1 setup
// Setup the the UART interface for keyboard data input
SIM_SCGC4 |= SIM_SCGC4_UART0; // Disable clock gating
SIM_SCGC4 |= SIM_SCGC4_UART1; // Disable clock gating
// Pin Setup for UART0 / UART1
PORTA_PCR1 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(2); // RX Pin
PORTA_PCR2 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(2); // TX Pin
PORTE_PCR0 = PORT_PCR_PE | PORT_PCR_PS | PORT_PCR_PFE | PORT_PCR_MUX(3); // RX Pin
PORTE_PCR1 = PORT_PCR_DSE | PORT_PCR_SRE | PORT_PCR_MUX(3); // TX Pin
// Baud Rate setting
UART0_BDH = (uint8_t)(Connect_baud >> 8);
UART0_BDL = (uint8_t)Connect_baud;
UART0_C4 = Connect_baudFine;
UART1_BDH = (uint8_t)(Connect_baud >> 8);
UART1_BDL = (uint8_t)Connect_baud;
UART1_C4 = Connect_baudFine;
// 8 bit, Even Parity, Idle Character bit after stop
// NOTE: For 8 bit with Parity you must enable 9 bit transmission (pg. 1065)
// You only need to use UART0_D for 8 bit reading/writing though
// UART_C1_M UART_C1_PE UART_C1_PT UART_C1_ILT
UART0_C1 = UART_C1_M | UART_C1_PE | UART_C1_ILT;
UART1_C1 = UART_C1_M | UART_C1_PE | UART_C1_ILT;
// Only using Tx Fifos
UART0_PFIFO = UART_PFIFO_TXFE;
UART1_PFIFO = UART_PFIFO_TXFE;
// Setup DMA clocks
SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
SIM_SCGC7 |= SIM_SCGC7_DMA;
// Start with channels disabled first
DMAMUX0_CHCFG0 = 0;
DMAMUX0_CHCFG1 = 0;
// Configure DMA channels
//DMA_DSR_BCR0 |= DMA_DSR_BCR_DONE_MASK; // TODO What's this?
DMA_TCD0_CSR = 0;
DMA_TCD1_CSR = 0;
// Default control register
DMA_CR = 0;
// DMA Priority
DMA_DCHPRI0 = 0; // Ch 0, priority 0
DMA_DCHPRI1 = 1; // ch 1, priority 1
// Clear error interrupts
DMA_EEI = 0;
// Setup TCD
DMA_TCD0_SADDR = (uint32_t*)&UART0_D;
DMA_TCD1_SADDR = (uint32_t*)&UART1_D;
DMA_TCD0_SOFF = 0;
DMA_TCD1_SOFF = 0;
// No modulo, 8-bit transfer size
DMA_TCD0_ATTR = DMA_TCD_ATTR_SMOD(0) | DMA_TCD_ATTR_SSIZE(0) | DMA_TCD_ATTR_DMOD(0) | DMA_TCD_ATTR_DSIZE(0);
DMA_TCD1_ATTR = DMA_TCD_ATTR_SMOD(0) | DMA_TCD_ATTR_SSIZE(0) | DMA_TCD_ATTR_DMOD(0) | DMA_TCD_ATTR_DSIZE(0);
// One byte transferred at a time
DMA_TCD0_NBYTES_MLNO = 1;
DMA_TCD1_NBYTES_MLNO = 1;
// Source address does not change
DMA_TCD0_SLAST = 0;
DMA_TCD1_SLAST = 0;
// Destination buffer
DMA_TCD0_DADDR = (uint32_t*)uart_rx_buf[0].buffer;
DMA_TCD1_DADDR = (uint32_t*)uart_rx_buf[1].buffer;
// Incoming byte, increment by 1 in the rx buffer
DMA_TCD0_DOFF = 1;
DMA_TCD1_DOFF = 1;
// Single major loop, must be the same value
DMA_TCD0_CITER_ELINKNO = UART_Buffer_Size;
DMA_TCD1_CITER_ELINKNO = UART_Buffer_Size;
DMA_TCD0_BITER_ELINKNO = UART_Buffer_Size;
DMA_TCD1_BITER_ELINKNO = UART_Buffer_Size;
// Reset buffer when full
DMA_TCD0_DLASTSGA = -( UART_Buffer_Size );
DMA_TCD1_DLASTSGA = -( UART_Buffer_Size );
// Enable DMA channels
DMA_ERQ |= DMA_ERQ_ERQ0 | DMA_ERQ_ERQ1;
// Setup DMA channel routing
DMAMUX0_CHCFG0 = DMAMUX_ENABLE | DMAMUX_SOURCE_UART0_RX;
DMAMUX0_CHCFG1 = DMAMUX_ENABLE | DMAMUX_SOURCE_UART1_RX;
// Enable DMA requests (requires Rx interrupts)
UART0_C5 = UART_C5_RDMAS;
UART1_C5 = UART_C5_RDMAS;
// TX Enabled, RX Enabled, RX Interrupt Enabled
UART0_C2 = UART_C2_TE | UART_C2_RE | UART_C2_RIE;
UART1_C2 = UART_C2_TE | UART_C2_RE | UART_C2_RIE;
// Add interrupts to the vector table
NVIC_ENABLE_IRQ( IRQ_UART0_STATUS );
NVIC_ENABLE_IRQ( IRQ_UART1_STATUS );
// UARTs are now ready to go
uarts_configured = 1;
// Reset the state of the UART variables
Connect_reset();
}
