static void setup_rcrb(const int peg_enabled)
{
/*\ RCRB setup: Egress Port \*/
/* Set component ID of MCH (1). */
EPBAR8(EPESD + 2) = 1;
/* Link1: component ID 1, link valid. */
EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0);
EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
if (peg_enabled)
/* Link2: link_valid. */
EPBAR8(EPLE2D) |= (1 << 0); /* link valid */
/*\ RCRB setup: DMI Port \*/
/* Set component ID of MCH (1). */
DMIBAR8(DMIESD + 2) = 1;
/* Link1: target port 0, component id 2 (ICH), link valid. */
DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0);
DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA;
/* Link2: component ID 1 (MCH), link valid */
DMIBAR32(DMILE2D) =
(DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0);
DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR;
}
static void init_dmi(void)
{
/* VC0: TC0 only */
DMIBAR8(DMIVC0RCTL) = 1;
DMIBAR8(0x4) = 1;
/* VC1: ID1, TC7 */
DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
DMIBAR8(DMIVC1RCTL) = 1 << 7;
/* VC1: enable */
DMIBAR32(DMIVC1RCTL) |= 1 << 31;
// Hangs
//while ((DMIBAR8(0x26) & 2) != 0) ;
//printk(BIOS_DEBUG, "Done DMI loop\n");
DMIBAR32(0x0028) = 0x00000001;
DMIBAR32(0x002c) = 0x86000000;
DMIBAR32(0x0040) = 0x08010005;
DMIBAR32(0x0044) = 0x01010202;
DMIBAR32(0x0050) = 0x00020001;
DMIBAR32(0x0058) = DEFAULT_RCBA;
DMIBAR32(0x0060) = 0x00010001;
DMIBAR32(0x0068) = DEFAULT_EPBAR;
DMIBAR32(0x0080) = 0x00010006;
DMIBAR32(0x0084) = 0x00012c41;
DMIBAR32(0x0088) = 0x00410000;
DMIBAR32(0x00f0) = 0x00012000;
DMIBAR32(0x00f4) = 0x33fe0037;
DMIBAR32(0x00fc) = 0xf000f004;
DMIBAR32(0x01b0) = 0x00400000;
DMIBAR32(0x01b4) = 0x00008000;
DMIBAR32(0x01b8) = 0x000018f2;
DMIBAR32(0x01bc) = 0x00000018;
DMIBAR32(0x01cc) = 0x00060010;
DMIBAR32(0x01d4) = 0x00002000;
DMIBAR32(0x0200) = 0x00400f26;
DMIBAR32(0x0204) = 0x0001313f;
DMIBAR32(0x0208) = 0x00007cb0;
DMIBAR32(0x0210) = 0x00000101;
DMIBAR32(0x0214) = 0x0007000f;
DMIBAR32(0x0224) = 0x00030005;
DMIBAR32(0x0230) = 0x2800000e;
DMIBAR32(0x0234) = 0x4abcb5bc;
DMIBAR32(0x0250) = 0x00000007;
DMIBAR32(0x0c00) = 0x0000003c;
DMIBAR32(0x0c04) = 0x16000000;
DMIBAR32(0x0c0c) = 0x00001fff;
DMIBAR32(0x0c10) = 0x0000b100;
DMIBAR32(0x0c24) = 0xffff0038;
DMIBAR32(0x0c28) = 0x0000000e;
DMIBAR32(0x0c2c) = 0x003c0008;
DMIBAR32(0x0c30) = 0x02000180;
DMIBAR32(0x0c34) = 0x10040071;
DMIBAR32(0x0d60) = 0x00000001;
DMIBAR32(0x0d6c) = 0x00000300;
DMIBAR32(0x0d74) = 0x00000020;
DMIBAR32(0x0d78) = 0x00220000;
DMIBAR32(0x0d7c) = 0x111f727c;
DMIBAR32(0x0d80) = 0x00001409;
DMIBAR32(0x0d88) = 0x000f1867;
DMIBAR32(0x0d8c) = 0x013000fc;
DMIBAR32(0x0da4) = 0x00009757;
DMIBAR32(0x0da8) = 0x00000078;
DMIBAR32(0x0e00) = 0x000d034e;
DMIBAR32(0x0e04) = 0x01880880;
DMIBAR32(0x0e08) = 0x01000060;
DMIBAR32(0x0e0c) = 0x00000080;
DMIBAR32(0x0e10) = 0xbe000000;
DMIBAR32(0x0e18) = 0x000000e3;
DMIBAR32(0x0e20) = 0x000d034e;
DMIBAR32(0x0e24) = 0x01880880;
DMIBAR32(0x0e28) = 0x01000060;
DMIBAR32(0x0e2c) = 0x00000080;
DMIBAR32(0x0e30) = 0xbe000000;
DMIBAR32(0x0e38) = 0x000000e3;
DMIBAR32(0x0e40) = 0x000d034e;
DMIBAR32(0x0e44) = 0x01880880;
DMIBAR32(0x0e48) = 0x01000060;
DMIBAR32(0x0e4c) = 0x00000080;
DMIBAR32(0x0e50) = 0xbe000000;
DMIBAR32(0x0e58) = 0x000000e3;
DMIBAR32(0x0e60) = 0x000d034e;
DMIBAR32(0x0e64) = 0x01880880;
DMIBAR32(0x0e68) = 0x01000060;
DMIBAR32(0x0e6c) = 0x00000080;
DMIBAR32(0x0e70) = 0xbe000000;
DMIBAR32(0x0e78) = 0x000000e3;
DMIBAR32(0x0e14) = 0xce00381b;
DMIBAR32(0x0e34) = 0x4000781b;
DMIBAR32(0x0e54) = 0x5c00781b;
DMIBAR32(0x0e74) = 0x5400381b;
DMIBAR32(0x0218) = 0x0b6202c1;
DMIBAR32(0x021c) = 0x02c202c2;
DMIBAR32(0x0334) = 0x00b904b3;
DMIBAR32(0x0338) = 0x004e0000;
DMIBAR32(0x0300) = 0x00a70f4c;
DMIBAR32(0x0304) = 0x00a90f54;
DMIBAR32(0x0308) = 0x00d103c4;
DMIBAR32(0x030c) = 0x003c0e10;
DMIBAR32(0x0310) = 0x003d0e11;
DMIBAR32(0x0314) = 0x00640000;
DMIBAR32(0x0318) = 0x00320c86;
DMIBAR32(0x031c) = 0x003a0ca6;
DMIBAR32(0x0324) = 0x00040010;
DMIBAR32(0x0328) = 0x00040000;
EPBAR32(0x40) = 0x00010005;
EPBAR32(0x44) = 0x00010301;
EPBAR32(0x50) = 0x01010001;
EPBAR32(0x58) = DEFAULT_DMIBAR;
EPBAR32(0x60) = 0x02010003;
EPBAR32(0x68) = 0x00008000;
EPBAR32(0x70) = 0x03000002;
EPBAR32(0x78) = 0x00030000;
}
static void pineview_setup_bars(void)
{
u8 reg8;
u16 reg16;
u32 reg32;
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */
pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(LPC, 0x4c /* GC */ , 0x10); /* Enable GPIOs */
pci_write_config32(LPC, 0x88, 0x007c0291);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
printk(BIOS_DEBUG, " done.\n");
printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
printk(BIOS_DEBUG, " done.\n");
/* Enable upper 128bytes of CMOS */
RCBA32(0x3400) = (1 << 2);
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
pci_write_config8(D0F0, 0x8, 0x69);
/* Set up all hardcoded northbridge BARs */
pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1);
reg32 = MCHBAR32(0x30);
MCHBAR32(0x30) = 0x21800;
DMIBAR32(0x2c) = 0x86000040;
pci_write_config8(D0F0, DEVEN, 0x09);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000);
reg8 = pci_read_config8(D0F0, 0xe5); // 0x10
reg16 = pci_read_config16(PCI_DEV(0, 0x02, 0), 0x0); // 0x8086
reg16 = pci_read_config16(D0F0, GGC);
pci_write_config16(D0F0, GGC, 0x130);
reg16 = pci_read_config16(D0F0, GGC);
pci_write_config16(D0F0, GGC, 0x130);
MCHBAR8(0xb08) = 0x20;
reg8 = pci_read_config8(D0F0, 0xe6); // 0x11
reg16 = MCHBAR16(0xc8c);
MCHBAR16(0xc8c) = reg16 | 0x0200;
reg8 = MCHBAR8(0xc8c);
MCHBAR8(0xc8c) = reg8;
MCHBAR8(0xc8c) = 0x12;
pci_write_config8(PCI_DEV(0, 0x02, 0), 0x62, 0x02);
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe8, 0x8000);
MCHBAR32(0x3004) = 0x48000000;
MCHBAR32(0x3008) = 0xfffffe00;
MCHBAR32(0xb08) = 0x06028220;
MCHBAR32(0xff4) = 0xc6db8b5f;
MCHBAR16(0xff8) = 0x024f;
// PLL Voltage controlled oscillator
//MCHBAR8(0xc38) = 0x04;
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xcc, 0x014d);
reg32 = MCHBAR32(0x40);
MCHBAR32(0x40) = 0x0;
reg32 = MCHBAR32(0x40);
MCHBAR32(0x40) = 0x8;
pci_write_config8(LPC, 0x8, 0x1d);
pci_write_config8(LPC, 0x8, 0x0);
RCBA32(0x3410) = 0x00020465;
RCBA32(0x88) = 0x0011d000;
RCBA32(0x1fc) = 0x60f;
RCBA32(0x1f4) = 0x86000040;
RCBA32(0x214) = 0x10030509;
RCBA32(0x218) = 0x00020504;
RCBA32(0x220) = 0xc5;
RCBA32(0x3430) = 0x1;
RCBA32(0x2027) = 0x38f6a70d;
RCBA16(0x3e08) = 0x0080;
RCBA16(0x3e48) = 0x0080;
RCBA32(0x3e0e) = 0x00000080;
RCBA32(0x3e4e) = 0x00000080;
RCBA32(0x2034) = 0xb24577cc;
RCBA32(0x1c) = 0x03128010;
RCBA32(0x2010) = 0x400;
RCBA32(0x3400) = 0x4;
RCBA32(0x2080) = 0x18006007;
RCBA32(0x20a0) = 0x18006007;
RCBA32(0x20c0) = 0x18006007;
RCBA32(0x20e0) = 0x18006007;
pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1);
RCBA32(0x3100) = 0x42210;
RCBA32(0x3108) = 0x10004321;
RCBA32(0x310c) = 0x00214321;
RCBA32(0x3110) = 0x1;
RCBA32(0x3140) = 0x01460132;
RCBA32(0x3142) = 0x02370146;
RCBA32(0x3144) = 0x32010237;
RCBA32(0x3146) = 0x01463201;
RCBA32(0x3148) = 0x146;
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(D0F0, PAM0, 0x30);
pci_write_config8(D0F0, PAM1, 0x33);
pci_write_config8(D0F0, PAM2, 0x33);
pci_write_config8(D0F0, PAM3, 0x33);
pci_write_config8(D0F0, PAM4, 0x33);
pci_write_config8(D0F0, PAM5, 0x33);
pci_write_config8(D0F0, PAM6, 0x33);
pci_write_config32(D0F0, SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
printk(BIOS_DEBUG, " done.\n");
}
static void dmi_config(void)
{
DMIBAR32(0x0218) = 0x06aa0b0c;
DMIBAR32(0x021c) = 0x0b0d0b0d;
DMIBAR32(0x0300) = 0x0011028d;
DMIBAR32(0x0304) = 0x002102cd;
DMIBAR32(0x030c) = 0x007d004b;
DMIBAR32(0x0310) = 0x007e004c;
DMIBAR32(0x0318) = 0x002304ad;
DMIBAR32(0x031c) = 0x003304ed;
DMIBAR32(0x03b8) = 0x005c05a4;
DMIBAR32(0x03bc) = 0x006c05e4;
DMIBAR32(0x0530) = 0x41d3b000;
DMIBAR32(0x0534) = 0x00019f80;
DMIBAR32(0x0ba4) = 0x0000000d;
DMIBAR32(0x0d80) = 0x1c9cfc0b;
DMIBAR32(0x0e1c) = 0x20000000;
DMIBAR32(0x0e2c) = 0x20000000;
}
/* b2step: b2 stepping or higher */
static void init_dmi(int b2step)
{
/* VC0: TC0 only */
DMIBAR8(DMIVC0RCTL) &= 1;
DMIBAR8(0x4) = (DMIBAR8(0x4) & ~7) | 1;
/* VC1: ID1, TC7 */
DMIBAR32(0x20) = (DMIBAR32(0x20) & ~(7 << 24)) | (1 << 24);
DMIBAR8(0x20) = (DMIBAR8(0x20) & 1) | (1 << 7);
/* VC1: enable */
DMIBAR32(0x20) |= 1 << 31;
while ((DMIBAR8(0x26) & 2) != 0) ;
/* additional configuration. */
DMIBAR32(0x200) |= 3 << 13;
DMIBAR32(0x200) &= ~(1 << 21);
DMIBAR32(0x200) = (DMIBAR32(0x200) & ~(3 << 26)) | (2 << 26);
DMIBAR32(0x2c) = 0x86000040;
DMIBAR32(0xfc) |= 1 << 0;
DMIBAR32(0xfc) |= 1 << 1;
DMIBAR32(0xfc) |= 1 << 4;
if (!b2step) {
DMIBAR32(0xfc) |= 1 << 11;
} else {
DMIBAR32(0xfc) &= ~(1 << 11);
}
DMIBAR32(0x204) &= ~(3 << 10);
DMIBAR32(0xf4) &= ~(1 << 4);
DMIBAR32(0xf0) |= 3 << 24;
DMIBAR32(0xf04) = 0x07050880;
DMIBAR32(0xf44) = 0x07050880;
DMIBAR32(0xf84) = 0x07050880;
DMIBAR32(0xfc4) = 0x07050880;
/* lock down write-once registers
DMIBAR32(0x84) will be set in setup_aspm(). */
DMIBAR32(0x308) = DMIBAR32(0x308);
DMIBAR32(0x314) = DMIBAR32(0x314);
DMIBAR32(0x324) = DMIBAR32(0x324);
DMIBAR32(0x328) = DMIBAR32(0x328);
DMIBAR32(0x334) = DMIBAR32(0x334);
DMIBAR32(0x338) = DMIBAR32(0x338);
}
static void setup_aspm(const stepping_t stepping, const int peg_enabled)
{
u32 tmp32;
const device_t pciex = PCI_DEV(0, 1, 0);
/* Prerequisites for ASPM: */
if (peg_enabled) {
tmp32 = pci_read_config32(pciex, 0x200) | (3 << 13);
pci_write_config32(pciex, 0x200, tmp32);
tmp32 = pci_read_config32(pciex, 0x0f0);
tmp32 &= ~((1 << 27) | (1 << 26));
pci_write_config32(pciex, 0x0f0, tmp32);
tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24);
pci_write_config32(pciex, 0x0f0, tmp32);
tmp32 = pci_read_config32(pciex, 0x0f4) & ~(1 << 4);
pci_write_config32(pciex, 0x0f4, tmp32);
tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 0);
pci_write_config32(pciex, 0x0fc, tmp32);
tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 1);
pci_write_config32(pciex, 0x0fc, tmp32);
tmp32 = pci_read_config32(pciex, 0x0fc) | (1 << 4);
pci_write_config32(pciex, 0x0fc, tmp32);
tmp32 = pci_read_config32(pciex, 0x0fc) & ~(7 << 5);
pci_write_config32(pciex, 0x0fc, tmp32);
/* Set L0s, L1 supported in LCTL? */
tmp32 = pci_read_config32(pciex, 0x0b0) | (3 << 0);
pci_write_config32(pciex, 0x0b0, tmp32);
tmp32 = pci_read_config32(pciex, 0x0f0) | (3 << 24);
pci_write_config32(pciex, 0x0f0, tmp32);
tmp32 = pci_read_config32(pciex, 0x0f0);
if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1))
tmp32 |= (1 << 31);
else if (stepping >= STEPPING_B2)
tmp32 &= ~(1 << 31);
pci_write_config32(pciex, 0x0f0, tmp32);
tmp32 = pci_read_config32(pciex, 0x0fc);
if ((stepping >= STEPPING_B0) && (stepping <= STEPPING_B1))
tmp32 |= (1 << 10);
else if (stepping >= STEPPING_B2)
tmp32 &= ~(1 << 10);
pci_write_config32(pciex, 0x0fc, tmp32);
tmp32 = pci_read_config32(pciex, 0x0fc);
if (stepping >= STEPPING_B2)
tmp32 |= (1 << 14);
pci_write_config32(pciex, 0x0fc, tmp32);
tmp32 = pci_read_config32(pciex, 0x0fc);
if (stepping >= STEPPING_B1)
tmp32 &= ~(1 << 13);
pci_write_config32(pciex, 0x0fc, tmp32);
}
DMIBAR8 (0x0e1c) |= (1 << 0);
DMIBAR16(0x0f00) |= (3 << 8);
DMIBAR16(0x0f00) |= (7 << 3);
DMIBAR32(0x0f14) &= ~(1 << 17);
DMIBAR16(0x0e1c) &= ~(1 << 8);
if (stepping >= STEPPING_B0) {
DMIBAR32(0x0e28 + 4) = (DMIBAR32(0x0e28 + 4) &
~(0xf << (52 - 32))) |
(0xd << (52 - 32));
DMIBAR32(0x0e2c) = 0x88d07333;
}
if (peg_enabled) {
tmp32 = pci_read_config32(pciex, 0xa08) & ~(1 << 15);
pci_write_config32(pciex, 0xa08, tmp32);
tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8);
pci_write_config32(pciex, 0xa84, tmp32);
tmp32 = pci_read_config32(pciex, 0xb14) & ~(1 << 17);
pci_write_config32(pciex, 0xb14, tmp32);
tmp32 = pci_read_config32(pciex, 0xb00) | (3 << 8);
pci_write_config32(pciex, 0xb00, tmp32);
tmp32 = pci_read_config32(pciex, 0xb00) | (7 << 3);
pci_write_config32(pciex, 0xb00, tmp32);
tmp32 = pci_read_config32(pciex, 0xa84) & ~(1 << 8);
pci_write_config32(pciex, 0xa84, tmp32);
tmp32 = pci_read_config32(pciex, 0xa84) | (1 << 8);
pci_write_config32(pciex, 0xa84, tmp32);
tmp32 = pci_read_config32(pciex, 0xb04);
tmp32 = (tmp32 & ~(0x1f << 23)) | (0xe << 23);
pci_write_config32(pciex, 0xb04, tmp32);
tmp32 = pci_read_config32(pciex, 0xb04);
tmp32 |= (1 << 31);
pci_write_config32(pciex, 0xb04, tmp32);
tmp32 = pci_read_config32(pciex, 0xb04);
tmp32 = (tmp32 & ~(0x03 << 29)) | (0x1 << 29);
pci_write_config32(pciex, 0xb04, tmp32);
}
/*\ Setup ASPM on DMI \*/
/* Exit latencies should be checked to be supported by
the endpoint (ICH), but ICH doesn't give any limits. */
if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0)))
DMIBAR8(0x88) |= (3 << 0); // enable ASPM L0s, L1 (write-once)
else
DMIBAR8(0x88) |= (1 << 0); // enable ASPM L0s (write-once)
/* timing */
DMIBAR32(0x84) = (DMIBAR32(0x84) & ~(63 << 12)) | (2 << 12) | (2 << 15);
DMIBAR8(0x208 + 3) = 0;
DMIBAR32(0x208) &= ~(3 << 20);
/*\ Setup ASPM on PEG \*/
/*
* Maybe we just have to advertise ASPM through LCAP[11:10]
* (LCAP[17:15] == 010b is the default, will be locked, as it's R/WO),
* set 0x208[31:24,23:22] to zero, 0x224[24:21] = 1 and let the
* generic ASPM code do the rest? – Nico
*/
/* TODO: Prepare PEG for ASPM. */
}
static void init_dmi(void)
{
u32 reg32;
u16 reg16;
/* Assume IGD present */
/* Clear error status */
DMIBAR32(0x1c4) = 0xffffffff;
DMIBAR32(0x1d0) = 0xffffffff;
/* VC0: TC0 only */
DMIBAR8(DMIVC0RCTL) = 1;
DMIBAR8(0x4) = 1;
/* VC1: ID1, TC7 */
reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
reg32 = (reg32 & ~0xff) | 1 << 7;
/* VC1: enable */
reg32 |= 1 << 31;
reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17);
DMIBAR32(DMIVC1RCTL) = reg32;
/* Set up VCs in southbridge RCBA */
RCBA8(0x3022) &= ~1;
reg32 = (0x5 << 28) | (1 << 6); /* PCIe x4 */
RCBA32(0x2020) = (RCBA32(0x2020) & ~((0xf << 28) | (0x7 << 6))) | reg32;
/* Assign VC1 id 1 */
RCBA32(0x20) = (RCBA32(0x20) & ~(0x7 << 24)) | (1 << 24);
/* Map TC7 to VC1 */
RCBA8(0x20) &= 1;
RCBA8(0x20) |= 1 << 7;
/* Map TC0 to VC0 */
RCBA8(0x14) &= 1;
/* Init DMI VC1 port arbitration table */
RCBA32(0x20) &= 0xfff1ffff;
RCBA32(0x20) |= 1 << 19;
RCBA32(0x30) = 0x0000000f;
RCBA32(0x34) = 0x000f0000;
RCBA32(0x38) = 0;
RCBA32(0x3c) = 0x000000f0;
RCBA32(0x40) = 0x0f000000;
RCBA32(0x44) = 0;
RCBA32(0x48) = 0x0000f000;
RCBA32(0x4c) = 0;
RCBA32(0x50) = 0x0000000f;
RCBA32(0x54) = 0x000f0000;
RCBA32(0x58) = 0;
RCBA32(0x5c) = 0x000000f0;
RCBA32(0x60) = 0x0f000000;
RCBA32(0x64) = 0;
RCBA32(0x68) = 0x0000f000;
RCBA32(0x6c) = 0;
RCBA32(0x20) |= 1 << 16;
/* Enable VC1 */
RCBA32(0x20) |= 1 << 31;
/* Wait for VC1 */
while ((RCBA8(0x26) & (1 << 1)) != 0);
/* Wait for table load */
while ((RCBA8(0x26) & (1 << 0)) != 0);
/* ASPM on DMI link */
RCBA16(0x1a8) &= ~0x3;
reg16 = RCBA16(0x1a8);
RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10);
reg32 = RCBA32(0x2010);
/* Set up VC1 max time */
RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000;
while ((DMIBAR32(0x26) & (1 << 1)) != 0);
printk(BIOS_DEBUG, "Done DMI setup\n");
/* ASPM on DMI */
DMIBAR32(0x200) &= ~(0x3 << 26);
DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101;
DMIBAR32(0x88) &= ~0x3;
DMIBAR32(0x88) |= 0x3;
reg16 = DMIBAR16(0x88);
}
